aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--target-cris/translate.c29
-rw-r--r--target-mips/dsp_helper.c30
-rw-r--r--target-mips/translate.c7
-rw-r--r--target-sh4/cpu.h6
4 files changed, 24 insertions, 48 deletions
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 5faa44c1ea..f990d591c7 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -1133,7 +1133,7 @@ static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
cris_store_direct_jmp(dc);
}
- tcg_gen_qemu_ld64(dst, addr, mem_index);
+ tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ);
}
static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
@@ -1147,23 +1147,8 @@ static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
cris_store_direct_jmp(dc);
}
- if (size == 1) {
- if (sign) {
- tcg_gen_qemu_ld8s(dst, addr, mem_index);
- } else {
- tcg_gen_qemu_ld8u(dst, addr, mem_index);
- }
- } else if (size == 2) {
- if (sign) {
- tcg_gen_qemu_ld16s(dst, addr, mem_index);
- } else {
- tcg_gen_qemu_ld16u(dst, addr, mem_index);
- }
- } else if (size == 4) {
- tcg_gen_qemu_ld32u(dst, addr, mem_index);
- } else {
- abort();
- }
+ tcg_gen_qemu_ld_tl(dst, addr, mem_index,
+ MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
}
static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
@@ -1187,13 +1172,7 @@ static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
return;
}
- if (size == 1) {
- tcg_gen_qemu_st8(val, addr, mem_index);
- } else if (size == 2) {
- tcg_gen_qemu_st16(val, addr, mem_index);
- } else {
- tcg_gen_qemu_st32(val, addr, mem_index);
- }
+ tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
if (dc->flagx_known && dc->flags_x) {
cris_evaluate_flags(dc);
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index b088a25017..a2f46d9637 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -1088,12 +1088,11 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b)
target_ulong helper_##name(target_ulong rt, CPUMIPSState *env) \
{ \
DSP32Value dt; \
- unsigned int i, n; \
+ unsigned int i; \
\
- n = sizeof(DSP32Value) / sizeof(dt.element[0]); \
dt.sw[0] = rt; \
\
- for (i = 0; i < n; i++) { \
+ for (i = 0; i < ARRAY_SIZE(dt.element); i++) { \
dt.element[i] = mipsdsp_##func(dt.element[i], env); \
} \
\
@@ -1109,12 +1108,11 @@ MIPSDSP32_UNOP_ENV(absq_s_w, sat_abs32, sw)
target_ulong helper_##name(target_ulong rt, CPUMIPSState *env) \
{ \
DSP64Value dt; \
- unsigned int i, n; \
+ unsigned int i; \
\
- n = sizeof(DSP64Value) / sizeof(dt.element[0]); \
dt.sl[0] = rt; \
\
- for (i = 0; i < n; i++) { \
+ for (i = 0; i < ARRAY_SIZE(dt.element); i++) { \
dt.element[i] = mipsdsp_##func(dt.element[i], env); \
} \
\
@@ -1130,13 +1128,12 @@ MIPSDSP64_UNOP_ENV(absq_s_pw, sat_abs32, sw)
target_ulong helper_##name(target_ulong rs, target_ulong rt) \
{ \
DSP32Value ds, dt; \
- unsigned int i, n; \
+ unsigned int i; \
\
- n = sizeof(DSP32Value) / sizeof(ds.element[0]); \
ds.sw[0] = rs; \
dt.sw[0] = rt; \
\
- for (i = 0; i < n; i++) { \
+ for (i = 0; i < ARRAY_SIZE(ds.element); i++) { \
ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]); \
} \
\
@@ -1159,13 +1156,12 @@ target_ulong helper_##name(target_ulong rs, target_ulong rt, \
CPUMIPSState *env) \
{ \
DSP32Value ds, dt; \
- unsigned int i, n; \
+ unsigned int i; \
\
- n = sizeof(DSP32Value) / sizeof(ds.element[0]); \
ds.sw[0] = rs; \
dt.sw[0] = rt; \
\
- for (i = 0 ; i < n ; i++) { \
+ for (i = 0 ; i < ARRAY_SIZE(ds.element); i++) { \
ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \
} \
\
@@ -1192,13 +1188,12 @@ MIPSDSP32_BINOP_ENV(subu_s_qb, satu8_sub, ub);
target_ulong helper_##name(target_ulong rs, target_ulong rt) \
{ \
DSP64Value ds, dt; \
- unsigned int i, n; \
+ unsigned int i; \
\
- n = sizeof(DSP64Value) / sizeof(ds.element[0]); \
ds.sl[0] = rs; \
dt.sl[0] = rt; \
\
- for (i = 0 ; i < n ; i++) { \
+ for (i = 0 ; i < ARRAY_SIZE(ds.element); i++) { \
ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]); \
} \
\
@@ -1215,13 +1210,12 @@ target_ulong helper_##name(target_ulong rs, target_ulong rt, \
CPUMIPSState *env) \
{ \
DSP64Value ds, dt; \
- unsigned int i, n; \
+ unsigned int i; \
\
- n = sizeof(DSP64Value) / sizeof(ds.element[0]); \
ds.sl[0] = rs; \
dt.sl[0] = rt; \
\
- for (i = 0 ; i < n ; i++) { \
+ for (i = 0 ; i < ARRAY_SIZE(ds.element); i++) { \
ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \
} \
\
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 67f326b205..e30273438a 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15983,10 +15983,13 @@ void cpu_state_reset(CPUMIPSState *env)
if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
env->CP0_Status |= (1 << CP0St_MX);
}
- /* Enable 64-bit FPU if the target cpu supports it. */
- if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
+# if defined(TARGET_MIPS64)
+ /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
+ if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
+ (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
env->CP0_Status |= (1 << CP0St_FR);
}
+# endif
#else
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 276d2955c3..c181ddacf5 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -157,9 +157,6 @@ typedef struct CPUSH4State {
/* float point status register */
float_status fp_status;
- /* The features that we should emulate. See sh_features above. */
- uint32_t features;
-
/* Those belong to the specific unit (SH7750) but are handled here */
uint32_t mmucr; /* MMU control register */
uint32_t pteh; /* page table entry high register */
@@ -180,6 +177,9 @@ typedef struct CPUSH4State {
int id; /* CPU model */
+ /* The features that we should emulate. See sh_features above. */
+ uint32_t features;
+
void *intc_handle;
int in_sleep; /* SR_BL ignored during sleep */
memory_content *movcal_backup;
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-13 11:53:36 +0000