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-rw-r--r--MAINTAINERS1
-rw-r--r--configs/targets/loongarch64-softmmu.mak1
-rw-r--r--gdb-xml/loongarch-base64.xml44
-rw-r--r--gdb-xml/loongarch-fpu64.xml57
-rw-r--r--target/loongarch/cpu.c9
-rw-r--r--target/loongarch/gdbstub.c81
-rw-r--r--target/loongarch/internals.h4
-rw-r--r--target/loongarch/meson.build1
8 files changed, 198 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index e8938db694..954fb95218 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1137,6 +1137,7 @@ F: include/hw/intc/loongarch_*.h
F: hw/intc/loongarch_*.c
F: include/hw/pci-host/ls7a.h
F: hw/rtc/ls7a_rtc.c
+F: gdb-xml/loongarch*.xml
M68K Machines
-------------
diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak
index 666154022f..7bc06c850c 100644
--- a/configs/targets/loongarch64-softmmu.mak
+++ b/configs/targets/loongarch64-softmmu.mak
@@ -1,3 +1,4 @@
TARGET_ARCH=loongarch64
TARGET_BASE_ARCH=loongarch
TARGET_SUPPORTS_MTTCG=y
+TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.xml
diff --git a/gdb-xml/loongarch-base64.xml b/gdb-xml/loongarch-base64.xml
new file mode 100644
index 0000000000..4962bdbd28
--- /dev/null
+++ b/gdb-xml/loongarch-base64.xml
@@ -0,0 +1,44 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2021 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.loongarch.base">
+ <reg name="r0" bitsize="64" type="uint64" group="general"/>
+ <reg name="r1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r3" bitsize="64" type="uint64" group="general"/>
+ <reg name="r4" bitsize="64" type="uint64" group="general"/>
+ <reg name="r5" bitsize="64" type="uint64" group="general"/>
+ <reg name="r6" bitsize="64" type="uint64" group="general"/>
+ <reg name="r7" bitsize="64" type="uint64" group="general"/>
+ <reg name="r8" bitsize="64" type="uint64" group="general"/>
+ <reg name="r9" bitsize="64" type="uint64" group="general"/>
+ <reg name="r10" bitsize="64" type="uint64" group="general"/>
+ <reg name="r11" bitsize="64" type="uint64" group="general"/>
+ <reg name="r12" bitsize="64" type="uint64" group="general"/>
+ <reg name="r13" bitsize="64" type="uint64" group="general"/>
+ <reg name="r14" bitsize="64" type="uint64" group="general"/>
+ <reg name="r15" bitsize="64" type="uint64" group="general"/>
+ <reg name="r16" bitsize="64" type="uint64" group="general"/>
+ <reg name="r17" bitsize="64" type="uint64" group="general"/>
+ <reg name="r18" bitsize="64" type="uint64" group="general"/>
+ <reg name="r19" bitsize="64" type="uint64" group="general"/>
+ <reg name="r20" bitsize="64" type="uint64" group="general"/>
+ <reg name="r21" bitsize="64" type="uint64" group="general"/>
+ <reg name="r22" bitsize="64" type="uint64" group="general"/>
+ <reg name="r23" bitsize="64" type="uint64" group="general"/>
+ <reg name="r24" bitsize="64" type="uint64" group="general"/>
+ <reg name="r25" bitsize="64" type="uint64" group="general"/>
+ <reg name="r26" bitsize="64" type="uint64" group="general"/>
+ <reg name="r27" bitsize="64" type="uint64" group="general"/>
+ <reg name="r28" bitsize="64" type="uint64" group="general"/>
+ <reg name="r29" bitsize="64" type="uint64" group="general"/>
+ <reg name="r30" bitsize="64" type="uint64" group="general"/>
+ <reg name="r31" bitsize="64" type="uint64" group="general"/>
+ <reg name="pc" bitsize="64" type="code_ptr" group="general"/>
+ <reg name="badvaddr" bitsize="64" type="code_ptr" group="general"/>
+</feature>
diff --git a/gdb-xml/loongarch-fpu64.xml b/gdb-xml/loongarch-fpu64.xml
new file mode 100644
index 0000000000..e52cf89fbc
--- /dev/null
+++ b/gdb-xml/loongarch-fpu64.xml
@@ -0,0 +1,57 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2021 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.loongarch.fpu">
+
+ <union id="fpu64type">
+ <field name="f" type="ieee_single"/>
+ <field name="d" type="ieee_double"/>
+ </union>
+
+ <reg name="f0" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f1" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f2" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f3" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f4" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f5" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f6" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f7" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f8" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f9" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f10" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f11" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f12" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f13" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f14" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f15" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f16" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f17" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f18" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f19" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f20" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f21" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f22" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f23" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f24" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f25" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f26" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f27" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f28" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f29" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f30" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f31" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="fcc0" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc1" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc2" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc3" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc4" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc5" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc6" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc7" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcsr" bitsize="32" type="uint32" group="float"/>
+</feature>
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 3b7d6289d2..4c8f96bc3a 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -487,6 +487,8 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
+ loongarch_cpu_register_gdb_regs_for_features(cs);
+
cpu_reset(cs);
qemu_init_vcpu(cs);
@@ -640,6 +642,13 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
dc->vmsd = &vmstate_loongarch_cpu;
cc->sysemu_ops = &loongarch_sysemu_ops;
cc->disas_set_info = loongarch_cpu_disas_set_info;
+ cc->gdb_read_register = loongarch_cpu_gdb_read_register;
+ cc->gdb_write_register = loongarch_cpu_gdb_write_register;
+ cc->disas_set_info = loongarch_cpu_disas_set_info;
+ cc->gdb_num_core_regs = 34;
+ cc->gdb_core_xml_file = "loongarch-base64.xml";
+ cc->gdb_stop_before_watchpoint = true;
+
#ifdef CONFIG_TCG
cc->tcg_ops = &loongarch_tcg_ops;
#endif
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
new file mode 100644
index 0000000000..0c48834201
--- /dev/null
+++ b/target/loongarch/gdbstub.c
@@ -0,0 +1,81 @@
+/*
+ * LOONGARCH gdb server stub
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+#include "exec/gdbstub.h"
+
+int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ if (0 <= n && n < 32) {
+ return gdb_get_regl(mem_buf, env->gpr[n]);
+ } else if (n == 32) {
+ return gdb_get_regl(mem_buf, env->pc);
+ } else if (n == 33) {
+ return gdb_get_regl(mem_buf, env->badaddr);
+ }
+ return 0;
+}
+
+int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+ target_ulong tmp = ldtul_p(mem_buf);
+ int length = 0;
+
+ if (0 <= n && n < 32) {
+ env->gpr[n] = tmp;
+ length = sizeof(target_ulong);
+ } else if (n == 32) {
+ env->pc = tmp;
+ length = sizeof(target_ulong);
+ }
+ return length;
+}
+
+static int loongarch_gdb_get_fpu(CPULoongArchState *env,
+ GByteArray *mem_buf, int n)
+{
+ if (0 <= n && n < 32) {
+ return gdb_get_reg64(mem_buf, env->fpr[n]);
+ } else if (32 <= n && n < 40) {
+ return gdb_get_reg8(mem_buf, env->cf[n - 32]);
+ } else if (n == 40) {
+ return gdb_get_reg32(mem_buf, env->fcsr0);
+ }
+ return 0;
+}
+
+static int loongarch_gdb_set_fpu(CPULoongArchState *env,
+ uint8_t *mem_buf, int n)
+{
+ int length = 0;
+
+ if (0 <= n && n < 32) {
+ env->fpr[n] = ldq_p(mem_buf);
+ length = 8;
+ } else if (32 <= n && n < 40) {
+ env->cf[n - 32] = ldub_p(mem_buf);
+ length = 1;
+ } else if (n == 40) {
+ env->fcsr0 = ldl_p(mem_buf);
+ length = 4;
+ }
+ return length;
+}
+
+void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs)
+{
+ gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu,
+ 41, "loongarch-fpu64.xml", 0);
+}
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index a410c41c37..9d50fbdd81 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -49,4 +49,8 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
+int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
+void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs);
+
#endif
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index 74e5f3b2a7..6376f9e84b 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -11,6 +11,7 @@ loongarch_tcg_ss.add(files(
'fpu_helper.c',
'op_helper.c',
'translate.c',
+ 'gdbstub.c',
))
loongarch_tcg_ss.add(zlib)
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-01 03:03:01 +0000