diff options
| -rw-r--r-- | hw/ppc/spapr_cpu_core.c | 2 | ||||
| -rw-r--r-- | target/ppc/cpu.h | 3 | ||||
| -rw-r--r-- | target/ppc/cpu_init.c | 12 | ||||
| -rw-r--r-- | target/ppc/excp_helper.c | 4 | ||||
| -rw-r--r-- | target/ppc/misc_helper.c | 8 | ||||
| -rw-r--r-- | target/ppc/translate.c | 11 |
6 files changed, 35 insertions, 5 deletions
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index a4e3c2fadd..b482d9754a 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -270,6 +270,8 @@ static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr, env->spr_cb[SPR_PIR].default_value = cs->cpu_index; env->spr_cb[SPR_TIR].default_value = thread_index; + cpu_ppc_set_1lpar(cpu); + /* Set time-base frequency to 512 MHz. vhyp must be set first. */ cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index af12c93ebc..b269b0d090 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -674,6 +674,8 @@ enum { POWERPC_FLAG_SCV = 0x00200000, /* Has >1 thread per core */ POWERPC_FLAG_SMT = 0x00400000, + /* Using "LPAR per core" mode (as opposed to per-thread) */ + POWERPC_FLAG_SMT_1LPAR = 0x00800000, }; /* @@ -1437,6 +1439,7 @@ void store_booke_tsr(CPUPPCState *env, target_ulong val); void ppc_tlb_invalidate_all(CPUPPCState *env); void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr); void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp); +void cpu_ppc_set_1lpar(PowerPCCPU *cpu); int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddrp, target_ulong address, uint32_t pid); int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, uint32_t pid); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 5f4969664e..905a59aea9 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6629,6 +6629,18 @@ void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) env->msr_mask &= ~MSR_HVB; } +void cpu_ppc_set_1lpar(PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + + /* + * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable + * between threads. + */ + if (env->flags & POWERPC_FLAG_SMT) { + env->flags |= POWERPC_FLAG_SMT_1LPAR; + } +} #endif /* !defined(CONFIG_USER_ONLY) */ #endif /* defined(TARGET_PPC64) */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 354392668e..7683ea0fc9 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -3130,6 +3130,10 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP); + if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + nr_threads = 1; /* msgsndp behaves as 1-thread in LPAR-per-thread mode*/ + } + if (!dbell_type_server(rb) || ttir >= nr_threads) { return; } diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 1f1af21f33..26e546cc9c 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -191,6 +191,10 @@ target_ulong helper_load_dpdes(CPUPPCState *env) helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP); + if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */ + } + if (nr_threads == 1) { if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { dpdes = 1; @@ -222,6 +226,10 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong val) helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP); + if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */ + } + if (val & ~(nr_threads - 1)) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value " TARGET_FMT_lx"\n", val); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index db0ba49bdc..4556297ab5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -246,9 +246,9 @@ static inline bool gen_serialize(DisasContext *ctx) } #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) -static inline bool gen_serialize_core(DisasContext *ctx) +static inline bool gen_serialize_core_lpar(DisasContext *ctx) { - if (ctx->flags & POWERPC_FLAG_SMT) { + if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { return gen_serialize(ctx); } @@ -451,7 +451,8 @@ static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) { - if (!(ctx->flags & POWERPC_FLAG_SMT)) { + if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { + /* CTRL behaves as 1-thread in LPAR-per-thread mode */ spr_write_CTRL_ST(ctx, sprn, gprn); goto out; } @@ -815,7 +816,7 @@ void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) /* DPDES */ void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) { - if (!gen_serialize_core(ctx)) { + if (!gen_serialize_core_lpar(ctx)) { return; } @@ -824,7 +825,7 @@ void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) { - if (!gen_serialize_core(ctx)) { + if (!gen_serialize_core_lpar(ctx)) { return; } |