diff options
| -rw-r--r-- | target-sh4/op.c | 21 | ||||
| -rw-r--r-- | target-sh4/translate.c | 12 |
2 files changed, 9 insertions, 24 deletions
diff --git a/target-sh4/op.c b/target-sh4/op.c index 8313070232..7bd2e18dcf 100644 --- a/target-sh4/op.c +++ b/target-sh4/op.c @@ -115,27 +115,6 @@ void OPPROTO op_rotr_Rn(void) RETURN(); } -void OPPROTO op_shal_Rn(void) -{ - cond_t(env->gregs[PARAM1] & 0x80000000); - env->gregs[PARAM1] <<= 1; - RETURN(); -} - -void OPPROTO op_shar_Rn(void) -{ - cond_t(env->gregs[PARAM1] & 1); - *(int32_t *)&env->gregs[PARAM1] >>= 1; - RETURN(); -} - -void OPPROTO op_shlr_Rn(void) -{ - cond_t(env->gregs[PARAM1] & 1); - env->gregs[PARAM1] >>= 1; - RETURN(); -} - void OPPROTO op_fmov_frN_FT0(void) { FT0 = env->fregs[PARAM1]; diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 985675bfa7..6e29e8f9c6 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1226,13 +1226,19 @@ void _decode_opc(DisasContext * ctx) return; case 0x4000: /* shll Rn */ case 0x4020: /* shal Rn */ - gen_op_shal_Rn(REG(B11_8)); + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 0x80000000); + gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); + tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); return; case 0x4021: /* shar Rn */ - gen_op_shar_Rn(REG(B11_8)); + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1); + gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); + tcg_gen_sari_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); return; case 0x4001: /* shlr Rn */ - gen_op_shlr_Rn(REG(B11_8)); + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1); + gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); + tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); return; case 0x4008: /* shll2 Rn */ tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2); |