diff options
| -rw-r--r-- | CODING_STYLE | 4 | ||||
| -rw-r--r-- | Makefile.hw | 2 | ||||
| -rw-r--r-- | Makefile.target | 1 | ||||
| -rw-r--r-- | bswap.h | 474 | ||||
| -rwxr-xr-x | configure | 26 | ||||
| -rw-r--r-- | cpu-all.h | 446 | ||||
| -rw-r--r-- | cpu-common.h | 4 | ||||
| -rw-r--r-- | docs/memory.txt | 172 | ||||
| -rw-r--r-- | exec-memory.h | 39 | ||||
| -rw-r--r-- | exec.c | 19 | ||||
| -rw-r--r-- | fpu/softfloat-specialize.h | 72 | ||||
| -rw-r--r-- | fpu/softfloat.h | 60 | ||||
| -rw-r--r-- | hw/apb_pci.c | 2 | ||||
| -rw-r--r-- | hw/bonito.c | 4 | ||||
| -rw-r--r-- | hw/fw_cfg.c | 140 | ||||
| -rw-r--r-- | hw/grackle_pci.c | 5 | ||||
| -rw-r--r-- | hw/gt64xxx.c | 4 | ||||
| -rw-r--r-- | hw/hw.h | 1 | ||||
| -rw-r--r-- | hw/ide/ich.c | 6 | ||||
| -rw-r--r-- | hw/multiboot.c | 14 | ||||
| -rw-r--r-- | hw/pc.c | 62 | ||||
| -rw-r--r-- | hw/pc.h | 9 | ||||
| -rw-r--r-- | hw/pc_piix.c | 20 | ||||
| -rw-r--r-- | hw/pci.c | 63 | ||||
| -rw-r--r-- | hw/pci.h | 15 | ||||
| -rw-r--r-- | hw/pci_host.h | 1 | ||||
| -rw-r--r-- | hw/pci_internals.h | 1 | ||||
| -rw-r--r-- | hw/piix_pci.c | 13 | ||||
| -rw-r--r-- | hw/ppc4xx_pci.c | 5 | ||||
| -rw-r--r-- | hw/ppc_mac.h | 9 | ||||
| -rw-r--r-- | hw/ppc_newworld.c | 5 | ||||
| -rw-r--r-- | hw/ppc_oldworld.c | 3 | ||||
| -rw-r--r-- | hw/ppc_prep.c | 3 | ||||
| -rw-r--r-- | hw/ppce500_pci.c | 6 | ||||
| -rw-r--r-- | hw/prep_pci.c | 5 | ||||
| -rw-r--r-- | hw/prep_pci.h | 3 | ||||
| -rw-r--r-- | hw/qdev.c | 3 | ||||
| -rw-r--r-- | hw/sd.c | 19 | ||||
| -rw-r--r-- | hw/sh_pci.c | 4 | ||||
| -rw-r--r-- | hw/sysbus.c | 27 | ||||
| -rw-r--r-- | hw/sysbus.h | 3 | ||||
| -rw-r--r-- | hw/unin_pci.c | 10 | ||||
| -rw-r--r-- | hw/usb-bt.c | 6 | ||||
| -rw-r--r-- | hw/usb-ehci.c | 7 | ||||
| -rw-r--r-- | hw/usb-msd.c | 12 | ||||
| -rw-r--r-- | hw/usb-net.c | 6 | ||||
| -rw-r--r-- | hw/usb-ohci.c | 42 | ||||
| -rw-r--r-- | hw/usb-serial.c | 7 | ||||
| -rw-r--r-- | hw/usb-wacom.c | 6 | ||||
| -rw-r--r-- | hw/versatile_pci.c | 2 | ||||
| -rw-r--r-- | ioport.c | 4 | ||||
| -rw-r--r-- | memory.c | 1141 | ||||
| -rw-r--r-- | memory.h | 469 | ||||
| -rw-r--r-- | monitor.c | 2 | ||||
| -rw-r--r-- | oslib-posix.c | 5 | ||||
| -rw-r--r-- | qemu-common.h | 4 | ||||
| -rw-r--r-- | qemu-config.c | 27 | ||||
| -rw-r--r-- | qemu-options.hx | 16 | ||||
| -rw-r--r-- | savevm.c | 1 | ||||
| -rw-r--r-- | sysemu.h | 3 | ||||
| -rw-r--r-- | vl.c | 22 | ||||
| -rw-r--r-- | xen-mapcache.c | 3 |
62 files changed, 2937 insertions, 632 deletions
diff --git a/CODING_STYLE b/CODING_STYLE index 5ecfa22161..6e61c49089 100644 --- a/CODING_STYLE +++ b/CODING_STYLE @@ -68,6 +68,10 @@ keyword. Example: printf("a was something else entirely.\n"); } +Note that 'else if' is considered a single statement; otherwise a long if/ +else if/else if/.../else sequence would need an indent for every else +statement. + An exception is the opening brace for a function; for reasons of tradition and clarity it comes on a line by itself: diff --git a/Makefile.hw b/Makefile.hw index b9181ab122..659e441992 100644 --- a/Makefile.hw +++ b/Makefile.hw @@ -9,7 +9,7 @@ include $(SRC_PATH)/rules.mak $(call set-vpath, $(SRC_PATH):$(SRC_PATH)/hw) -QEMU_CFLAGS+=-I.. -I$(SRC_PATH)/fpu +QEMU_CFLAGS+=-I.. include $(SRC_PATH)/Makefile.objs diff --git a/Makefile.target b/Makefile.target index cde509ba76..8884a56aa3 100644 --- a/Makefile.target +++ b/Makefile.target @@ -198,6 +198,7 @@ obj-$(CONFIG_REALLY_VIRTFS) += 9pfs/virtio-9p-device.o obj-y += rwhandler.o obj-$(CONFIG_KVM) += kvm.o kvm-all.o obj-$(CONFIG_NO_KVM) += kvm-stub.o +obj-y += memory.o LIBS+=-lz QEMU_CFLAGS += $(VNC_TLS_CFLAGS) @@ -11,6 +11,8 @@ #include <machine/bswap.h> #else +#include "softfloat.h" + #ifdef CONFIG_BYTESWAP_H #include <byteswap.h> #else @@ -237,4 +239,476 @@ static inline uint32_t qemu_bswap_len(uint32_t value, int len) return bswap32(value) >> (32 - 8 * len); } +typedef union { + float32 f; + uint32_t l; +} CPU_FloatU; + +typedef union { + float64 d; +#if defined(HOST_WORDS_BIGENDIAN) + struct { + uint32_t upper; + uint32_t lower; + } l; +#else + struct { + uint32_t lower; + uint32_t upper; + } l; +#endif + uint64_t ll; +} CPU_DoubleU; + +typedef union { + floatx80 d; + struct { + uint64_t lower; + uint16_t upper; + } l; +} CPU_LDoubleU; + +typedef union { + float128 q; +#if defined(HOST_WORDS_BIGENDIAN) + struct { + uint32_t upmost; + uint32_t upper; + uint32_t lower; + uint32_t lowest; + } l; + struct { + uint64_t upper; + uint64_t lower; + } ll; +#else + struct { + uint32_t lowest; + uint32_t lower; + uint32_t upper; + uint32_t upmost; + } l; + struct { + uint64_t lower; + uint64_t upper; + } ll; +#endif +} CPU_QuadU; + +/* unaligned/endian-independent pointer access */ + +/* + * the generic syntax is: + * + * load: ld{type}{sign}{size}{endian}_p(ptr) + * + * store: st{type}{size}{endian}_p(ptr, val) + * + * Note there are small differences with the softmmu access API! + * + * type is: + * (empty): integer access + * f : float access + * + * sign is: + * (empty): for floats or 32 bit size + * u : unsigned + * s : signed + * + * size is: + * b: 8 bits + * w: 16 bits + * l: 32 bits + * q: 64 bits + * + * endian is: + * (empty): 8 bit access + * be : big endian + * le : little endian + */ +static inline int ldub_p(const void *ptr) +{ + return *(uint8_t *)ptr; +} + +static inline int ldsb_p(const void *ptr) +{ + return *(int8_t *)ptr; +} + +static inline void stb_p(void *ptr, int v) +{ + *(uint8_t *)ptr = v; +} + +/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the + kernel handles unaligned load/stores may give better results, but + it is a system wide setting : bad */ +#if defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED) + +/* conservative code for little endian unaligned accesses */ +static inline int lduw_le_p(const void *ptr) +{ +#ifdef _ARCH_PPC + int val; + __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); + return val; +#else + const uint8_t *p = ptr; + return p[0] | (p[1] << 8); +#endif +} + +static inline int ldsw_le_p(const void *ptr) +{ +#ifdef _ARCH_PPC + int val; + __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); + return (int16_t)val; +#else + const uint8_t *p = ptr; + return (int16_t)(p[0] | (p[1] << 8)); +#endif +} + +static inline int ldl_le_p(const void *ptr) +{ +#ifdef _ARCH_PPC + int val; + __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr)); + return val; +#else + const uint8_t *p = ptr; + return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); +#endif +} + +static inline uint64_t ldq_le_p(const void *ptr) +{ + const uint8_t *p = ptr; + uint32_t v1, v2; + v1 = ldl_le_p(p); + v2 = ldl_le_p(p + 4); + return v1 | ((uint64_t)v2 << 32); +} + +static inline void stw_le_p(void *ptr, int v) +{ +#ifdef _ARCH_PPC + __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr)); +#else + uint8_t *p = ptr; + p[0] = v; + p[1] = v >> 8; +#endif +} + +static inline void stl_le_p(void *ptr, int v) +{ +#ifdef _ARCH_PPC + __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr)); +#else + uint8_t *p = ptr; + p[0] = v; + p[1] = v >> 8; + p[2] = v >> 16; + p[3] = v >> 24; +#endif +} + +static inline void stq_le_p(void *ptr, uint64_t v) +{ + uint8_t *p = ptr; + stl_le_p(p, (uint32_t)v); + stl_le_p(p + 4, v >> 32); +} + +/* float access */ + +static inline float32 ldfl_le_p(const void *ptr) +{ + union { + float32 f; + uint32_t i; + } u; + u.i = ldl_le_p(ptr); + return u.f; +} + +static inline void stfl_le_p(void *ptr, float32 v) +{ + union { + float32 f; + uint32_t i; + } u; + u.f = v; + stl_le_p(ptr, u.i); +} + +static inline float64 ldfq_le_p(const void *ptr) +{ + CPU_DoubleU u; + u.l.lower = ldl_le_p(ptr); + u.l.upper = ldl_le_p(ptr + 4); + return u.d; +} + +static inline void stfq_le_p(void *ptr, float64 v) +{ + CPU_DoubleU u; + u.d = v; + stl_le_p(ptr, u.l.lower); + stl_le_p(ptr + 4, u.l.upper); +} + +#else + +static inline int lduw_le_p(const void *ptr) +{ + return *(uint16_t *)ptr; +} + +static inline int ldsw_le_p(const void *ptr) +{ + return *(int16_t *)ptr; +} + +static inline int ldl_le_p(const void *ptr) +{ + return *(uint32_t *)ptr; +} + +static inline uint64_t ldq_le_p(const void *ptr) +{ + return *(uint64_t *)ptr; +} + +static inline void stw_le_p(void *ptr, int v) +{ + *(uint16_t *)ptr = v; +} + +static inline void stl_le_p(void *ptr, int v) +{ + *(uint32_t *)ptr = v; +} + +static inline void stq_le_p(void *ptr, uint64_t v) +{ + *(uint64_t *)ptr = v; +} + +/* float access */ + +static inline float32 ldfl_le_p(const void *ptr) +{ + return *(float32 *)ptr; +} + +static inline float64 ldfq_le_p(const void *ptr) +{ + return *(float64 *)ptr; +} + +static inline void stfl_le_p(void *ptr, float32 v) +{ + *(float32 *)ptr = v; +} + +static inline void stfq_le_p(void *ptr, float64 v) +{ + *(float64 *)ptr = v; +} +#endif + +#if !defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED) + +static inline int lduw_be_p(const void *ptr) +{ +#if defined(__i386__) + int val; + asm volatile ("movzwl %1, %0\n" + "xchgb %b0, %h0\n" + : "=q" (val) + : "m" (*(uint16_t *)ptr)); + return val; +#else + const uint8_t *b = ptr; + return ((b[0] << 8) | b[1]); +#endif +} + +static inline int ldsw_be_p(const void *ptr) +{ +#if defined(__i386__) + int val; + asm volatile ("movzwl %1, %0\n" + "xchgb %b0, %h0\n" + : "=q" (val) + : "m" (*(uint16_t *)ptr)); + return (int16_t)val; +#else + const uint8_t *b = ptr; + return (int16_t)((b[0] << 8) | b[1]); +#endif +} + +static inline int ldl_be_p(const void *ptr) +{ +#if defined(__i386__) || defined(__x86_64__) + int val; + asm volatile ("movl %1, %0\n" + "bswap %0\n" + : "=r" (val) + : "m" (*(uint32_t *)ptr)); + return val; +#else + const uint8_t *b = ptr; + return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; +#endif +} + +static inline uint64_t ldq_be_p(const void *ptr) +{ + uint32_t a,b; + a = ldl_be_p(ptr); + b = ldl_be_p((uint8_t *)ptr + 4); + return (((uint64_t)a<<32)|b); +} + +static inline void stw_be_p(void *ptr, int v) +{ +#if defined(__i386__) + asm volatile ("xchgb %b0, %h0\n" + "movw %w0, %1\n" + : "=q" (v) + : "m" (*(uint16_t *)ptr), "0" (v)); +#else + uint8_t *d = (uint8_t *) ptr; + d[0] = v >> 8; + d[1] = v; +#endif +} + +static inline void stl_be_p(void *ptr, int v) +{ +#if defined(__i386__) || defined(__x86_64__) + asm volatile ("bswap %0\n" + "movl %0, %1\n" + : "=r" (v) + : "m" (*(uint32_t *)ptr), "0" (v)); +#else + uint8_t *d = (uint8_t *) ptr; + d[0] = v >> 24; + d[1] = v >> 16; + d[2] = v >> 8; + d[3] = v; +#endif +} + +static inline void stq_be_p(void *ptr, uint64_t v) +{ + stl_be_p(ptr, v >> 32); + stl_be_p((uint8_t *)ptr + 4, v); +} + +/* float access */ + +static inline float32 ldfl_be_p(const void *ptr) +{ + union { + float32 f; + uint32_t i; + } u; + u.i = ldl_be_p(ptr); + return u.f; +} + +static inline void stfl_be_p(void *ptr, float32 v) +{ + union { + float32 f; + uint32_t i; + } u; + u.f = v; + stl_be_p(ptr, u.i); +} + +static inline float64 ldfq_be_p(const void *ptr) +{ + CPU_DoubleU u; + u.l.upper = ldl_be_p(ptr); + u.l.lower = ldl_be_p((uint8_t *)ptr + 4); + return u.d; +} + +static inline void stfq_be_p(void *ptr, float64 v) +{ + CPU_DoubleU u; + u.d = v; + stl_be_p(ptr, u.l.upper); + stl_be_p((uint8_t *)ptr + 4, u.l.lower); +} + +#else + +static inline int lduw_be_p(const void *ptr) +{ + return *(uint16_t *)ptr; +} + +static inline int ldsw_be_p(const void *ptr) +{ + return *(int16_t *)ptr; +} + +static inline int ldl_be_p(const void *ptr) +{ + return *(uint32_t *)ptr; +} + +static inline uint64_t ldq_be_p(const void *ptr) +{ + return *(uint64_t *)ptr; +} + +static inline void stw_be_p(void *ptr, int v) +{ + *(uint16_t *)ptr = v; +} + +static inline void stl_be_p(void *ptr, int v) +{ + *(uint32_t *)ptr = v; +} + +static inline void stq_be_p(void *ptr, uint64_t v) +{ + *(uint64_t *)ptr = v; +} + +/* float access */ + +static inline float32 ldfl_be_p(const void *ptr) +{ + return *(float32 *)ptr; +} + +static inline float64 ldfq_be_p(const void *ptr) +{ + return *(float64 *)ptr; +} + +static inline void stfl_be_p(void *ptr, float32 v) +{ + *(float32 *)ptr = v; +} + +static inline void stfq_be_p(void *ptr, float64 v) +{ + *(float64 *)ptr = v; +} + +#endif + #endif /* BSWAP_H */ @@ -179,6 +179,7 @@ smartcard="" smartcard_nss="" usb_redir="" opengl="" +zlib="yes" # parse CC options first for opt do @@ -233,7 +234,7 @@ QEMU_CFLAGS="-Wall -Wundef -Wwrite-strings -Wmissing-prototypes $QEMU_CFLAGS" QEMU_CFLAGS="-Wstrict-prototypes -Wredundant-decls $QEMU_CFLAGS" QEMU_CFLAGS="-D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE $QEMU_CFLAGS" QEMU_CFLAGS="-D_FORTIFY_SOURCE=2 $QEMU_CFLAGS" -QEMU_INCLUDES="-I. -I\$(SRC_PATH)" +QEMU_INCLUDES="-I. -I\$(SRC_PATH) -I\$(SRC_PATH)/fpu" LDFLAGS="-g $LDFLAGS" # make source path absolute @@ -751,6 +752,8 @@ for opt do ;; --enable-usb-redir) usb_redir="yes" ;; + --disable-zlib-test) zlib="no" + ;; *) echo "ERROR: unknown option $opt"; show_help="yes" ;; esac @@ -1190,18 +1193,20 @@ fi ########################################## # zlib check -cat > $TMPC << EOF +if test "$zlib" != "no" ; then + cat > $TMPC << EOF #include <zlib.h> int main(void) { zlibVersion(); return 0; } EOF -if compile_prog "" "-lz" ; then - : -else - echo - echo "Error: zlib check failed" - echo "Make sure to have the zlib libs and headers installed." - echo - exit 1 + if compile_prog "" "-lz" ; then + : + else + echo + echo "Error: zlib check failed" + echo "Make sure to have the zlib libs and headers installed." + echo + exit 1 + fi fi ########################################## @@ -3376,7 +3381,6 @@ else includes="-I\$(SRC_PATH)/tcg/\$(ARCH) $includes" fi includes="-I\$(SRC_PATH)/tcg $includes" -includes="-I\$(SRC_PATH)/fpu $includes" if test "$target_user_only" = "yes" ; then libdis_config_mak=libdis-user/config.mak @@ -35,8 +35,6 @@ * TARGET_WORDS_BIGENDIAN : same for target cpu */ -#include "softfloat.h" - #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) #define BSWAP_NEEDED #endif @@ -114,64 +112,6 @@ static inline void tswap64s(uint64_t *s) #define bswaptls(s) bswap64s(s) #endif -typedef union { - float32 f; - uint32_t l; -} CPU_FloatU; - -/* NOTE: arm FPA is horrible as double 32 bit words are stored in big - endian ! */ -typedef union { - float64 d; -#if defined(HOST_WORDS_BIGENDIAN) - struct { - uint32_t upper; - uint32_t lower; - } l; -#else - struct { - uint32_t lower; - uint32_t upper; - } l; -#endif - uint64_t ll; -} CPU_DoubleU; - -typedef union { - floatx80 d; - struct { - uint64_t lower; - uint16_t upper; - } l; -} CPU_LDoubleU; - -typedef union { - float128 q; -#if defined(HOST_WORDS_BIGENDIAN) - struct { - uint32_t upmost; - uint32_t upper; - uint32_t lower; - uint32_t lowest; - } l; - struct { - uint64_t upper; - uint64_t lower; - } ll; -#else - struct { - uint32_t lowest; - uint32_t lower; - uint32_t upper; - uint32_t upmost; - } l; - struct { - uint64_t lower; - uint64_t upper; - } ll; -#endif -} CPU_QuadU; - /* CPU memory access without any memory or io remapping */ /* @@ -207,392 +147,8 @@ typedef union { * user : user mode access using soft MMU * kernel : kernel mode access using soft MMU */ -static inline int ldub_p(const void *ptr) -{ - return *(uint8_t *)ptr; -} - -static inline int ldsb_p(const void *ptr) -{ - return *(int8_t *)ptr; -} - -static inline void stb_p(void *ptr, int v) -{ - *(uint8_t *)ptr = v; -} - -/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the - kernel handles unaligned load/stores may give better results, but - it is a system wide setting : bad */ -#if defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED) - -/* conservative code for little endian unaligned accesses */ -static inline int lduw_le_p(const void *ptr) -{ -#ifdef _ARCH_PPC - int val; - __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); - return val; -#else - const uint8_t *p = ptr; - return p[0] | (p[1] << 8); -#endif -} - -static inline int ldsw_le_p(const void *ptr) -{ -#ifdef _ARCH_PPC - int val; - __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); - return (int16_t)val; -#else - const uint8_t *p = ptr; - return (int16_t)(p[0] | (p[1] << 8)); -#endif -} - -static inline int ldl_le_p(const void *ptr) -{ -#ifdef _ARCH_PPC - int val; - __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr)); - return val; -#else - const uint8_t *p = ptr; - return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); -#endif -} - -static inline uint64_t ldq_le_p(const void *ptr) -{ - const uint8_t *p = ptr; - uint32_t v1, v2; - v1 = ldl_le_p(p); - v2 = ldl_le_p(p + 4); - return v1 | ((uint64_t)v2 << 32); -} - -static inline void stw_le_p(void *ptr, int v) -{ -#ifdef _ARCH_PPC - __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr)); -#else - uint8_t *p = ptr; - p[0] = v; - p[1] = v >> 8; -#endif -} - -static inline void stl_le_p(void *ptr, int v) -{ -#ifdef _ARCH_PPC - __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr)); -#else - uint8_t *p = ptr; - p[0] = v; - p[1] = v >> 8; - p[2] = v >> 16; - p[3] = v >> 24; -#endif -} - -static inline void stq_le_p(void *ptr, uint64_t v) -{ - uint8_t *p = ptr; - stl_le_p(p, (uint32_t)v); - stl_le_p(p + 4, v >> 32); -} - -/* float access */ - -static inline float32 ldfl_le_p(const void *ptr) -{ - union { - float32 f; - uint32_t i; - } u; - u.i = ldl_le_p(ptr); - return u.f; -} - -static inline void stfl_le_p(void *ptr, float32 v) -{ - union { - float32 f; - uint32_t i; - } u; - u.f = v; - stl_le_p(ptr, u.i); -} - -static inline float64 ldfq_le_p(const void *ptr) -{ - CPU_DoubleU u; - u.l.lower = ldl_le_p(ptr); - u.l.upper = ldl_le_p(ptr + 4); - return u.d; -} - -static inline void stfq_le_p(void *ptr, float64 v) -{ - CPU_DoubleU u; - u.d = v; - stl_le_p(ptr, u.l.lower); - stl_le_p(ptr + 4, u.l.upper); -} - -#else - -static inline int lduw_le_p(const void *ptr) -{ - return *(uint16_t *)ptr; -} - -static inline int ldsw_le_p(const void *ptr) -{ - return *(int16_t *)ptr; -} - -static inline int ldl_le_p(const void *ptr) -{ - return *(uint32_t *)ptr; -} - -static inline uint64_t ldq_le_p(const void *ptr) -{ - return *(uint64_t *)ptr; -} - -static inline void stw_le_p(void *ptr, int v) -{ - *(uint16_t *)ptr = v; -} - -static inline void stl_le_p(void *ptr, int v) -{ - *(uint32_t *)ptr = v; -} - -static inline void stq_le_p(void *ptr, uint64_t v) -{ - *(uint64_t *)ptr = v; -} - -/* float access */ - -static inline float32 ldfl_le_p(const void *ptr) -{ - return *(float32 *)ptr; -} - -static inline float64 ldfq_le_p(const void *ptr) -{ - return *(float64 *)ptr; -} - -static inline void stfl_le_p(void *ptr, float32 v) -{ - *(float32 *)ptr = v; -} - -static inline void stfq_le_p(void *ptr, float64 v) -{ - *(float64 *)ptr = v; -} -#endif - -#if !defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED) - -static inline int lduw_be_p(const void *ptr) -{ -#if defined(__i386__) - int val; - asm volatile ("movzwl %1, %0\n" - "xchgb %b0, %h0\n" - : "=q" (val) - : "m" (*(uint16_t *)ptr)); - return val; -#else - const uint8_t *b = ptr; - return ((b[0] << 8) | b[1]); -#endif -} - -static inline int ldsw_be_p(const void *ptr) -{ -#if defined(__i386__) - int val; - asm volatile ("movzwl %1, %0\n" - "xchgb %b0, %h0\n" - : "=q" (val) - : "m" (*(uint16_t *)ptr)); - return (int16_t)val; -#else - const uint8_t *b = ptr; - return (int16_t)((b[0] << 8) | b[1]); -#endif -} - -static inline int ldl_be_p(const void *ptr) -{ -#if defined(__i386__) || defined(__x86_64__) - int val; - asm volatile ("movl %1, %0\n" - "bswap %0\n" - : "=r" (val) - : "m" (*(uint32_t *)ptr)); - return val; -#else - const uint8_t *b = ptr; - return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; -#endif -} - -static inline uint64_t ldq_be_p(const void *ptr) -{ - uint32_t a,b; - a = ldl_be_p(ptr); - b = ldl_be_p((uint8_t *)ptr + 4); - return (((uint64_t)a<<32)|b); -} - -static inline void stw_be_p(void *ptr, int v) -{ -#if defined(__i386__) - asm volatile ("xchgb %b0, %h0\n" - "movw %w0, %1\n" - : "=q" (v) - : "m" (*(uint16_t *)ptr), "0" (v)); -#else - uint8_t *d = (uint8_t *) ptr; - d[0] = v >> 8; - d[1] = v; -#endif -} - -static inline void stl_be_p(void *ptr, int v) -{ -#if defined(__i386__) || defined(__x86_64__) - asm volatile ("bswap %0\n" - "movl %0, %1\n" - : "=r" (v) - : "m" (*(uint32_t *)ptr), "0" (v)); -#else - uint8_t *d = (uint8_t *) ptr; - d[0] = v >> 24; - d[1] = v >> 16; - d[2] = v >> 8; - d[3] = v; -#endif -} - -static inline void stq_be_p(void *ptr, uint64_t v) -{ - stl_be_p(ptr, v >> 32); - stl_be_p((uint8_t *)ptr + 4, v); -} - -/* float access */ - -static inline float32 ldfl_be_p(const void *ptr) -{ - union { - float32 f; - uint32_t i; - } u; - u.i = ldl_be_p(ptr); - return u.f; -} - -static inline void stfl_be_p(void *ptr, float32 v) -{ - union { - float32 f; - uint32_t i; - } u; - u.f = v; - stl_be_p(ptr, u.i); -} - -static inline float64 ldfq_be_p(const void *ptr) -{ - CPU_DoubleU u; - u.l.upper = ldl_be_p(ptr); - u.l.lower = ldl_be_p((uint8_t *)ptr + 4); - return u.d; -} - -static inline void stfq_be_p(void *ptr, float64 v) -{ - CPU_DoubleU u; - u.d = v; - stl_be_p(ptr, u.l.upper); - stl_be_p((uint8_t *)ptr + 4, u.l.lower); -} - -#else - -static inline int lduw_be_p(const void *ptr) -{ - return *(uint16_t *)ptr; -} - -static inline int ldsw_be_p(const void *ptr) -{ - return *(int16_t *)ptr; -} - -static inline int ldl_be_p(const void *ptr) -{ - return *(uint32_t *)ptr; -} - -static inline uint64_t ldq_be_p(const void *ptr) -{ - return *(uint64_t *)ptr; -} - -static inline void stw_be_p(void *ptr, int v) -{ - *(uint16_t *)ptr = v; -} - -static inline void stl_be_p(void *ptr, int v) -{ - *(uint32_t *)ptr = v; -} - -static inline void stq_be_p(void *ptr, uint64_t v) -{ - *(uint64_t *)ptr = v; -} - -/* float access */ - -static inline float32 ldfl_be_p(const void *ptr) -{ - return *(float32 *)ptr; -} - -static inline float64 ldfq_be_p(const void *ptr) -{ - return *(float64 *)ptr; -} - -static inline void stfl_be_p(void *ptr, float32 v) -{ - *(float32 *)ptr = v; -} - -static inline void stfq_be_p(void *ptr, float64 v) -{ - *(float64 *)ptr = v; -} - -#endif -/* target CPU memory access functions */ +/* target-endianness CPU memory access functions */ #if defined(TARGET_WORDS_BIGENDIAN) #define lduw_p(p) lduw_be_p(p) #define ldsw_p(p) ldsw_be_p(p) diff --git a/cpu-common.h b/cpu-common.h index 070010130c..c9878ba474 100644 --- a/cpu-common.h +++ b/cpu-common.h @@ -3,10 +3,6 @@ /* CPU interfaces that are target indpendent. */ -#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__) -#define WORDS_ALIGNED -#endif - #ifdef TARGET_PHYS_ADDR_BITS #include "targphys.h" #endif diff --git a/docs/memory.txt b/docs/memory.txt new file mode 100644 index 0000000000..4460c0641a --- /dev/null +++ b/docs/memory.txt @@ -0,0 +1,172 @@ +The memory API +============== + +The memory API models the memory and I/O buses and controllers of a QEMU +machine. It attempts to allow modelling of: + + - ordinary RAM + - memory-mapped I/O (MMIO) + - memory controllers that can dynamically reroute physical memory regions + to different destinations + +The memory model provides support for + + - tracking RAM changes by the guest + - setting up coalesced memory for kvm + - setting up ioeventfd regions for kvm + +Memory is modelled as an tree (really acyclic graph) of MemoryRegion objects. +The root of the tree is memory as seen from the CPU's viewpoint (the system +bus). Nodes in the tree represent other buses, memory controllers, and +memory regions that have been rerouted. Leaves are RAM and MMIO regions. + +Types of regions +---------------- + +There are four types of memory regions (all represented by a single C type +MemoryRegion): + +- RAM: a RAM region is simply a range of host memory that can be made available + to the guest. + +- MMIO: a range of guest memory that is implemented by host callbacks; + each read or write causes a callback to be called on the host. + +- container: a container simply includes other memory regions, each at + a different offset. Containers are useful for grouping several regions + into one unit. For example, a PCI BAR may be composed of a RAM region + and an MMIO region. + + A container's subregions are usually non-overlapping. In some cases it is + useful to have overlapping regions; for example a memory controller that + can overlay a subregion of RAM with MMIO or ROM, or a PCI controller + that does not prevent card from claiming overlapping BARs. + +- alias: a subsection of another region. Aliases allow a region to be + split apart into discontiguous regions. Examples of uses are memory banks + used when the guest address space is smaller than the amount of RAM + addressed, or a memory controller that splits main memory to expose a "PCI + hole". Aliases may point to any type of region, including other aliases, + but an alias may not point back to itself, directly or indirectly. + + +Region names +------------ + +Regions are assigned names by the constructor. For most regions these are +only used for debugging purposes, but RAM regions also use the name to identify +live migration sections. This means that RAM region names need to have ABI +stability. + +Region lifecycle +---------------- + +A region is created by one of the constructor functions (memory_region_init*()) +and destroyed by the destructor (memory_region_destroy()). In between, +a region can be added to an address space by using memory_region_add_subregion() +and removed using memory_region_del_subregion(). Region attributes may be +changed at any point; they take effect once the region becomes exposed to the +guest. + +Overlapping regions and priority +-------------------------------- +Usually, regions may not overlap each other; a memory address decodes into +exactly one target. In some cases it is useful to allow regions to overlap, +and sometimes to control which of an overlapping regions is visible to the +guest. This is done with memory_region_add_subregion_overlap(), which +allows the region to overlap any other region in the same container, and +specifies a priority that allows the core to decide which of two regions at +the same address are visible (highest wins). + +Visibility +---------- +The memory core uses the following rules to select a memory region when the +guest accesses an address: + +- all direct subregions of the root region are matched against the address, in + descending priority order + - if the address lies outside the region offset/size, the subregion is + discarded + - if the subregion is a leaf (RAM or MMIO), the seach terminates + - if the subregion is a container, the same algorithm is used within the + subregion (after the address is adjusted by the subregion offset) + - if the subregion is an alias, the search is continues at the alias target + (after the address is adjusted by the subregion offset and alias offset) + +Example memory map +------------------ + +system_memory: container@0-2^48-1 + | + +---- lomem: alias@0-0xdfffffff ---> #ram (0-0xdfffffff) + | + +---- himem: alias@0x100000000-0x11fffffff ---> #ram (0xe0000000-0xffffffff) + | + +---- vga-window: alias@0xa0000-0xbfffff ---> #pci (0xa0000-0xbffff) + | (prio 1) + | + +---- pci-hole: alias@0xe0000000-0xffffffff ---> #pci (0xe0000000-0xffffffff) + +pci (0-2^32-1) + | + +--- vga-area: container@0xa0000-0xbffff + | | + | +--- alias@0x00000-0x7fff ---> #vram (0x010000-0x017fff) + | | + | +--- alias@0x08000-0xffff ---> #vram (0x020000-0x027fff) + | + +---- vram: ram@0xe1000000-0xe1ffffff + | + +---- vga-mmio: mmio@0xe2000000-0xe200ffff + +ram: ram@0x00000000-0xffffffff + +The is a (simplified) PC memory map. The 4GB RAM block is mapped into the +system address space via two aliases: "lomem" is a 1:1 mapping of the first +3.5GB; "himem" maps the last 0.5GB at address 4GB. This leaves 0.5GB for the +so-called PCI hole, that allows a 32-bit PCI bus to exist in a system with +4GB of memory. + +The memory controller diverts addresses in the range 640K-768K to the PCI +address space. This is modeled using the "vga-window" alias, mapped at a +higher priority so it obscures the RAM at the same addresses. The vga window +can be removed by programming the memory controller; this is modelled by +removing the alias and exposing the RAM underneath. + +The pci address space is not a direct child of the system address space, since +we only want parts of it to be visible (we accomplish this using aliases). +It has two subregions: vga-area models the legacy vga window and is occupied +by two 32K memory banks pointing at two sections of the framebuffer. +In addition the vram is mapped as a BAR at address e1000000, and an additional +BAR containing MMIO registers is mapped after it. + +Note that if the guest maps a BAR outside the PCI hole, it would not be +visible as the pci-hole alias clips it to a 0.5GB range. + +Attributes +---------- + +Various region attributes (read-only, dirty logging, coalesced mmio, ioeventfd) +can be changed during the region lifecycle. They take effect once the region +is made visible (which can be immediately, later, or never). + +MMIO Operations +--------------- + +MMIO regions are provided with ->read() and ->write() callbacks; in addition +various constraints can be supplied to control how these callbacks are called: + + - .valid.min_access_size, .valid.max_access_size define the access sizes + (in bytes) which the device accepts; accesses outside this range will + have device and bus specific behaviour (ignored, or machine check) + - .valid.aligned specifies that the device only accepts naturally aligned + accesses. Unaligned accesses invoke device and bus specific behaviour. + - .impl.min_access_size, .impl.max_access_size define the access sizes + (in bytes) supported by the *implementation*; other access sizes will be + emulated using the ones available. For example a 4-byte write will be + emulated using four 1-byte write, is .impl.max_access_size = 1. + - .impl.valid specifies that the *implementation* only supports unaligned + accesses; unaligned accesses will be emulated by two aligned accesses. + - .old_portio and .old_mmio can be used to ease porting from code using + cpu_register_io_memory() and register_ioport(). They should not be used + in new code. diff --git a/exec-memory.h b/exec-memory.h new file mode 100644 index 0000000000..c439aba3d1 --- /dev/null +++ b/exec-memory.h @@ -0,0 +1,39 @@ +/* + * Internal memory managment interfaces + * + * Copyright 2011 Red Hat, Inc. and/or its affiliates + * + * Authors: + * Avi Kivity <avi@redhat.com> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + */ + +#ifndef EXEC_MEMORY_H +#define EXEC_MEMORY_H + +/* + * Internal interfaces between memory.c/exec.c/vl.c. Do not #include unless + * you're one of them. + */ + +#include "memory.h" + +#ifndef CONFIG_USER_ONLY + +/* Get the root memory region. This interface should only be used temporarily + * until a proper bus interface is available. + */ +MemoryRegion *get_system_memory(void); + +/* Set the root memory region. This region is the system memory map. */ +void set_system_memory_map(MemoryRegion *mr); + +/* Set the I/O memory region. This region is the I/O memory map. */ +void set_system_io_map(MemoryRegion *mr); + +#endif + +#endif @@ -33,6 +33,8 @@ #include "kvm.h" #include "hw/xen.h" #include "qemu-timer.h" +#include "memory.h" +#include "exec-memory.h" #if defined(CONFIG_USER_ONLY) #include <qemu.h> #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) @@ -109,6 +111,9 @@ int phys_ram_fd; static int in_migration; RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list) }; + +static MemoryRegion *system_memory; + #endif CPUState *first_cpu; @@ -197,6 +202,7 @@ typedef struct PhysPageDesc { static void *l1_phys_map[P_L1_SIZE]; static void io_mem_init(void); +static void memory_map_init(void); /* io memory support */ CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; @@ -571,6 +577,7 @@ void cpu_exec_init_all(unsigned long tb_size) code_gen_ptr = code_gen_buffer; page_init(); #if !defined(CONFIG_USER_ONLY) + memory_map_init(); io_mem_init(); #endif #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE) @@ -3808,6 +3815,18 @@ static void io_mem_init(void) DEVICE_NATIVE_ENDIAN); } +static void memory_map_init(void) +{ + system_memory = qemu_malloc(sizeof(*system_memory)); + memory_region_init(system_memory, "system", UINT64_MAX); + set_system_memory_map(system_memory); +} + +MemoryRegion *get_system_memory(void) +{ + return system_memory; +} + #endif /* !defined(CONFIG_USER_ONLY) */ /* physical memory access (slow version, mainly for debug) */ diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index c7d35a161d..c165205a49 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -35,6 +35,78 @@ these four paragraphs for those parts of this code that are retained. =============================================================================*/ +#if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICORE32) +#define SNAN_BIT_IS_ONE 1 +#else +#define SNAN_BIT_IS_ONE 0 +#endif + +/*---------------------------------------------------------------------------- +| The pattern for a default generated half-precision NaN. +*----------------------------------------------------------------------------*/ +#if defined(TARGET_ARM) +const float16 float16_default_nan = const_float16(0x7E00); +#elif SNAN_BIT_IS_ONE +const float16 float16_default_nan = const_float16(0x7DFF); +#else +const float16 float16_default_nan = const_float16(0xFE00); +#endif + +/*---------------------------------------------------------------------------- +| The pattern for a default generated single-precision NaN. +*----------------------------------------------------------------------------*/ +#if defined(TARGET_SPARC) +const float32 float32_default_nan = const_float32(0x7FFFFFFF); +#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) +const float32 float32_default_nan = const_float32(0x7FC00000); +#elif SNAN_BIT_IS_ONE +const float32 float32_default_nan = const_float32(0x7FBFFFFF); +#else +const float32 float32_default_nan = const_float32(0xFFC00000); +#endif + +/*---------------------------------------------------------------------------- +| The pattern for a default generated double-precision NaN. +*----------------------------------------------------------------------------*/ +#if defined(TARGET_SPARC) +const float64 float64_default_nan = const_float64(LIT64( 0x7FFFFFFFFFFFFFFF )); +#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) +const float64 float64_default_nan = const_float64(LIT64( 0x7FF8000000000000 )); +#elif SNAN_BIT_IS_ONE +const float64 float64_default_nan = const_float64(LIT64( 0x7FF7FFFFFFFFFFFF )); +#else +const float64 float64_default_nan = const_float64(LIT64( 0xFFF8000000000000 )); +#endif + +/*---------------------------------------------------------------------------- +| The pattern for a default generated extended double-precision NaN. +*----------------------------------------------------------------------------*/ +#if SNAN_BIT_IS_ONE +#define floatx80_default_nan_high 0x7FFF +#define floatx80_default_nan_low LIT64( 0xBFFFFFFFFFFFFFFF ) +#else +#define floatx80_default_nan_high 0xFFFF +#define floatx80_default_nan_low LIT64( 0xC000000000000000 ) +#endif + +const floatx80 floatx80_default_nan = make_floatx80(floatx80_default_nan_high, + floatx80_default_nan_low); + +/*---------------------------------------------------------------------------- +| The pattern for a default generated quadruple-precision NaN. The `high' and +| `low' values hold the most- and least-significant bits, respectively. +*----------------------------------------------------------------------------*/ +#if SNAN_BIT_IS_ONE +#define float128_default_nan_high LIT64( 0x7FFF7FFFFFFFFFFF ) +#define float128_default_nan_low LIT64( 0xFFFFFFFFFFFFFFFF ) +#else +#define float128_default_nan_high LIT64( 0xFFFF800000000000 ) +#define float128_default_nan_low LIT64( 0x0000000000000000 ) +#endif + +const float128 float128_default_nan = make_float128(float128_default_nan_high, + float128_default_nan_low); + /*---------------------------------------------------------------------------- | Raises the exceptions specified by `flags'. Floating-point traps can be | defined here if desired. It is currently not possible for such a trap diff --git a/fpu/softfloat.h b/fpu/softfloat.h index bde250087b..3bb7d8fa6d 100644 --- a/fpu/softfloat.h +++ b/fpu/softfloat.h @@ -43,7 +43,7 @@ these four paragraphs for those parts of this code that are retained. #endif #include <inttypes.h> -#include "config.h" +#include "config-host.h" /*---------------------------------------------------------------------------- | Each of the following `typedef's defines the most convenient type that holds @@ -68,12 +68,6 @@ typedef int64_t int64; #define LIT64( a ) a##LL #define INLINE static inline -#if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICORE32) -#define SNAN_BIT_IS_ONE 1 -#else -#define SNAN_BIT_IS_ONE 0 -#endif - #define STATUS_PARAM , float_status *status #define STATUS(field) status->field #define STATUS_VAR , status @@ -142,6 +136,7 @@ typedef struct { uint64_t low, high; #endif } float128; +#define make_float128(high_, low_) ((float128) { .high = high_, .low = low_ }) /*---------------------------------------------------------------------------- | Software IEC/IEEE floating-point underflow tininess-detection mode. @@ -248,13 +243,7 @@ float16 float16_maybe_silence_nan( float16 ); /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ -#if defined(TARGET_ARM) -#define float16_default_nan make_float16(0x7E00) -#elif SNAN_BIT_IS_ONE -#define float16_default_nan make_float16(0x7DFF) -#else -#define float16_default_nan make_float16(0xFE00) -#endif +extern const float16 float16_default_nan; /*---------------------------------------------------------------------------- | Software IEC/IEEE single-precision conversion routines. @@ -357,15 +346,7 @@ INLINE float32 float32_set_sign(float32 a, int sign) /*---------------------------------------------------------------------------- | The pattern for a default generated single-precision NaN. *----------------------------------------------------------------------------*/ -#if defined(TARGET_SPARC) -#define float32_default_nan make_float32(0x7FFFFFFF) -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) -#define float32_default_nan make_float32(0x7FC00000) -#elif SNAN_BIT_IS_ONE -#define float32_default_nan make_float32(0x7FBFFFFF) -#else -#define float32_default_nan make_float32(0xFFC00000) -#endif +extern const float32 float32_default_nan; /*---------------------------------------------------------------------------- | Software IEC/IEEE double-precision conversion routines. @@ -470,15 +451,7 @@ INLINE float64 float64_set_sign(float64 a, int sign) /*---------------------------------------------------------------------------- | The pattern for a default generated double-precision NaN. *----------------------------------------------------------------------------*/ -#if defined(TARGET_SPARC) -#define float64_default_nan make_float64(LIT64( 0x7FFFFFFFFFFFFFFF )) -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) -#define float64_default_nan make_float64(LIT64( 0x7FF8000000000000 )) -#elif SNAN_BIT_IS_ONE -#define float64_default_nan make_float64(LIT64( 0x7FF7FFFFFFFFFFFF )) -#else -#define float64_default_nan make_float64(LIT64( 0xFFF8000000000000 )) -#endif +extern const float64 float64_default_nan; /*---------------------------------------------------------------------------- | Software IEC/IEEE extended double-precision conversion routines. @@ -561,17 +534,9 @@ INLINE int floatx80_is_any_nan(floatx80 a) #define floatx80_infinity make_floatx80(0x7fff, 0x8000000000000000LL) /*---------------------------------------------------------------------------- -| The pattern for a default generated extended double-precision NaN. The -| `high' and `low' values hold the most- and least-significant bits, -| respectively. +| The pattern for a default generated extended double-precision NaN. *----------------------------------------------------------------------------*/ -#if SNAN_BIT_IS_ONE -#define floatx80_default_nan_high 0x7FFF -#define floatx80_default_nan_low LIT64( 0xBFFFFFFFFFFFFFFF ) -#else -#define floatx80_default_nan_high 0xFFFF -#define floatx80_default_nan_low LIT64( 0xC000000000000000 ) -#endif +extern const floatx80 floatx80_default_nan; /*---------------------------------------------------------------------------- | Software IEC/IEEE quadruple-precision conversion routines. @@ -648,15 +613,8 @@ INLINE int float128_is_any_nan(float128 a) } /*---------------------------------------------------------------------------- -| The pattern for a default generated quadruple-precision NaN. The `high' and -| `low' values hold the most- and least-significant bits, respectively. +| The pattern for a default generated quadruple-precision NaN. *----------------------------------------------------------------------------*/ -#if SNAN_BIT_IS_ONE -#define float128_default_nan_high LIT64( 0x7FFF7FFFFFFFFFFF ) -#define float128_default_nan_low LIT64( 0xFFFFFFFFFFFFFFFF ) -#else -#define float128_default_nan_high LIT64( 0xFFFF800000000000 ) -#define float128_default_nan_low LIT64( 0x0000000000000000 ) -#endif +extern const float128 float128_default_nan; #endif /* !SOFTFLOAT_H */ diff --git a/hw/apb_pci.c b/hw/apb_pci.c index 974c87a8ce..8b9939c06a 100644 --- a/hw/apb_pci.c +++ b/hw/apb_pci.c @@ -34,6 +34,7 @@ #include "rwhandler.h" #include "apb_pci.h" #include "sysemu.h" +#include "exec-memory.h" /* debug APB */ //#define DEBUG_APB @@ -346,6 +347,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base, d->bus = pci_register_bus(&d->busdev.qdev, "pci", pci_apb_set_irq, pci_pbm_map_irq, d, + get_system_memory(), 0, 32); pci_bus_set_mem_base(d->bus, mem_base); diff --git a/hw/bonito.c b/hw/bonito.c index e8c57a36ff..5f62dda6e2 100644 --- a/hw/bonito.c +++ b/hw/bonito.c @@ -42,6 +42,7 @@ #include "mips.h" #include "pci_host.h" #include "sysemu.h" +#include "exec-memory.h" //#define DEBUG_BONITO @@ -773,7 +774,8 @@ PCIBus *bonito_init(qemu_irq *pic) dev = qdev_create(NULL, "Bonito-pcihost"); pcihost = FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev)); b = pci_register_bus(&pcihost->busdev.qdev, "pci", pci_bonito_set_irq, - pci_bonito_map_irq, pic, 0x28, 32); + pci_bonito_map_irq, pic, get_system_memory(), + 0x28, 32); pcihost->bus = b; qdev_init_nofail(dev); diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c index 34e7526d59..a29db9055d 100644 --- a/hw/fw_cfg.c +++ b/hw/fw_cfg.c @@ -26,6 +26,7 @@ #include "isa.h" #include "fw_cfg.h" #include "sysbus.h" +#include "qemu-error.h" /* debug firmware config */ //#define DEBUG_FW_CFG @@ -56,6 +57,143 @@ struct FWCfgState { Notifier machine_ready; }; +#define JPG_FILE 0 +#define BMP_FILE 1 + +static FILE *probe_splashfile(char *filename, int *file_sizep, int *file_typep) +{ + FILE *fp = NULL; + int fop_ret; + int file_size; + int file_type = -1; + unsigned char buf[2] = {0, 0}; + unsigned int filehead_value = 0; + int bmp_bpp; + + fp = fopen(filename, "rb"); + if (fp == NULL) { + error_report("failed to open file '%s'.", filename); + return fp; + } + /* check file size */ + fseek(fp, 0L, SEEK_END); + file_size = ftell(fp); + if (file_size < 2) { + error_report("file size is less than 2 bytes '%s'.", filename); + fclose(fp); + fp = NULL; + return fp; + } + /* check magic ID */ + fseek(fp, 0L, SEEK_SET); + fop_ret = fread(buf, 1, 2, fp); + filehead_value = (buf[0] + (buf[1] << 8)) & 0xffff; + if (filehead_value == 0xd8ff) { + file_type = JPG_FILE; + } else { + if (filehead_value == 0x4d42) { + file_type = BMP_FILE; + } + } + if (file_type < 0) { + error_report("'%s' not jpg/bmp file,head:0x%x.", + filename, filehead_value); + fclose(fp); + fp = NULL; + return fp; + } + /* check BMP bpp */ + if (file_type == BMP_FILE) { + fseek(fp, 28, SEEK_SET); + fop_ret = fread(buf, 1, 2, fp); + bmp_bpp = (buf[0] + (buf[1] << 8)) & 0xffff; + if (bmp_bpp != 24) { + error_report("only 24bpp bmp file is supported."); + fclose(fp); + fp = NULL; + return fp; + } + } + /* return values */ + *file_sizep = file_size; + *file_typep = file_type; + return fp; +} + +static void fw_cfg_bootsplash(FWCfgState *s) +{ + int boot_splash_time = -1; + const char *boot_splash_filename = NULL; + char *p; + char *filename; + FILE *fp; + int fop_ret; + int file_size; + int file_type = -1; + const char *temp; + + /* get user configuration */ + QemuOptsList *plist = qemu_find_opts("boot-opts"); + QemuOpts *opts = QTAILQ_FIRST(&plist->head); + if (opts != NULL) { + temp = qemu_opt_get(opts, "splash"); + if (temp != NULL) { + boot_splash_filename = temp; + } + temp = qemu_opt_get(opts, "splash-time"); + if (temp != NULL) { + p = (char *)temp; + boot_splash_time = strtol(p, (char **)&p, 10); + } + } + + /* insert splash time if user configurated */ + if (boot_splash_time >= 0) { + /* validate the input */ + if (boot_splash_time > 0xffff) { + error_report("splash time is big than 65535, force it to 65535."); + boot_splash_time = 0xffff; + } + /* use little endian format */ + qemu_extra_params_fw[0] = (uint8_t)(boot_splash_time & 0xff); + qemu_extra_params_fw[1] = (uint8_t)((boot_splash_time >> 8) & 0xff); + fw_cfg_add_file(s, "etc/boot-menu-wait", qemu_extra_params_fw, 2); + } + + /* insert splash file if user configurated */ + if (boot_splash_filename != NULL) { + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename); + if (filename == NULL) { + error_report("failed to find file '%s'.", boot_splash_filename); + return; + } + /* probing the file */ + fp = probe_splashfile(filename, &file_size, &file_type); + if (fp == NULL) { + qemu_free(filename); + return; + } + /* loading file data */ + if (boot_splash_filedata != NULL) { + qemu_free(boot_splash_filedata); + } + boot_splash_filedata = qemu_malloc(file_size); + boot_splash_filedata_size = file_size; + fseek(fp, 0L, SEEK_SET); + fop_ret = fread(boot_splash_filedata, 1, file_size, fp); + fclose(fp); + /* insert data */ + if (file_type == JPG_FILE) { + fw_cfg_add_file(s, "bootsplash.jpg", + boot_splash_filedata, boot_splash_filedata_size); + } else { + fw_cfg_add_file(s, "bootsplash.bmp", + boot_splash_filedata, boot_splash_filedata_size); + } + qemu_free(filename); + } +} + static void fw_cfg_write(FWCfgState *s, uint8_t value) { int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); @@ -352,7 +490,7 @@ FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port, fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); fw_cfg_add_i16(s, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu); - + fw_cfg_bootsplash(s); s->machine_ready.notify = fw_cfg_machine_ready; qemu_add_machine_init_done_notifier(&s->machine_ready); diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c index cee07e06c7..da67cf9b38 100644 --- a/hw/grackle_pci.c +++ b/hw/grackle_pci.c @@ -61,7 +61,8 @@ static void pci_grackle_reset(void *opaque) { } -PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic) +PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic, + MemoryRegion *address_space) { DeviceState *dev; SysBusDevice *s; @@ -74,7 +75,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic) d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", pci_grackle_set_irq, pci_grackle_map_irq, - pic, 0, 4); + pic, address_space, 0, 4); pci_create_simple(d->host_state.bus, 0, "grackle"); diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c index 8e1f6a069d..65e63ddab8 100644 --- a/hw/gt64xxx.c +++ b/hw/gt64xxx.c @@ -27,6 +27,7 @@ #include "pci.h" #include "pci_host.h" #include "pc.h" +#include "exec-memory.h" //#define DEBUG @@ -1092,7 +1093,8 @@ PCIBus *gt64120_register(qemu_irq *pic) d = FROM_SYSBUS(GT64120State, s); d->pci.bus = pci_register_bus(&d->busdev.qdev, "pci", gt64120_pci_set_irq, gt64120_pci_map_irq, - pic, PCI_DEVFN(18, 0), 4); + pic, get_system_memory(), + PCI_DEVFN(18, 0), 4); d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d, DEVICE_NATIVE_ENDIAN); @@ -324,6 +324,7 @@ typedef struct VMStateSubsection { struct VMStateDescription { const char *name; + int unmigratable; int version_id; int minimum_version_id; int minimum_version_id_old; diff --git a/hw/ide/ich.c b/hw/ide/ich.c index 054e0734e4..d241ea8005 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -72,6 +72,11 @@ #include <hw/ide/pci.h> #include <hw/ide/ahci.h> +static const VMStateDescription vmstate_ahci = { + .name = "ahci", + .unmigratable = 1, +}; + static int pci_ich9_ahci_init(PCIDevice *dev) { struct AHCIPCIState *d; @@ -123,6 +128,7 @@ static PCIDeviceInfo ich_ahci_info[] = { .qdev.name = "ich9-ahci", .qdev.alias = "ahci", .qdev.size = sizeof(AHCIPCIState), + .qdev.vmsd = &vmstate_ahci, .init = pci_ich9_ahci_init, .exit = pci_ich9_uninit, .config_write = pci_ich9_write_config, diff --git a/hw/multiboot.c b/hw/multiboot.c index 2426e84833..a1d3f41293 100644 --- a/hw/multiboot.c +++ b/hw/multiboot.c @@ -198,11 +198,14 @@ int load_multiboot(void *fw_cfg, } else { /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */ uint32_t mh_header_addr = ldl_p(header+i+12); + uint32_t mh_load_end_addr = ldl_p(header+i+20); + uint32_t mh_bss_end_addr = ldl_p(header+i+24); mh_load_addr = ldl_p(header+i+16); uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr); + uint32_t mb_load_size = mh_load_end_addr - mh_load_addr; mh_entry_addr = ldl_p(header+i+28); - mb_kernel_size = kernel_file_size - mb_kernel_text_offset; + mb_kernel_size = mh_bss_end_addr - mh_load_addr; /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE. uint32_t mh_mode_type = ldl_p(header+i+32); @@ -212,17 +215,18 @@ int load_multiboot(void *fw_cfg, mb_debug("multiboot: mh_header_addr = %#x\n", mh_header_addr); mb_debug("multiboot: mh_load_addr = %#x\n", mh_load_addr); - mb_debug("multiboot: mh_load_end_addr = %#x\n", ldl_p(header+i+20)); - mb_debug("multiboot: mh_bss_end_addr = %#x\n", ldl_p(header+i+24)); + mb_debug("multiboot: mh_load_end_addr = %#x\n", mh_load_end_addr); + mb_debug("multiboot: mh_bss_end_addr = %#x\n", mh_bss_end_addr); mb_debug("qemu: loading multiboot kernel (%#x bytes) at %#x\n", - mb_kernel_size, mh_load_addr); + mb_load_size, mh_load_addr); mbs.mb_buf = qemu_malloc(mb_kernel_size); fseek(f, mb_kernel_text_offset, SEEK_SET); - if (fread(mbs.mb_buf, 1, mb_kernel_size, f) != mb_kernel_size) { + if (fread(mbs.mb_buf, 1, mb_load_size, f) != mb_load_size) { fprintf(stderr, "fread() failed\n"); exit(1); } + memset(mbs.mb_buf + mb_load_size, 0, mb_kernel_size - mb_load_size); fclose(f); } @@ -41,6 +41,7 @@ #include "sysemu.h" #include "blockdev.h" #include "ui/qemu-spice.h" +#include "memory.h" /* output Bochs bios info messages */ //#define DEBUG_BIOS @@ -957,7 +958,8 @@ void pc_cpus_init(const char *cpu_model) } } -void pc_memory_init(const char *kernel_filename, +void pc_memory_init(MemoryRegion *system_memory, + const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, ram_addr_t below_4g_mem_size, @@ -965,22 +967,30 @@ void pc_memory_init(const char *kernel_filename, { char *filename; int ret, linux_boot, i; - ram_addr_t ram_addr, bios_offset, option_rom_offset; + MemoryRegion *ram, *bios, *isa_bios, *option_rom_mr; + MemoryRegion *ram_below_4g, *ram_above_4g; int bios_size, isa_bios_size; void *fw_cfg; linux_boot = (kernel_filename != NULL); - /* allocate RAM */ - ram_addr = qemu_ram_alloc(NULL, "pc.ram", - below_4g_mem_size + above_4g_mem_size); - cpu_register_physical_memory(0, 0xa0000, ram_addr); - cpu_register_physical_memory(0x100000, - below_4g_mem_size - 0x100000, - ram_addr + 0x100000); + /* Allocate RAM. We allocate it as a single memory region and use + * aliases to address portions of it, mostly for backwards compatiblity + * with older qemus that used qemu_ram_alloc(). + */ + ram = qemu_malloc(sizeof(*ram)); + memory_region_init_ram(ram, NULL, "pc.ram", + below_4g_mem_size + above_4g_mem_size); + ram_below_4g = qemu_malloc(sizeof(*ram_below_4g)); + memory_region_init_alias(ram_below_4g, "ram-below-4g", ram, + 0, below_4g_mem_size); + memory_region_add_subregion(system_memory, 0, ram_below_4g); if (above_4g_mem_size > 0) { - cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size, - ram_addr + below_4g_mem_size); + ram_above_4g = qemu_malloc(sizeof(*ram_above_4g)); + memory_region_init_alias(ram_above_4g, "ram-above-4g", ram, + below_4g_mem_size, above_4g_mem_size); + memory_region_add_subregion(system_memory, 0x100000000ULL, + ram_above_4g); } /* BIOS load */ @@ -996,7 +1006,9 @@ void pc_memory_init(const char *kernel_filename, (bios_size % 65536) != 0) { goto bios_error; } - bios_offset = qemu_ram_alloc(NULL, "pc.bios", bios_size); + bios = qemu_malloc(sizeof(*bios)); + memory_region_init_ram(bios, NULL, "pc.bios", bios_size); + memory_region_set_readonly(bios, true); ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1); if (ret != 0) { bios_error: @@ -1010,16 +1022,26 @@ void pc_memory_init(const char *kernel_filename, isa_bios_size = bios_size; if (isa_bios_size > (128 * 1024)) isa_bios_size = 128 * 1024; - cpu_register_physical_memory(0x100000 - isa_bios_size, - isa_bios_size, - (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); - - option_rom_offset = qemu_ram_alloc(NULL, "pc.rom", PC_ROM_SIZE); - cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset); + isa_bios = qemu_malloc(sizeof(*isa_bios)); + memory_region_init_alias(isa_bios, "isa-bios", bios, + bios_size - isa_bios_size, isa_bios_size); + memory_region_add_subregion_overlap(system_memory, + 0x100000 - isa_bios_size, + isa_bios, + 1); + memory_region_set_readonly(isa_bios, true); + + option_rom_mr = qemu_malloc(sizeof(*option_rom_mr)); + memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE); + memory_region_add_subregion_overlap(system_memory, + PC_ROM_MIN_VGA, + option_rom_mr, + 1); /* map all the bios at the top of memory */ - cpu_register_physical_memory((uint32_t)(-bios_size), - bios_size, bios_offset | IO_MEM_ROM); + memory_region_add_subregion(system_memory, + (uint32_t)(-bios_size), + bios); fw_cfg = bochs_bios_init(); rom_set_fw(fw_cfg); @@ -2,10 +2,12 @@ #define HW_PC_H #include "qemu-common.h" +#include "memory.h" #include "ioport.h" #include "isa.h" #include "fdc.h" #include "net.h" +#include "memory.h" /* PC-style peripherals (also used by other machines). */ @@ -129,7 +131,8 @@ void pc_cmos_set_s3_resume(void *opaque, int irq, int level); void pc_acpi_smi_interrupt(void *opaque, int irq, int level); void pc_cpus_init(const char *cpu_model); -void pc_memory_init(const char *kernel_filename, +void pc_memory_init(MemoryRegion *system_memory, + const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, ram_addr_t below_4g_mem_size, @@ -175,7 +178,9 @@ int pcspk_audio_init(qemu_irq *pic); struct PCII440FXState; typedef struct PCII440FXState PCII440FXState; -PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic, ram_addr_t ram_size); +PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, + qemu_irq *pic, MemoryRegion *address_space, + ram_addr_t ram_size); void i440fx_init_memory_mappings(PCII440FXState *d); /* piix4.c */ diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 40b73ea25c..c0a2abe4bc 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -39,6 +39,8 @@ #include "blockdev.h" #include "smbus.h" #include "xen.h" +#include "memory.h" +#include "exec-memory.h" #ifdef CONFIG_XEN # include <xen/hvm/hvm_info_table.h> #endif @@ -66,7 +68,8 @@ static void ioapic_init(IsaIrqState *isa_irq_state) } /* PC hardware initialisation */ -static void pc_init1(ram_addr_t ram_size, +static void pc_init1(MemoryRegion *system_memory, + ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -106,7 +109,8 @@ static void pc_init1(ram_addr_t ram_size, /* allocate ram and load rom/bios */ if (!xen_enabled()) { - pc_memory_init(kernel_filename, kernel_cmdline, initrd_filename, + pc_memory_init(system_memory, + kernel_filename, kernel_cmdline, initrd_filename, below_4g_mem_size, above_4g_mem_size); } @@ -124,7 +128,8 @@ static void pc_init1(ram_addr_t ram_size, isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24); if (pci_enabled) { - pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq, ram_size); + pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq, + system_memory, ram_size); } else { pci_bus = NULL; i440fx_state = NULL; @@ -212,7 +217,8 @@ static void pc_init_pci(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { - pc_init1(ram_size, boot_device, + pc_init1(get_system_memory(), + ram_size, boot_device, kernel_filename, kernel_cmdline, initrd_filename, cpu_model, 1, 1); } @@ -224,7 +230,8 @@ static void pc_init_pci_no_kvmclock(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { - pc_init1(ram_size, boot_device, + pc_init1(get_system_memory(), + ram_size, boot_device, kernel_filename, kernel_cmdline, initrd_filename, cpu_model, 1, 0); } @@ -238,7 +245,8 @@ static void pc_init_isa(ram_addr_t ram_size, { if (cpu_model == NULL) cpu_model = "486"; - pc_init1(ram_size, boot_device, + pc_init1(get_system_memory(), + ram_size, boot_device, kernel_filename, kernel_cmdline, initrd_filename, cpu_model, 0, 1); } @@ -263,11 +263,14 @@ int pci_find_domain(const PCIBus *bus) } void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, - const char *name, uint8_t devfn_min) + const char *name, + MemoryRegion *address_space, + uint8_t devfn_min) { qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name); assert(PCI_FUNC(devfn_min) == 0); bus->devfn_min = devfn_min; + bus->address_space = address_space; /* host bridge */ QLIST_INIT(&bus->child); @@ -276,13 +279,14 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, vmstate_register(NULL, -1, &vmstate_pcibus, bus); } -PCIBus *pci_bus_new(DeviceState *parent, const char *name, uint8_t devfn_min) +PCIBus *pci_bus_new(DeviceState *parent, const char *name, + MemoryRegion *address_space, uint8_t devfn_min) { PCIBus *bus; bus = qemu_mallocz(sizeof(*bus)); bus->qbus.qdev_allocated = 1; - pci_bus_new_inplace(bus, parent, name, devfn_min); + pci_bus_new_inplace(bus, parent, name, address_space, devfn_min); return bus; } @@ -310,11 +314,13 @@ void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base) PCIBus *pci_register_bus(DeviceState *parent, const char *name, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, - void *irq_opaque, uint8_t devfn_min, int nirq) + void *irq_opaque, + MemoryRegion *address_space, + uint8_t devfn_min, int nirq) { PCIBus *bus; - bus = pci_bus_new(parent, name, devfn_min); + bus = pci_bus_new(parent, name, address_space, devfn_min); pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); return bus; } @@ -838,10 +844,15 @@ static void pci_unregister_io_regions(PCIDevice *pci_dev) if (r->type == PCI_BASE_ADDRESS_SPACE_IO) { isa_unassign_ioport(r->addr, r->filtered_size); } else { - cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus, - r->addr), - r->filtered_size, - IO_MEM_UNASSIGNED); + if (r->memory) { + memory_region_del_subregion(pci_dev->bus->address_space, + r->memory); + } else { + cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus, + r->addr), + r->filtered_size, + IO_MEM_UNASSIGNED); + } } } } @@ -887,6 +898,7 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, r->type = type; r->map_func = map_func; r->ram_addr = IO_MEM_UNASSIGNED; + r->memory = NULL; wmask = ~(size - 1); addr = pci_bar(pci_dev, region_num); @@ -912,6 +924,16 @@ static void pci_simple_bar_mapfunc(PCIDevice *pci_dev, int region_num, pci_dev->io_regions[region_num].ram_addr); } +static void pci_simple_bar_mapfunc_region(PCIDevice *pci_dev, int region_num, + pcibus_t addr, pcibus_t size, + int type) +{ + memory_region_add_subregion_overlap(pci_dev->bus->address_space, + addr, + pci_dev->io_regions[region_num].memory, + 1); +} + void pci_register_bar_simple(PCIDevice *pci_dev, int region_num, pcibus_t size, uint8_t attr, ram_addr_t ram_addr) { @@ -921,6 +943,15 @@ void pci_register_bar_simple(PCIDevice *pci_dev, int region_num, pci_dev->io_regions[region_num].ram_addr = ram_addr; } +void pci_register_bar_region(PCIDevice *pci_dev, int region_num, + uint8_t attr, MemoryRegion *memory) +{ + pci_register_bar(pci_dev, region_num, memory_region_size(memory), + PCI_BASE_ADDRESS_SPACE_MEMORY | attr, + pci_simple_bar_mapfunc_region); + pci_dev->io_regions[region_num].memory = memory; +} + static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size, uint8_t type) { @@ -1059,10 +1090,16 @@ static void pci_update_mappings(PCIDevice *d) isa_unassign_ioport(r->addr, r->filtered_size); } } else { - cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr), - r->filtered_size, - IO_MEM_UNASSIGNED); - qemu_unregister_coalesced_mmio(r->addr, r->filtered_size); + if (r->memory) { + memory_region_del_subregion(d->bus->address_space, + r->memory); + } else { + cpu_register_physical_memory(pci_to_cpu_addr(d->bus, + r->addr), + r->filtered_size, + IO_MEM_UNASSIGNED); + qemu_unregister_coalesced_mmio(r->addr, r->filtered_size); + } } } r->addr = new_addr; @@ -5,6 +5,7 @@ #include "qobject.h" #include "qdev.h" +#include "memory.h" /* PCI includes legacy ISA access. */ #include "isa.h" @@ -93,6 +94,7 @@ typedef struct PCIIORegion { uint8_t type; PCIMapIORegionFunc *map_func; ram_addr_t ram_addr; + MemoryRegion *memory; } PCIIORegion; #define PCI_ROM_SLOT 6 @@ -203,6 +205,8 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, PCIMapIORegionFunc *map_func); void pci_register_bar_simple(PCIDevice *pci_dev, int region_num, pcibus_t size, uint8_t attr, ram_addr_t ram_addr); +void pci_register_bar_region(PCIDevice *pci_dev, int region_num, + uint8_t attr, MemoryRegion *memory); int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t offset, uint8_t size); @@ -233,15 +237,20 @@ typedef enum { typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, PCIHotplugState state); void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, - const char *name, uint8_t devfn_min); -PCIBus *pci_bus_new(DeviceState *parent, const char *name, uint8_t devfn_min); + const char *name, + MemoryRegion *address_space, + uint8_t devfn_min); +PCIBus *pci_bus_new(DeviceState *parent, const char *name, + MemoryRegion *address_space, uint8_t devfn_min); void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, void *irq_opaque, int nirq); int pci_bus_get_irq_level(PCIBus *bus, int irq_num); void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev); PCIBus *pci_register_bus(DeviceState *parent, const char *name, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, - void *irq_opaque, uint8_t devfn_min, int nirq); + void *irq_opaque, + MemoryRegion *address_space, + uint8_t devfn_min, int nirq); void pci_device_reset(PCIDevice *dev); void pci_bus_reset(PCIBus *bus); diff --git a/hw/pci_host.h b/hw/pci_host.h index 0a585951e0..05dcb662c6 100644 --- a/hw/pci_host.h +++ b/hw/pci_host.h @@ -35,6 +35,7 @@ struct PCIHostState { SysBusDevice busdev; ReadWriteHandler conf_handler; ReadWriteHandler data_handler; + MemoryRegion *address_space; uint32_t config_reg; PCIBus *bus; }; diff --git a/hw/pci_internals.h b/hw/pci_internals.h index fbe1866808..c3a463a703 100644 --- a/hw/pci_internals.h +++ b/hw/pci_internals.h @@ -25,6 +25,7 @@ struct PCIBus { PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX]; PCIDevice *parent_dev; target_phys_addr_t mem_base; + MemoryRegion *address_space; QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */ QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */ diff --git a/hw/piix_pci.c b/hw/piix_pci.c index d08b31a266..80d6665350 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -241,7 +241,9 @@ static int i440fx_initfn(PCIDevice *dev) static PCIBus *i440fx_common_init(const char *device_name, PCII440FXState **pi440fx_state, int *piix3_devfn, - qemu_irq *pic, ram_addr_t ram_size) + qemu_irq *pic, + MemoryRegion *address_space, + ram_addr_t ram_size) { DeviceState *dev; PCIBus *b; @@ -251,7 +253,8 @@ static PCIBus *i440fx_common_init(const char *device_name, dev = qdev_create(NULL, "i440FX-pcihost"); s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev)); - b = pci_bus_new(&s->busdev.qdev, NULL, 0); + s->address_space = address_space; + b = pci_bus_new(&s->busdev.qdev, NULL, s->address_space, 0); s->bus = b; qdev_init_nofail(dev); @@ -288,11 +291,13 @@ static PCIBus *i440fx_common_init(const char *device_name, } PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, - qemu_irq *pic, ram_addr_t ram_size) + qemu_irq *pic, MemoryRegion *address_space, + ram_addr_t ram_size) { PCIBus *b; - b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic, ram_size); + b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic, + address_space, ram_size); return b; } diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c index 299473c4b5..15c24f6e7a 100644 --- a/hw/ppc4xx_pci.c +++ b/hw/ppc4xx_pci.c @@ -24,6 +24,7 @@ #include "ppc4xx.h" #include "pci.h" #include "pci_host.h" +#include "exec-memory.h" #undef DEBUG #ifdef DEBUG @@ -345,7 +346,9 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], controller->pci_state.bus = pci_register_bus(NULL, "pci", ppc4xx_pci_set_irq, ppc4xx_pci_map_irq, - pci_irqs, 0, 4); + pci_irqs, + get_system_memory(), + 0, 4); controller->pci_dev = pci_register_device(controller->pci_state.bus, "host bridge", sizeof(PCIDevice), diff --git a/hw/ppc_mac.h b/hw/ppc_mac.h index 68dade7e40..6fad20a745 100644 --- a/hw/ppc_mac.h +++ b/hw/ppc_mac.h @@ -25,6 +25,8 @@ #if !defined(__PPC_MAC_H__) #define __PPC_MAC_H__ +#include "memory.h" + /* SMP is not enabled, for now */ #define MAX_CPUS 1 @@ -52,11 +54,12 @@ qemu_irq *heathrow_pic_init(int *pmem_index, int nb_cpus, qemu_irq **irqs); /* Grackle PCI */ -PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic); +PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic, + MemoryRegion *address_space); /* UniNorth PCI */ -PCIBus *pci_pmac_init(qemu_irq *pic); -PCIBus *pci_pmac_u3_init(qemu_irq *pic); +PCIBus *pci_pmac_init(qemu_irq *pic, MemoryRegion *address_space); +PCIBus *pci_pmac_u3_init(qemu_irq *pic, MemoryRegion *address_space); /* Mac NVRAM */ typedef struct MacIONVRAMState MacIONVRAMState; diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c index 5bce709bab..2c0fae8ef3 100644 --- a/hw/ppc_newworld.c +++ b/hw/ppc_newworld.c @@ -67,6 +67,7 @@ #include "kvm_ppc.h" #include "hw/usb.h" #include "blockdev.h" +#include "exec-memory.h" #define MAX_IDE_BUS 2 #define CFG_ADDR 0xf0000510 @@ -317,10 +318,10 @@ static void ppc_core99_init (ram_addr_t ram_size, pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL); if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { /* 970 gets a U3 bus */ - pci_bus = pci_pmac_u3_init(pic); + pci_bus = pci_pmac_u3_init(pic, get_system_memory()); machine_arch = ARCH_MAC99_U3; } else { - pci_bus = pci_pmac_init(pic); + pci_bus = pci_pmac_init(pic, get_system_memory()); machine_arch = ARCH_MAC99; } /* init basic PC hardware */ diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c index 20cd8e1a8d..585afd6c4b 100644 --- a/hw/ppc_oldworld.c +++ b/hw/ppc_oldworld.c @@ -43,6 +43,7 @@ #include "kvm.h" #include "kvm_ppc.h" #include "blockdev.h" +#include "exec-memory.h" #define MAX_IDE_BUS 2 #define CFG_ADDR 0xf0000510 @@ -233,7 +234,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, hw_error("Only 6xx bus is supported on heathrow machine\n"); } pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs); - pci_bus = pci_grackle_init(0xfec00000, pic); + pci_bus = pci_grackle_init(0xfec00000, pic, get_system_memory()); pci_vga_init(pci_bus); escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0], diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index 0e9cfc24cd..91ebe07dcd 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -38,6 +38,7 @@ #include "loader.h" #include "mc146818rtc.h" #include "blockdev.h" +#include "exec-memory.h" //#define HARD_DEBUG_PPC_IO //#define DEBUG_PPC_IO @@ -648,7 +649,7 @@ static void ppc_prep_init (ram_addr_t ram_size, hw_error("Only 6xx bus is supported on PREP machine\n"); } i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); - pci_bus = pci_prep_init(i8259); + pci_bus = pci_prep_init(i8259, get_system_memory()); /* Hmm, prep has no pci-isa bridge ??? */ isa_bus_new(NULL); isa_bus_irqs(i8259); diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c index fc11af4374..134453965b 100644 --- a/hw/ppce500_pci.c +++ b/hw/ppce500_pci.c @@ -274,12 +274,15 @@ static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base) s->reg); } +#include "exec-memory.h" + static int e500_pcihost_initfn(SysBusDevice *dev) { PCIHostState *h; PPCE500PCIState *s; PCIBus *b; int i; + MemoryRegion *address_space = get_system_memory(); h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); s = DO_UPCAST(PPCE500PCIState, pci_state, h); @@ -289,7 +292,8 @@ static int e500_pcihost_initfn(SysBusDevice *dev) } b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq, - mpc85xx_pci_map_irq, s->irq, PCI_DEVFN(0x11, 0), 4); + mpc85xx_pci_map_irq, s->irq, address_space, + PCI_DEVFN(0x11, 0), 4); s->pci_state.bus = b; pci_create_simple(b, 0, "e500-host-bridge"); diff --git a/hw/prep_pci.c b/hw/prep_pci.c index f88b8254c2..da02f0ea8e 100644 --- a/hw/prep_pci.c +++ b/hw/prep_pci.c @@ -110,7 +110,7 @@ static void prep_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level); } -PCIBus *pci_prep_init(qemu_irq *pic) +PCIBus *pci_prep_init(qemu_irq *pic, MemoryRegion *address_space) { PREPPCIState *s; PCIDevice *d; @@ -118,7 +118,8 @@ PCIBus *pci_prep_init(qemu_irq *pic) s = qemu_mallocz(sizeof(PREPPCIState)); s->bus = pci_register_bus(NULL, "pci", - prep_set_irq, prep_map_irq, pic, 0, 4); + prep_set_irq, prep_map_irq, pic, + address_space, 0, 4); pci_host_conf_register_ioport(0xcf8, s); diff --git a/hw/prep_pci.h b/hw/prep_pci.h index cd6851288c..a27368b99b 100644 --- a/hw/prep_pci.h +++ b/hw/prep_pci.h @@ -2,7 +2,8 @@ #define QEMU_PREP_PCI_H #include "qemu-common.h" +#include "memory.h" -PCIBus *pci_prep_init(qemu_irq *pic); +PCIBus *pci_prep_init(qemu_irq *pic, MemoryRegion *address_space); #endif @@ -289,6 +289,9 @@ int qdev_init(DeviceState *dev) dev->alias_required_for_version); } dev->state = DEV_STATE_INITIALIZED; + if (dev->hotplugged && dev->info->reset) { + dev->info->reset(dev); + } return 0; } @@ -1450,14 +1450,8 @@ void sd_write_data(SDState *sd, uint8_t value) break; case 25: /* CMD25: WRITE_MULTIPLE_BLOCK */ - sd->data[sd->data_offset ++] = value; - if (sd->data_offset >= sd->blk_len) { - /* TODO: Check CRC before committing */ - sd->state = sd_programming_state; - BLK_WRITE_BLOCK(sd->data_start, sd->data_offset); - sd->blk_written ++; - sd->data_start += sd->blk_len; - sd->data_offset = 0; + if (sd->data_offset == 0) { + /* Start of the block - lets check the address is valid */ if (sd->data_start + sd->blk_len > sd->size) { sd->card_status |= ADDRESS_ERROR; break; @@ -1466,6 +1460,15 @@ void sd_write_data(SDState *sd, uint8_t value) sd->card_status |= WP_VIOLATION; break; } + } + sd->data[sd->data_offset++] = value; + if (sd->data_offset >= sd->blk_len) { + /* TODO: Check CRC before committing */ + sd->state = sd_programming_state; + BLK_WRITE_BLOCK(sd->data_start, sd->data_offset); + sd->blk_written++; + sd->data_start += sd->blk_len; + sd->data_offset = 0; sd->csd[14] |= 0x40; /* Bzzzzzzztt .... Operation complete. */ diff --git a/hw/sh_pci.c b/hw/sh_pci.c index a076cf2ff0..0ef93a062e 100644 --- a/hw/sh_pci.c +++ b/hw/sh_pci.c @@ -26,6 +26,7 @@ #include "pci.h" #include "pci_host.h" #include "bswap.h" +#include "exec-memory.h" typedef struct SHPCIState { SysBusDevice busdev; @@ -127,7 +128,8 @@ static int sh_pci_init_device(SysBusDevice *dev) } s->bus = pci_register_bus(&s->busdev.qdev, "pci", sh_pci_set_irq, sh_pci_map_irq, - s->irq, PCI_DEVFN(0, 0), 4); + s->irq, get_system_memory(), + PCI_DEVFN(0, 0), 4); s->memconfig = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio_cb(dev, 0x224, sh_pci_map); diff --git a/hw/sysbus.c b/hw/sysbus.c index 2e22be7b25..ea442acb50 100644 --- a/hw/sysbus.c +++ b/hw/sysbus.c @@ -19,6 +19,7 @@ #include "sysbus.h" #include "monitor.h" +#include "exec-memory.h" static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent); static char *sysbus_get_fw_dev_path(DeviceState *dev); @@ -49,11 +50,20 @@ void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr) } if (dev->mmio[n].addr != (target_phys_addr_t)-1) { /* Unregister previous mapping. */ - cpu_register_physical_memory(dev->mmio[n].addr, dev->mmio[n].size, - IO_MEM_UNASSIGNED); + if (dev->mmio[n].memory) { + memory_region_del_subregion(get_system_memory(), + dev->mmio[n].memory); + } else { + cpu_register_physical_memory(dev->mmio[n].addr, dev->mmio[n].size, + IO_MEM_UNASSIGNED); + } } dev->mmio[n].addr = addr; - if (dev->mmio[n].cb) { + if (dev->mmio[n].memory) { + memory_region_add_subregion(get_system_memory(), + addr, + dev->mmio[n].memory); + } else if (dev->mmio[n].cb) { dev->mmio[n].cb(dev, addr); } else { cpu_register_physical_memory(addr, dev->mmio[n].size, @@ -107,6 +117,17 @@ void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size, dev->mmio[n].cb = cb; } +void sysbus_init_mmio_region(SysBusDevice *dev, MemoryRegion *memory) +{ + int n; + + assert(dev->num_mmio < QDEV_MAX_MMIO); + n = dev->num_mmio++; + dev->mmio[n].addr = -1; + dev->mmio[n].size = memory_region_size(memory); + dev->mmio[n].memory = memory; +} + void sysbus_init_ioports(SysBusDevice *dev, pio_addr_t ioport, pio_addr_t size) { pio_addr_t i; diff --git a/hw/sysbus.h b/hw/sysbus.h index 4e8cb16d42..5f62e2da31 100644 --- a/hw/sysbus.h +++ b/hw/sysbus.h @@ -4,6 +4,7 @@ /* Devices attached directly to the main system bus. */ #include "qdev.h" +#include "memory.h" #define QDEV_MAX_MMIO 32 #define QDEV_MAX_PIO 32 @@ -23,6 +24,7 @@ struct SysBusDevice { target_phys_addr_t size; mmio_mapfunc cb; ram_addr_t iofunc; + MemoryRegion *memory; } mmio[QDEV_MAX_MMIO]; int num_pio; pio_addr_t pio[QDEV_MAX_PIO]; @@ -46,6 +48,7 @@ void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size, ram_addr_t iofunc); void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size, mmio_mapfunc cb); +void sysbus_init_mmio_region(SysBusDevice *dev, MemoryRegion *memory); void sysbus_init_irq(SysBusDevice *dev, qemu_irq *p); void sysbus_pass_irq(SysBusDevice *dev, SysBusDevice *target); void sysbus_init_ioports(SysBusDevice *dev, pio_addr_t ioport, pio_addr_t size); diff --git a/hw/unin_pci.c b/hw/unin_pci.c index d364daa53a..b499523c93 100644 --- a/hw/unin_pci.c +++ b/hw/unin_pci.c @@ -201,7 +201,7 @@ static int pci_unin_internal_init_device(SysBusDevice *dev) return 0; } -PCIBus *pci_pmac_init(qemu_irq *pic) +PCIBus *pci_pmac_init(qemu_irq *pic, MemoryRegion *address_space) { DeviceState *dev; SysBusDevice *s; @@ -215,7 +215,8 @@ PCIBus *pci_pmac_init(qemu_irq *pic) d = FROM_SYSBUS(UNINState, s); d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", pci_unin_set_irq, pci_unin_map_irq, - pic, PCI_DEVFN(11, 0), 4); + pic, address_space, + PCI_DEVFN(11, 0), 4); #if 0 pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north"); @@ -252,7 +253,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic) return d->host_state.bus; } -PCIBus *pci_pmac_u3_init(qemu_irq *pic) +PCIBus *pci_pmac_u3_init(qemu_irq *pic, MemoryRegion *address_space) { DeviceState *dev; SysBusDevice *s; @@ -267,7 +268,8 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic) d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", pci_unin_set_irq, pci_unin_map_irq, - pic, PCI_DEVFN(11, 0), 4); + pic, address_space, + PCI_DEVFN(11, 0), 4); sysbus_mmio_map(s, 0, 0xf0800000); sysbus_mmio_map(s, 1, 0xf0c00000); diff --git a/hw/usb-bt.c b/hw/usb-bt.c index e364513a01..4557802bbc 100644 --- a/hw/usb-bt.c +++ b/hw/usb-bt.c @@ -548,10 +548,16 @@ USBDevice *usb_bt_init(HCIInfo *hci) return dev; } +static const VMStateDescription vmstate_usb_bt = { + .name = "usb-bt", + .unmigratable = 1, +}; + static struct USBDeviceInfo bt_info = { .product_desc = "QEMU BT dongle", .qdev.name = "usb-bt-dongle", .qdev.size = sizeof(struct USBBtState), + .qdev.vmsd = &vmstate_usb_bt, .usb_desc = &desc_bluetooth, .init = usb_bt_initfn, .handle_packet = usb_generic_handle_packet, diff --git a/hw/usb-ehci.c b/hw/usb-ehci.c index a4758f976e..8b0dcc335d 100644 --- a/hw/usb-ehci.c +++ b/hw/usb-ehci.c @@ -2244,6 +2244,11 @@ static USBBusOps ehci_bus_ops = { .register_companion = ehci_register_companion, }; +static const VMStateDescription vmstate_ehci = { + .name = "ehci", + .unmigratable = 1, +}; + static Property ehci_properties[] = { DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ), DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), @@ -2254,6 +2259,7 @@ static PCIDeviceInfo ehci_info[] = { { .qdev.name = "usb-ehci", .qdev.size = sizeof(EHCIState), + .qdev.vmsd = &vmstate_ehci, .init = usb_ehci_initfn, .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801D, /* ich4 */ @@ -2263,6 +2269,7 @@ static PCIDeviceInfo ehci_info[] = { },{ .qdev.name = "ich9-usb-ehci1", .qdev.size = sizeof(EHCIState), + .qdev.vmsd = &vmstate_ehci, .init = usb_ehci_initfn, .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1, diff --git a/hw/usb-msd.c b/hw/usb-msd.c index 6391dad108..cdeac581e3 100644 --- a/hw/usb-msd.c +++ b/hw/usb-msd.c @@ -616,11 +616,23 @@ static USBDevice *usb_msd_init(const char *filename) return dev; } +static const VMStateDescription vmstate_usb_msd = { + .name = "usb-storage", + .unmigratable = 1, /* FIXME: handle transactions which are in flight */ + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField []) { + VMSTATE_USB_DEVICE(dev, MSDState), + VMSTATE_END_OF_LIST() + } +}; + static struct USBDeviceInfo msd_info = { .product_desc = "QEMU USB MSD", .qdev.name = "usb-storage", .qdev.fw_name = "storage", .qdev.size = sizeof(MSDState), + .qdev.vmsd = &vmstate_usb_msd, .usb_desc = &desc, .init = usb_msd_initfn, .handle_packet = usb_generic_handle_packet, diff --git a/hw/usb-net.c b/hw/usb-net.c index 9be709f7cf..4212e5b3c5 100644 --- a/hw/usb-net.c +++ b/hw/usb-net.c @@ -1414,11 +1414,17 @@ static USBDevice *usb_net_init(const char *cmdline) return dev; } +static const VMStateDescription vmstate_usb_net = { + .name = "usb-net", + .unmigratable = 1, +}; + static struct USBDeviceInfo net_info = { .product_desc = "QEMU USB Network Interface", .qdev.name = "usb-net", .qdev.fw_name = "network", .qdev.size = sizeof(USBNetState), + .qdev.vmsd = &vmstate_usb_net, .usb_desc = &desc_net, .init = usb_net_initfn, .handle_packet = usb_generic_handle_packet, diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c index 8491d59928..337b250261 100644 --- a/hw/usb-ohci.c +++ b/hw/usb-ohci.c @@ -62,7 +62,7 @@ typedef struct OHCIPort { typedef struct { USBBus bus; qemu_irq irq; - int mem; + MemoryRegion mem; int num_ports; const char *name; @@ -1440,13 +1440,13 @@ static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) return; } -static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr) +static uint64_t ohci_mem_read(void *opaque, + target_phys_addr_t addr, + unsigned size) { - OHCIState *ohci = ptr; + OHCIState *ohci = opaque; uint32_t retval; - addr &= 0xff; - /* Only aligned reads are allowed on OHCI */ if (addr & 3) { fprintf(stderr, "usb-ohci: Mis-aligned read\n"); @@ -1563,11 +1563,12 @@ static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr) return retval; } -static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val) +static void ohci_mem_write(void *opaque, + target_phys_addr_t addr, + uint64_t val, + unsigned size) { - OHCIState *ohci = ptr; - - addr &= 0xff; + OHCIState *ohci = opaque; /* Only aligned reads are allowed on OHCI */ if (addr & 3) { @@ -1697,18 +1698,10 @@ static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev) } } -/* Only dword reads are defined on OHCI register space */ -static CPUReadMemoryFunc * const ohci_readfn[3]={ - ohci_mem_read, - ohci_mem_read, - ohci_mem_read -}; - -/* Only dword writes are defined on OHCI register space */ -static CPUWriteMemoryFunc * const ohci_writefn[3]={ - ohci_mem_write, - ohci_mem_write, - ohci_mem_write +static const MemoryRegionOps ohci_mem_ops = { + .read = ohci_mem_read, + .write = ohci_mem_write, + .endianness = DEVICE_LITTLE_ENDIAN, }; static USBPortOps ohci_port_ops = { @@ -1764,8 +1757,7 @@ static int usb_ohci_init(OHCIState *ohci, DeviceState *dev, } } - ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci, - DEVICE_LITTLE_ENDIAN); + memory_region_init_io(&ohci->mem, &ohci_mem_ops, ohci, "ohci", 256); ohci->localmem_base = localmem_base; ohci->name = dev->info->name; @@ -1799,7 +1791,7 @@ static int usb_ohci_initfn_pci(struct PCIDevice *dev) ohci->state.irq = ohci->pci_dev.irq[0]; /* TODO: avoid cast below by using dev */ - pci_register_bar_simple(&ohci->pci_dev, 0, 256, 0, ohci->state.mem); + pci_register_bar_region(&ohci->pci_dev, 0, 0, &ohci->state.mem); return 0; } @@ -1822,7 +1814,7 @@ static int ohci_init_pxa(SysBusDevice *dev) /* Cannot fail as we pass NULL for masterbus */ usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset, NULL, 0); sysbus_init_irq(dev, &s->ohci.irq); - sysbus_init_mmio(dev, 0x1000, s->ohci.mem); + sysbus_init_mmio_region(dev, &s->ohci.mem); return 0; } diff --git a/hw/usb-serial.c b/hw/usb-serial.c index c69c4374e1..298c1e9d95 100644 --- a/hw/usb-serial.c +++ b/hw/usb-serial.c @@ -566,10 +566,16 @@ static USBDevice *usb_braille_init(const char *unused) return dev; } +static const VMStateDescription vmstate_usb_serial = { + .name = "usb-serial", + .unmigratable = 1, +}; + static struct USBDeviceInfo serial_info = { .product_desc = "QEMU USB Serial", .qdev.name = "usb-serial", .qdev.size = sizeof(USBSerialState), + .qdev.vmsd = &vmstate_usb_serial, .usb_desc = &desc_serial, .init = usb_serial_initfn, .handle_packet = usb_generic_handle_packet, @@ -589,6 +595,7 @@ static struct USBDeviceInfo braille_info = { .product_desc = "QEMU USB Braille", .qdev.name = "usb-braille", .qdev.size = sizeof(USBSerialState), + .qdev.vmsd = &vmstate_usb_serial, .usb_desc = &desc_braille, .init = usb_serial_initfn, .handle_packet = usb_generic_handle_packet, diff --git a/hw/usb-wacom.c b/hw/usb-wacom.c index 9d348e170e..d76ee97e49 100644 --- a/hw/usb-wacom.c +++ b/hw/usb-wacom.c @@ -349,6 +349,11 @@ static int usb_wacom_initfn(USBDevice *dev) return 0; } +static const VMStateDescription vmstate_usb_wacom = { + .name = "usb-wacom", + .unmigratable = 1, +}; + static struct USBDeviceInfo wacom_info = { .product_desc = "QEMU PenPartner Tablet", .qdev.name = "usb-wacom-tablet", @@ -356,6 +361,7 @@ static struct USBDeviceInfo wacom_info = { .usbdevice_name = "wacom-tablet", .usb_desc = &desc_wacom, .qdev.size = sizeof(USBWacomState), + .qdev.vmsd = &vmstate_usb_wacom, .init = usb_wacom_initfn, .handle_packet = usb_generic_handle_packet, .handle_reset = usb_wacom_handle_reset, diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c index 290a9009b2..cffe387187 100644 --- a/hw/versatile_pci.c +++ b/hw/versatile_pci.c @@ -10,6 +10,7 @@ #include "sysbus.h" #include "pci.h" #include "pci_host.h" +#include "exec-memory.h" typedef struct { SysBusDevice busdev; @@ -111,6 +112,7 @@ static int pci_vpb_init(SysBusDevice *dev) } bus = pci_register_bus(&dev->qdev, "pci", pci_vpb_set_irq, pci_vpb_map_irq, s->irq, + get_system_memory(), PCI_DEVFN(11, 0), 4); /* ??? Register memory space. */ @@ -146,7 +146,7 @@ int register_ioport_read(pio_addr_t start, int length, int size, hw_error("register_ioport_read: invalid size"); return -1; } - for(i = start; i < start + length; i += size) { + for(i = start; i < start + length; ++i) { ioport_read_table[bsize][i] = func; if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque) hw_error("register_ioport_read: invalid opaque for address 0x%x", @@ -166,7 +166,7 @@ int register_ioport_write(pio_addr_t start, int length, int size, hw_error("register_ioport_write: invalid size"); return -1; } - for(i = start; i < start + length; i += size) { + for(i = start; i < start + length; ++i) { ioport_write_table[bsize][i] = func; if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque) hw_error("register_ioport_write: invalid opaque for address 0x%x", diff --git a/memory.c b/memory.c new file mode 100644 index 0000000000..5c6e63df3f --- /dev/null +++ b/memory.c @@ -0,0 +1,1141 @@ +/* + * Physical memory management + * + * Copyright 2011 Red Hat, Inc. and/or its affiliates + * + * Authors: + * Avi Kivity <avi@redhat.com> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + */ + +#include "memory.h" +#include "exec-memory.h" +#include "ioport.h" +#include "bitops.h" +#include "kvm.h" +#include <assert.h> + +unsigned memory_region_transaction_depth = 0; + +typedef struct AddrRange AddrRange; + +struct AddrRange { + uint64_t start; + uint64_t size; +}; + +static AddrRange addrrange_make(uint64_t start, uint64_t size) +{ + return (AddrRange) { start, size }; +} + +static bool addrrange_equal(AddrRange r1, AddrRange r2) +{ + return r1.start == r2.start && r1.size == r2.size; +} + +static uint64_t addrrange_end(AddrRange r) +{ + return r.start + r.size; +} + +static AddrRange addrrange_shift(AddrRange range, int64_t delta) +{ + range.start += delta; + return range; +} + +static bool addrrange_intersects(AddrRange r1, AddrRange r2) +{ + return (r1.start >= r2.start && r1.start < r2.start + r2.size) + || (r2.start >= r1.start && r2.start < r1.start + r1.size); +} + +static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2) +{ + uint64_t start = MAX(r1.start, r2.start); + /* off-by-one arithmetic to prevent overflow */ + uint64_t end = MIN(addrrange_end(r1) - 1, addrrange_end(r2) - 1); + return addrrange_make(start, end - start + 1); +} + +struct CoalescedMemoryRange { + AddrRange addr; + QTAILQ_ENTRY(CoalescedMemoryRange) link; +}; + +struct MemoryRegionIoeventfd { + AddrRange addr; + bool match_data; + uint64_t data; + int fd; +}; + +static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a, + MemoryRegionIoeventfd b) +{ + if (a.addr.start < b.addr.start) { + return true; + } else if (a.addr.start > b.addr.start) { + return false; + } else if (a.addr.size < b.addr.size) { + return true; + } else if (a.addr.size > b.addr.size) { + return false; + } else if (a.match_data < b.match_data) { + return true; + } else if (a.match_data > b.match_data) { + return false; + } else if (a.match_data) { + if (a.data < b.data) { + return true; + } else if (a.data > b.data) { + return false; + } + } + if (a.fd < b.fd) { + return true; + } else if (a.fd > b.fd) { + return false; + } + return false; +} + +static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a, + MemoryRegionIoeventfd b) +{ + return !memory_region_ioeventfd_before(a, b) + && !memory_region_ioeventfd_before(b, a); +} + +typedef struct FlatRange FlatRange; +typedef struct FlatView FlatView; + +/* Range of memory in the global map. Addresses are absolute. */ +struct FlatRange { + MemoryRegion *mr; + target_phys_addr_t offset_in_region; + AddrRange addr; + uint8_t dirty_log_mask; +}; + +/* Flattened global view of current active memory hierarchy. Kept in sorted + * order. + */ +struct FlatView { + FlatRange *ranges; + unsigned nr; + unsigned nr_allocated; +}; + +typedef struct AddressSpace AddressSpace; +typedef struct AddressSpaceOps AddressSpaceOps; + +/* A system address space - I/O, memory, etc. */ +struct AddressSpace { + const AddressSpaceOps *ops; + MemoryRegion *root; + FlatView current_map; + int ioeventfd_nb; + MemoryRegionIoeventfd *ioeventfds; +}; + +struct AddressSpaceOps { + void (*range_add)(AddressSpace *as, FlatRange *fr); + void (*range_del)(AddressSpace *as, FlatRange *fr); + void (*log_start)(AddressSpace *as, FlatRange *fr); + void (*log_stop)(AddressSpace *as, FlatRange *fr); + void (*ioeventfd_add)(AddressSpace *as, MemoryRegionIoeventfd *fd); + void (*ioeventfd_del)(AddressSpace *as, MemoryRegionIoeventfd *fd); +}; + +#define FOR_EACH_FLAT_RANGE(var, view) \ + for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var) + +static bool flatrange_equal(FlatRange *a, FlatRange *b) +{ + return a->mr == b->mr + && addrrange_equal(a->addr, b->addr) + && a->offset_in_region == b->offset_in_region; +} + +static void flatview_init(FlatView *view) +{ + view->ranges = NULL; + view->nr = 0; + view->nr_allocated = 0; +} + +/* Insert a range into a given position. Caller is responsible for maintaining + * sorting order. + */ +static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range) +{ + if (view->nr == view->nr_allocated) { + view->nr_allocated = MAX(2 * view->nr, 10); + view->ranges = qemu_realloc(view->ranges, + view->nr_allocated * sizeof(*view->ranges)); + } + memmove(view->ranges + pos + 1, view->ranges + pos, + (view->nr - pos) * sizeof(FlatRange)); + view->ranges[pos] = *range; + ++view->nr; +} + +static void flatview_destroy(FlatView *view) +{ + qemu_free(view->ranges); +} + +static bool can_merge(FlatRange *r1, FlatRange *r2) +{ + return addrrange_end(r1->addr) == r2->addr.start + && r1->mr == r2->mr + && r1->offset_in_region + r1->addr.size == r2->offset_in_region + && r1->dirty_log_mask == r2->dirty_log_mask; +} + +/* Attempt to simplify a view by merging ajacent ranges */ +static void flatview_simplify(FlatView *view) +{ + unsigned i, j; + + i = 0; + while (i < view->nr) { + j = i + 1; + while (j < view->nr + && can_merge(&view->ranges[j-1], &view->ranges[j])) { + view->ranges[i].addr.size += view->ranges[j].addr.size; + ++j; + } + ++i; + memmove(&view->ranges[i], &view->ranges[j], + (view->nr - j) * sizeof(view->ranges[j])); + view->nr -= j - i; + } +} + +static void memory_region_prepare_ram_addr(MemoryRegion *mr); + +static void as_memory_range_add(AddressSpace *as, FlatRange *fr) +{ + ram_addr_t phys_offset, region_offset; + + memory_region_prepare_ram_addr(fr->mr); + + phys_offset = fr->mr->ram_addr; + region_offset = fr->offset_in_region; + /* cpu_register_physical_memory_log() wants region_offset for + * mmio, but prefers offseting phys_offset for RAM. Humour it. + */ + if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { + phys_offset += region_offset; + region_offset = 0; + } + + cpu_register_physical_memory_log(fr->addr.start, + fr->addr.size, + phys_offset, + region_offset, + fr->dirty_log_mask); +} + +static void as_memory_range_del(AddressSpace *as, FlatRange *fr) +{ + cpu_register_physical_memory(fr->addr.start, fr->addr.size, + IO_MEM_UNASSIGNED); +} + +static void as_memory_log_start(AddressSpace *as, FlatRange *fr) +{ + cpu_physical_log_start(fr->addr.start, fr->addr.size); +} + +static void as_memory_log_stop(AddressSpace *as, FlatRange *fr) +{ + cpu_physical_log_stop(fr->addr.start, fr->addr.size); +} + +static void as_memory_ioeventfd_add(AddressSpace *as, MemoryRegionIoeventfd *fd) +{ + int r; + + assert(fd->match_data && fd->addr.size == 4); + + r = kvm_set_ioeventfd_mmio_long(fd->fd, fd->addr.start, fd->data, true); + if (r < 0) { + abort(); + } +} + +static void as_memory_ioeventfd_del(AddressSpace *as, MemoryRegionIoeventfd *fd) +{ + int r; + + r = kvm_set_ioeventfd_mmio_long(fd->fd, fd->addr.start, fd->data, false); + if (r < 0) { + abort(); + } +} + +static const AddressSpaceOps address_space_ops_memory = { + .range_add = as_memory_range_add, + .range_del = as_memory_range_del, + .log_start = as_memory_log_start, + .log_stop = as_memory_log_stop, + .ioeventfd_add = as_memory_ioeventfd_add, + .ioeventfd_del = as_memory_ioeventfd_del, +}; + +static AddressSpace address_space_memory = { + .ops = &address_space_ops_memory, +}; + +static const MemoryRegionPortio *find_portio(MemoryRegion *mr, uint64_t offset, + unsigned width, bool write) +{ + const MemoryRegionPortio *mrp; + + for (mrp = mr->ops->old_portio; mrp->size; ++mrp) { + if (offset >= mrp->offset && offset < mrp->offset + mrp->len + && width == mrp->size + && (write ? (bool)mrp->write : (bool)mrp->read)) { + return mrp; + } + } + return NULL; +} + +static void memory_region_iorange_read(IORange *iorange, + uint64_t offset, + unsigned width, + uint64_t *data) +{ + MemoryRegion *mr = container_of(iorange, MemoryRegion, iorange); + + if (mr->ops->old_portio) { + const MemoryRegionPortio *mrp = find_portio(mr, offset, width, false); + + *data = ((uint64_t)1 << (width * 8)) - 1; + if (mrp) { + *data = mrp->read(mr->opaque, offset - mrp->offset); + } + return; + } + *data = mr->ops->read(mr->opaque, offset, width); +} + +static void memory_region_iorange_write(IORange *iorange, + uint64_t offset, + unsigned width, + uint64_t data) +{ + MemoryRegion *mr = container_of(iorange, MemoryRegion, iorange); + + if (mr->ops->old_portio) { + const MemoryRegionPortio *mrp = find_portio(mr, offset, width, true); + + if (mrp) { + mrp->write(mr->opaque, offset - mrp->offset, data); + } + return; + } + mr->ops->write(mr->opaque, offset, data, width); +} + +static const IORangeOps memory_region_iorange_ops = { + .read = memory_region_iorange_read, + .write = memory_region_iorange_write, +}; + +static void as_io_range_add(AddressSpace *as, FlatRange *fr) +{ + iorange_init(&fr->mr->iorange, &memory_region_iorange_ops, + fr->addr.start,fr->addr.size); + ioport_register(&fr->mr->iorange); +} + +static void as_io_range_del(AddressSpace *as, FlatRange *fr) +{ + isa_unassign_ioport(fr->addr.start, fr->addr.size); +} + +static void as_io_ioeventfd_add(AddressSpace *as, MemoryRegionIoeventfd *fd) +{ + int r; + + assert(fd->match_data && fd->addr.size == 2); + + r = kvm_set_ioeventfd_pio_word(fd->fd, fd->addr.start, fd->data, true); + if (r < 0) { + abort(); + } +} + +static void as_io_ioeventfd_del(AddressSpace *as, MemoryRegionIoeventfd *fd) +{ + int r; + + r = kvm_set_ioeventfd_pio_word(fd->fd, fd->addr.start, fd->data, false); + if (r < 0) { + abort(); + } +} + +static const AddressSpaceOps address_space_ops_io = { + .range_add = as_io_range_add, + .range_del = as_io_range_del, + .ioeventfd_add = as_io_ioeventfd_add, + .ioeventfd_del = as_io_ioeventfd_del, +}; + +static AddressSpace address_space_io = { + .ops = &address_space_ops_io, +}; + +/* Render a memory region into the global view. Ranges in @view obscure + * ranges in @mr. + */ +static void render_memory_region(FlatView *view, + MemoryRegion *mr, + target_phys_addr_t base, + AddrRange clip) +{ + MemoryRegion *subregion; + unsigned i; + target_phys_addr_t offset_in_region; + uint64_t remain; + uint64_t now; + FlatRange fr; + AddrRange tmp; + + base += mr->addr; + + tmp = addrrange_make(base, mr->size); + + if (!addrrange_intersects(tmp, clip)) { + return; + } + + clip = addrrange_intersection(tmp, clip); + + if (mr->alias) { + base -= mr->alias->addr; + base -= mr->alias_offset; + render_memory_region(view, mr->alias, base, clip); + return; + } + + /* Render subregions in priority order. */ + QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) { + render_memory_region(view, subregion, base, clip); + } + + if (!mr->terminates) { + return; + } + + offset_in_region = clip.start - base; + base = clip.start; + remain = clip.size; + + /* Render the region itself into any gaps left by the current view. */ + for (i = 0; i < view->nr && remain; ++i) { + if (base >= addrrange_end(view->ranges[i].addr)) { + continue; + } + if (base < view->ranges[i].addr.start) { + now = MIN(remain, view->ranges[i].addr.start - base); + fr.mr = mr; + fr.offset_in_region = offset_in_region; + fr.addr = addrrange_make(base, now); + fr.dirty_log_mask = mr->dirty_log_mask; + flatview_insert(view, i, &fr); + ++i; + base += now; + offset_in_region += now; + remain -= now; + } + if (base == view->ranges[i].addr.start) { + now = MIN(remain, view->ranges[i].addr.size); + base += now; + offset_in_region += now; + remain -= now; + } + } + if (remain) { + fr.mr = mr; + fr.offset_in_region = offset_in_region; + fr.addr = addrrange_make(base, remain); + fr.dirty_log_mask = mr->dirty_log_mask; + flatview_insert(view, i, &fr); + } +} + +/* Render a memory topology into a list of disjoint absolute ranges. */ +static FlatView generate_memory_topology(MemoryRegion *mr) +{ + FlatView view; + + flatview_init(&view); + + render_memory_region(&view, mr, 0, addrrange_make(0, UINT64_MAX)); + flatview_simplify(&view); + + return view; +} + +static void address_space_add_del_ioeventfds(AddressSpace *as, + MemoryRegionIoeventfd *fds_new, + unsigned fds_new_nb, + MemoryRegionIoeventfd *fds_old, + unsigned fds_old_nb) +{ + unsigned iold, inew; + + /* Generate a symmetric difference of the old and new fd sets, adding + * and deleting as necessary. + */ + + iold = inew = 0; + while (iold < fds_old_nb || inew < fds_new_nb) { + if (iold < fds_old_nb + && (inew == fds_new_nb + || memory_region_ioeventfd_before(fds_old[iold], + fds_new[inew]))) { + as->ops->ioeventfd_del(as, &fds_old[iold]); + ++iold; + } else if (inew < fds_new_nb + && (iold == fds_old_nb + || memory_region_ioeventfd_before(fds_new[inew], + fds_old[iold]))) { + as->ops->ioeventfd_add(as, &fds_new[inew]); + ++inew; + } else { + ++iold; + ++inew; + } + } +} + +static void address_space_update_ioeventfds(AddressSpace *as) +{ + FlatRange *fr; + unsigned ioeventfd_nb = 0; + MemoryRegionIoeventfd *ioeventfds = NULL; + AddrRange tmp; + unsigned i; + + FOR_EACH_FLAT_RANGE(fr, &as->current_map) { + for (i = 0; i < fr->mr->ioeventfd_nb; ++i) { + tmp = addrrange_shift(fr->mr->ioeventfds[i].addr, + fr->addr.start - fr->offset_in_region); + if (addrrange_intersects(fr->addr, tmp)) { + ++ioeventfd_nb; + ioeventfds = qemu_realloc(ioeventfds, + ioeventfd_nb * sizeof(*ioeventfds)); + ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i]; + ioeventfds[ioeventfd_nb-1].addr = tmp; + } + } + } + + address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb, + as->ioeventfds, as->ioeventfd_nb); + + qemu_free(as->ioeventfds); + as->ioeventfds = ioeventfds; + as->ioeventfd_nb = ioeventfd_nb; +} + +static void address_space_update_topology_pass(AddressSpace *as, + FlatView old_view, + FlatView new_view, + bool adding) +{ + unsigned iold, inew; + FlatRange *frold, *frnew; + + /* Generate a symmetric difference of the old and new memory maps. + * Kill ranges in the old map, and instantiate ranges in the new map. + */ + iold = inew = 0; + while (iold < old_view.nr || inew < new_view.nr) { + if (iold < old_view.nr) { + frold = &old_view.ranges[iold]; + } else { + frold = NULL; + } + if (inew < new_view.nr) { + frnew = &new_view.ranges[inew]; + } else { + frnew = NULL; + } + + if (frold + && (!frnew + || frold->addr.start < frnew->addr.start + || (frold->addr.start == frnew->addr.start + && !flatrange_equal(frold, frnew)))) { + /* In old, but (not in new, or in new but attributes changed). */ + + if (!adding) { + as->ops->range_del(as, frold); + } + + ++iold; + } else if (frold && frnew && flatrange_equal(frold, frnew)) { + /* In both (logging may have changed) */ + + if (adding) { + if (frold->dirty_log_mask && !frnew->dirty_log_mask) { + as->ops->log_stop(as, frnew); + } else if (frnew->dirty_log_mask && !frold->dirty_log_mask) { + as->ops->log_start(as, frnew); + } + } + + ++iold; + ++inew; + } else { + /* In new */ + + if (adding) { + as->ops->range_add(as, frnew); + } + + ++inew; + } + } +} + + +static void address_space_update_topology(AddressSpace *as) +{ + FlatView old_view = as->current_map; + FlatView new_view = generate_memory_topology(as->root); + + address_space_update_topology_pass(as, old_view, new_view, false); + address_space_update_topology_pass(as, old_view, new_view, true); + + as->current_map = new_view; + flatview_destroy(&old_view); + address_space_update_ioeventfds(as); +} + +static void memory_region_update_topology(void) +{ + if (memory_region_transaction_depth) { + return; + } + + if (address_space_memory.root) { + address_space_update_topology(&address_space_memory); + } + if (address_space_io.root) { + address_space_update_topology(&address_space_io); + } +} + +void memory_region_transaction_begin(void) +{ + ++memory_region_transaction_depth; +} + +void memory_region_transaction_commit(void) +{ + assert(memory_region_transaction_depth); + --memory_region_transaction_depth; + memory_region_update_topology(); +} + +void memory_region_init(MemoryRegion *mr, + const char *name, + uint64_t size) +{ + mr->ops = NULL; + mr->parent = NULL; + mr->size = size; + mr->addr = 0; + mr->offset = 0; + mr->terminates = false; + mr->priority = 0; + mr->may_overlap = false; + mr->alias = NULL; + QTAILQ_INIT(&mr->subregions); + memset(&mr->subregions_link, 0, sizeof mr->subregions_link); + QTAILQ_INIT(&mr->coalesced); + mr->name = qemu_strdup(name); + mr->dirty_log_mask = 0; + mr->ioeventfd_nb = 0; + mr->ioeventfds = NULL; +} + +static bool memory_region_access_valid(MemoryRegion *mr, + target_phys_addr_t addr, + unsigned size) +{ + if (!mr->ops->valid.unaligned && (addr & (size - 1))) { + return false; + } + + /* Treat zero as compatibility all valid */ + if (!mr->ops->valid.max_access_size) { + return true; + } + + if (size > mr->ops->valid.max_access_size + || size < mr->ops->valid.min_access_size) { + return false; + } + return true; +} + +static uint32_t memory_region_read_thunk_n(void *_mr, + target_phys_addr_t addr, + unsigned size) +{ + MemoryRegion *mr = _mr; + unsigned access_size, access_size_min, access_size_max; + uint64_t access_mask; + uint32_t data = 0, tmp; + unsigned i; + + if (!memory_region_access_valid(mr, addr, size)) { + return -1U; /* FIXME: better signalling */ + } + + if (!mr->ops->read) { + return mr->ops->old_mmio.read[bitops_ffsl(size)](mr->opaque, addr); + } + + /* FIXME: support unaligned access */ + + access_size_min = mr->ops->impl.min_access_size; + if (!access_size_min) { + access_size_min = 1; + } + access_size_max = mr->ops->impl.max_access_size; + if (!access_size_max) { + access_size_max = 4; + } + access_size = MAX(MIN(size, access_size_max), access_size_min); + access_mask = -1ULL >> (64 - access_size * 8); + addr += mr->offset; + for (i = 0; i < size; i += access_size) { + /* FIXME: big-endian support */ + tmp = mr->ops->read(mr->opaque, addr + i, access_size); + data |= (tmp & access_mask) << (i * 8); + } + + return data; +} + +static void memory_region_write_thunk_n(void *_mr, + target_phys_addr_t addr, + unsigned size, + uint64_t data) +{ + MemoryRegion *mr = _mr; + unsigned access_size, access_size_min, access_size_max; + uint64_t access_mask; + unsigned i; + + if (!memory_region_access_valid(mr, addr, size)) { + return; /* FIXME: better signalling */ + } + + if (!mr->ops->write) { + mr->ops->old_mmio.write[bitops_ffsl(size)](mr->opaque, addr, data); + return; + } + + /* FIXME: support unaligned access */ + + access_size_min = mr->ops->impl.min_access_size; + if (!access_size_min) { + access_size_min = 1; + } + access_size_max = mr->ops->impl.max_access_size; + if (!access_size_max) { + access_size_max = 4; + } + access_size = MAX(MIN(size, access_size_max), access_size_min); + access_mask = -1ULL >> (64 - access_size * 8); + addr += mr->offset; + for (i = 0; i < size; i += access_size) { + /* FIXME: big-endian support */ + mr->ops->write(mr->opaque, addr + i, (data >> (i * 8)) & access_mask, + access_size); + } +} + +static uint32_t memory_region_read_thunk_b(void *mr, target_phys_addr_t addr) +{ + return memory_region_read_thunk_n(mr, addr, 1); +} + +static uint32_t memory_region_read_thunk_w(void *mr, target_phys_addr_t addr) +{ + return memory_region_read_thunk_n(mr, addr, 2); +} + +static uint32_t memory_region_read_thunk_l(void *mr, target_phys_addr_t addr) +{ + return memory_region_read_thunk_n(mr, addr, 4); +} + +static void memory_region_write_thunk_b(void *mr, target_phys_addr_t addr, + uint32_t data) +{ + memory_region_write_thunk_n(mr, addr, 1, data); +} + +static void memory_region_write_thunk_w(void *mr, target_phys_addr_t addr, + uint32_t data) +{ + memory_region_write_thunk_n(mr, addr, 2, data); +} + +static void memory_region_write_thunk_l(void *mr, target_phys_addr_t addr, + uint32_t data) +{ + memory_region_write_thunk_n(mr, addr, 4, data); +} + +static CPUReadMemoryFunc * const memory_region_read_thunk[] = { + memory_region_read_thunk_b, + memory_region_read_thunk_w, + memory_region_read_thunk_l, +}; + +static CPUWriteMemoryFunc * const memory_region_write_thunk[] = { + memory_region_write_thunk_b, + memory_region_write_thunk_w, + memory_region_write_thunk_l, +}; + +static void memory_region_prepare_ram_addr(MemoryRegion *mr) +{ + if (mr->backend_registered) { + return; + } + + mr->ram_addr = cpu_register_io_memory(memory_region_read_thunk, + memory_region_write_thunk, + mr, + mr->ops->endianness); + mr->backend_registered = true; +} + +void memory_region_init_io(MemoryRegion *mr, + const MemoryRegionOps *ops, + void *opaque, + const char *name, + uint64_t size) +{ + memory_region_init(mr, name, size); + mr->ops = ops; + mr->opaque = opaque; + mr->terminates = true; + mr->backend_registered = false; +} + +void memory_region_init_ram(MemoryRegion *mr, + DeviceState *dev, + const char *name, + uint64_t size) +{ + memory_region_init(mr, name, size); + mr->terminates = true; + mr->ram_addr = qemu_ram_alloc(dev, name, size); + mr->backend_registered = true; +} + +void memory_region_init_ram_ptr(MemoryRegion *mr, + DeviceState *dev, + const char *name, + uint64_t size, + void *ptr) +{ + memory_region_init(mr, name, size); + mr->terminates = true; + mr->ram_addr = qemu_ram_alloc_from_ptr(dev, name, size, ptr); + mr->backend_registered = true; +} + +void memory_region_init_alias(MemoryRegion *mr, + const char *name, + MemoryRegion *orig, + target_phys_addr_t offset, + uint64_t size) +{ + memory_region_init(mr, name, size); + mr->alias = orig; + mr->alias_offset = offset; +} + +void memory_region_destroy(MemoryRegion *mr) +{ + assert(QTAILQ_EMPTY(&mr->subregions)); + memory_region_clear_coalescing(mr); + qemu_free((char *)mr->name); + qemu_free(mr->ioeventfds); +} + +uint64_t memory_region_size(MemoryRegion *mr) +{ + return mr->size; +} + +void memory_region_set_offset(MemoryRegion *mr, target_phys_addr_t offset) +{ + mr->offset = offset; +} + +void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client) +{ + uint8_t mask = 1 << client; + + mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask); + memory_region_update_topology(); +} + +bool memory_region_get_dirty(MemoryRegion *mr, target_phys_addr_t addr, + unsigned client) +{ + assert(mr->terminates); + return cpu_physical_memory_get_dirty(mr->ram_addr + addr, 1 << client); +} + +void memory_region_set_dirty(MemoryRegion *mr, target_phys_addr_t addr) +{ + assert(mr->terminates); + return cpu_physical_memory_set_dirty(mr->ram_addr + addr); +} + +void memory_region_sync_dirty_bitmap(MemoryRegion *mr) +{ + FlatRange *fr; + + FOR_EACH_FLAT_RANGE(fr, &address_space_memory.current_map) { + if (fr->mr == mr) { + cpu_physical_sync_dirty_bitmap(fr->addr.start, + fr->addr.start + fr->addr.size); + } + } +} + +void memory_region_set_readonly(MemoryRegion *mr, bool readonly) +{ + /* FIXME */ +} + +void memory_region_reset_dirty(MemoryRegion *mr, target_phys_addr_t addr, + target_phys_addr_t size, unsigned client) +{ + assert(mr->terminates); + cpu_physical_memory_reset_dirty(mr->ram_addr + addr, + mr->ram_addr + addr + size, + 1 << client); +} + +void *memory_region_get_ram_ptr(MemoryRegion *mr) +{ + if (mr->alias) { + return memory_region_get_ram_ptr(mr->alias) + mr->alias_offset; + } + + assert(mr->terminates); + + return qemu_get_ram_ptr(mr->ram_addr); +} + +static void memory_region_update_coalesced_range(MemoryRegion *mr) +{ + FlatRange *fr; + CoalescedMemoryRange *cmr; + AddrRange tmp; + + FOR_EACH_FLAT_RANGE(fr, &address_space_memory.current_map) { + if (fr->mr == mr) { + qemu_unregister_coalesced_mmio(fr->addr.start, fr->addr.size); + QTAILQ_FOREACH(cmr, &mr->coalesced, link) { + tmp = addrrange_shift(cmr->addr, + fr->addr.start - fr->offset_in_region); + if (!addrrange_intersects(tmp, fr->addr)) { + continue; + } + tmp = addrrange_intersection(tmp, fr->addr); + qemu_register_coalesced_mmio(tmp.start, tmp.size); + } + } + } +} + +void memory_region_set_coalescing(MemoryRegion *mr) +{ + memory_region_clear_coalescing(mr); + memory_region_add_coalescing(mr, 0, mr->size); +} + +void memory_region_add_coalescing(MemoryRegion *mr, + target_phys_addr_t offset, + uint64_t size) +{ + CoalescedMemoryRange *cmr = qemu_malloc(sizeof(*cmr)); + + cmr->addr = addrrange_make(offset, size); + QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link); + memory_region_update_coalesced_range(mr); +} + +void memory_region_clear_coalescing(MemoryRegion *mr) +{ + CoalescedMemoryRange *cmr; + + while (!QTAILQ_EMPTY(&mr->coalesced)) { + cmr = QTAILQ_FIRST(&mr->coalesced); + QTAILQ_REMOVE(&mr->coalesced, cmr, link); + qemu_free(cmr); + } + memory_region_update_coalesced_range(mr); +} + +void memory_region_add_eventfd(MemoryRegion *mr, + target_phys_addr_t addr, + unsigned size, + bool match_data, + uint64_t data, + int fd) +{ + MemoryRegionIoeventfd mrfd = { + .addr.start = addr, + .addr.size = size, + .match_data = match_data, + .data = data, + .fd = fd, + }; + unsigned i; + + for (i = 0; i < mr->ioeventfd_nb; ++i) { + if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) { + break; + } + } + ++mr->ioeventfd_nb; + mr->ioeventfds = qemu_realloc(mr->ioeventfds, + sizeof(*mr->ioeventfds) * mr->ioeventfd_nb); + memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i], + sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i)); + mr->ioeventfds[i] = mrfd; + memory_region_update_topology(); +} + +void memory_region_del_eventfd(MemoryRegion *mr, + target_phys_addr_t addr, + unsigned size, + bool match_data, + uint64_t data, + int fd) +{ + MemoryRegionIoeventfd mrfd = { + .addr.start = addr, + .addr.size = size, + .match_data = match_data, + .data = data, + .fd = fd, + }; + unsigned i; + + for (i = 0; i < mr->ioeventfd_nb; ++i) { + if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) { + break; + } + } + assert(i != mr->ioeventfd_nb); + memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1], + sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1))); + --mr->ioeventfd_nb; + mr->ioeventfds = qemu_realloc(mr->ioeventfds, + sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1); + memory_region_update_topology(); +} + +static void memory_region_add_subregion_common(MemoryRegion *mr, + target_phys_addr_t offset, + MemoryRegion *subregion) +{ + MemoryRegion *other; + + assert(!subregion->parent); + subregion->parent = mr; + subregion->addr = offset; + QTAILQ_FOREACH(other, &mr->subregions, subregions_link) { + if (subregion->may_overlap || other->may_overlap) { + continue; + } + if (offset >= other->offset + other->size + || offset + subregion->size <= other->offset) { + continue; + } + printf("warning: subregion collision %llx/%llx vs %llx/%llx\n", + (unsigned long long)offset, + (unsigned long long)subregion->size, + (unsigned long long)other->offset, + (unsigned long long)other->size); + } + QTAILQ_FOREACH(other, &mr->subregions, subregions_link) { + if (subregion->priority >= other->priority) { + QTAILQ_INSERT_BEFORE(other, subregion, subregions_link); + goto done; + } + } + QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link); +done: + memory_region_update_topology(); +} + + +void memory_region_add_subregion(MemoryRegion *mr, + target_phys_addr_t offset, + MemoryRegion *subregion) +{ + subregion->may_overlap = false; + subregion->priority = 0; + memory_region_add_subregion_common(mr, offset, subregion); +} + +void memory_region_add_subregion_overlap(MemoryRegion *mr, + target_phys_addr_t offset, + MemoryRegion *subregion, + unsigned priority) +{ + subregion->may_overlap = true; + subregion->priority = priority; + memory_region_add_subregion_common(mr, offset, subregion); +} + +void memory_region_del_subregion(MemoryRegion *mr, + MemoryRegion *subregion) +{ + assert(subregion->parent == mr); + subregion->parent = NULL; + QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link); + memory_region_update_topology(); +} + +void set_system_memory_map(MemoryRegion *mr) +{ + address_space_memory.root = mr; + memory_region_update_topology(); +} + +void set_system_io_map(MemoryRegion *mr) +{ + address_space_io.root = mr; + memory_region_update_topology(); +} diff --git a/memory.h b/memory.h new file mode 100644 index 0000000000..4e518b2a1b --- /dev/null +++ b/memory.h @@ -0,0 +1,469 @@ +/* + * Physical memory management API + * + * Copyright 2011 Red Hat, Inc. and/or its affiliates + * + * Authors: + * Avi Kivity <avi@redhat.com> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + */ + +#ifndef MEMORY_H +#define MEMORY_H + +#ifndef CONFIG_USER_ONLY + +#include <stdint.h> +#include <stdbool.h> +#include "qemu-common.h" +#include "cpu-common.h" +#include "targphys.h" +#include "qemu-queue.h" +#include "iorange.h" +#include "ioport.h" + +typedef struct MemoryRegionOps MemoryRegionOps; +typedef struct MemoryRegion MemoryRegion; +typedef struct MemoryRegionPortio MemoryRegionPortio; +typedef struct MemoryRegionMmio MemoryRegionMmio; + +/* Must match *_DIRTY_FLAGS in cpu-all.h. To be replaced with dynamic + * registration. + */ +#define DIRTY_MEMORY_VGA 0 +#define DIRTY_MEMORY_CODE 1 +#define DIRTY_MEMORY_MIGRATION 3 + +struct MemoryRegionMmio { + CPUReadMemoryFunc *read[3]; + CPUWriteMemoryFunc *write[3]; +}; + +/* + * Memory region callbacks + */ +struct MemoryRegionOps { + /* Read from the memory region. @addr is relative to @mr; @size is + * in bytes. */ + uint64_t (*read)(void *opaque, + target_phys_addr_t addr, + unsigned size); + /* Write to the memory region. @addr is relative to @mr; @size is + * in bytes. */ + void (*write)(void *opaque, + target_phys_addr_t addr, + uint64_t data, + unsigned size); + + enum device_endian endianness; + /* Guest-visible constraints: */ + struct { + /* If nonzero, specify bounds on access sizes beyond which a machine + * check is thrown. + */ + unsigned min_access_size; + unsigned max_access_size; + /* If true, unaligned accesses are supported. Otherwise unaligned + * accesses throw machine checks. + */ + bool unaligned; + } valid; + /* Internal implementation constraints: */ + struct { + /* If nonzero, specifies the minimum size implemented. Smaller sizes + * will be rounded upwards and a partial result will be returned. + */ + unsigned min_access_size; + /* If nonzero, specifies the maximum size implemented. Larger sizes + * will be done as a series of accesses with smaller sizes. + */ + unsigned max_access_size; + /* If true, unaligned accesses are supported. Otherwise all accesses + * are converted to (possibly multiple) naturally aligned accesses. + */ + bool unaligned; + } impl; + + /* If .read and .write are not present, old_portio may be used for + * backwards compatibility with old portio registration + */ + const MemoryRegionPortio *old_portio; + /* If .read and .write are not present, old_mmio may be used for + * backwards compatibility with old mmio registration + */ + const MemoryRegionMmio old_mmio; +}; + +typedef struct CoalescedMemoryRange CoalescedMemoryRange; +typedef struct MemoryRegionIoeventfd MemoryRegionIoeventfd; + +struct MemoryRegion { + /* All fields are private - violators will be prosecuted */ + const MemoryRegionOps *ops; + void *opaque; + MemoryRegion *parent; + uint64_t size; + target_phys_addr_t addr; + target_phys_addr_t offset; + bool backend_registered; + ram_addr_t ram_addr; + IORange iorange; + bool terminates; + MemoryRegion *alias; + target_phys_addr_t alias_offset; + unsigned priority; + bool may_overlap; + QTAILQ_HEAD(subregions, MemoryRegion) subregions; + QTAILQ_ENTRY(MemoryRegion) subregions_link; + QTAILQ_HEAD(coalesced_ranges, CoalescedMemoryRange) coalesced; + const char *name; + uint8_t dirty_log_mask; + unsigned ioeventfd_nb; + MemoryRegionIoeventfd *ioeventfds; +}; + +struct MemoryRegionPortio { + uint32_t offset; + uint32_t len; + unsigned size; + IOPortReadFunc *read; + IOPortWriteFunc *write; +}; + +#define PORTIO_END { } + +/** + * memory_region_init: Initialize a memory region + * + * The region typically acts as a container for other memory regions. Us + * memory_region_add_subregion() to add subregions. + * + * @mr: the #MemoryRegion to be initialized + * @name: used for debugging; not visible to the user or ABI + * @size: size of the region; any subregions beyond this size will be clipped + */ +void memory_region_init(MemoryRegion *mr, + const char *name, + uint64_t size); +/** + * memory_region_init_io: Initialize an I/O memory region. + * + * Accesses into the region will be cause the callbacks in @ops to be called. + * if @size is nonzero, subregions will be clipped to @size. + * + * @mr: the #MemoryRegion to be initialized. + * @ops: a structure containing read and write callbacks to be used when + * I/O is performed on the region. + * @opaque: passed to to the read and write callbacks of the @ops structure. + * @name: used for debugging; not visible to the user or ABI + * @size: size of the region. + */ +void memory_region_init_io(MemoryRegion *mr, + const MemoryRegionOps *ops, + void *opaque, + const char *name, + uint64_t size); + +/** + * memory_region_init_ram: Initialize RAM memory region. Accesses into the + * region will be modify memory directly. + * + * @mr: the #MemoryRegion to be initialized. + * @dev: a device associated with the region; may be %NULL. + * @name: the name of the region; the pair (@dev, @name) must be globally + * unique. The name is part of the save/restore ABI and so cannot be + * changed. + * @size: size of the region. + */ +void memory_region_init_ram(MemoryRegion *mr, + DeviceState *dev, /* FIXME: layering violation */ + const char *name, + uint64_t size); + +/** + * memory_region_init_ram: Initialize RAM memory region from a user-provided. + * pointer. Accesses into the region will be modify + * memory directly. + * + * @mr: the #MemoryRegion to be initialized. + * @dev: a device associated with the region; may be %NULL. + * @name: the name of the region; the pair (@dev, @name) must be globally + * unique. The name is part of the save/restore ABI and so cannot be + * changed. + * @size: size of the region. + * @ptr: memory to be mapped; must contain at least @size bytes. + */ +void memory_region_init_ram_ptr(MemoryRegion *mr, + DeviceState *dev, /* FIXME: layering violation */ + const char *name, + uint64_t size, + void *ptr); + +/** + * memory_region_init_alias: Initialize a memory region that aliases all or a + * part of another memory region. + * + * @mr: the #MemoryRegion to be initialized. + * @name: used for debugging; not visible to the user or ABI + * @orig: the region to be referenced; @mr will be equivalent to + * @orig between @offset and @offset + @size - 1. + * @offset: start of the section in @orig to be referenced. + * @size: size of the region. + */ +void memory_region_init_alias(MemoryRegion *mr, + const char *name, + MemoryRegion *orig, + target_phys_addr_t offset, + uint64_t size); +/** + * memory_region_destroy: Destroy a memory region and relaim all resources. + * + * @mr: the region to be destroyed. May not currently be a subregion + * (see memory_region_add_subregion()) or referenced in an alias + * (see memory_region_init_alias()). + */ +void memory_region_destroy(MemoryRegion *mr); + +/** + * memory_region_size: get a memory region's size. + * + * @mr: the memory region being queried. + */ +uint64_t memory_region_size(MemoryRegion *mr); + +/** + * memory_region_get_ram_ptr: Get a pointer into a RAM memory region. + * + * Returns a host pointer to a RAM memory region (created with + * memory_region_init_ram() or memory_region_init_ram_ptr()). Use with + * care. + * + * @mr: the memory region being queried. + */ +void *memory_region_get_ram_ptr(MemoryRegion *mr); + +/** + * memory_region_set_offset: Sets an offset to be added to MemoryRegionOps + * callbacks. + * + * This function is deprecated and should not be used in new code. + */ +void memory_region_set_offset(MemoryRegion *mr, target_phys_addr_t offset); + +/** + * memory_region_set_log: Turn dirty logging on or off for a region. + * + * Turns dirty logging on or off for a specified client (display, migration). + * Only meaningful for RAM regions. + * + * @mr: the memory region being updated. + * @log: whether dirty logging is to be enabled or disabled. + * @client: the user of the logging information; %DIRTY_MEMORY_MIGRATION or + * %DIRTY_MEMORY_VGA. + */ +void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client); + +/** + * memory_region_get_dirty: Check whether a page is dirty for a specified + * client. + * + * Checks whether a page has been written to since the last + * call to memory_region_reset_dirty() with the same @client. Dirty logging + * must be enabled. + * + * @mr: the memory region being queried. + * @addr: the address (relative to the start of the region) being queried. + * @client: the user of the logging information; %DIRTY_MEMORY_MIGRATION or + * %DIRTY_MEMORY_VGA. + */ +bool memory_region_get_dirty(MemoryRegion *mr, target_phys_addr_t addr, + unsigned client); + +/** + * memory_region_set_dirty: Mark a page as dirty in a memory region. + * + * Marks a page as dirty, after it has been dirtied outside guest code. + * + * @mr: the memory region being queried. + * @addr: the address (relative to the start of the region) being dirtied. + */ +void memory_region_set_dirty(MemoryRegion *mr, target_phys_addr_t addr); + +/** + * memory_region_sync_dirty_bitmap: Synchronize a region's dirty bitmap with + * any external TLBs (e.g. kvm) + * + * Flushes dirty information from accelerators such as kvm and vhost-net + * and makes it available to users of the memory API. + * + * @mr: the region being flushed. + */ +void memory_region_sync_dirty_bitmap(MemoryRegion *mr); + +/** + * memory_region_reset_dirty: Mark a range of pages as clean, for a specified + * client. + * + * Marks a range of pages as no longer dirty. + * + * @mr: the region being updated. + * @addr: the start of the subrange being cleaned. + * @size: the size of the subrange being cleaned. + * @client: the user of the logging information; %DIRTY_MEMORY_MIGRATION or + * %DIRTY_MEMORY_VGA. + */ +void memory_region_reset_dirty(MemoryRegion *mr, target_phys_addr_t addr, + target_phys_addr_t size, unsigned client); + +/** + * memory_region_set_readonly: Turn a memory region read-only (or read-write) + * + * Allows a memory region to be marked as read-only (turning it into a ROM). + * only useful on RAM regions. + * + * @mr: the region being updated. + * @readonly: whether rhe region is to be ROM or RAM. + */ +void memory_region_set_readonly(MemoryRegion *mr, bool readonly); + +/** + * memory_region_set_coalescing: Enable memory coalescing for the region. + * + * Enabled writes to a region to be queued for later processing. MMIO ->write + * callbacks may be delayed until a non-coalesced MMIO is issued. + * Only useful for IO regions. Roughly similar to write-combining hardware. + * + * @mr: the memory region to be write coalesced + */ +void memory_region_set_coalescing(MemoryRegion *mr); + +/** + * memory_region_add_coalescing: Enable memory coalescing for a sub-range of + * a region. + * + * Like memory_region_set_coalescing(), but works on a sub-range of a region. + * Multiple calls can be issued coalesced disjoint ranges. + * + * @mr: the memory region to be updated. + * @offset: the start of the range within the region to be coalesced. + * @size: the size of the subrange to be coalesced. + */ +void memory_region_add_coalescing(MemoryRegion *mr, + target_phys_addr_t offset, + uint64_t size); + +/** + * memory_region_clear_coalescing: Disable MMIO coalescing for the region. + * + * Disables any coalescing caused by memory_region_set_coalescing() or + * memory_region_add_coalescing(). Roughly equivalent to uncacheble memory + * hardware. + * + * @mr: the memory region to be updated. + */ +void memory_region_clear_coalescing(MemoryRegion *mr); + +/** + * memory_region_add_eventfd: Request an eventfd to be triggered when a word + * is written to a location. + * + * Marks a word in an IO region (initialized with memory_region_init_io()) + * as a trigger for an eventfd event. The I/O callback will not be called. + * The caller must be prepared to handle failure (hat is, take the required + * action if the callback _is_ called). + * + * @mr: the memory region being updated. + * @addr: the address within @mr that is to be monitored + * @size: the size of the access to trigger the eventfd + * @match_data: whether to match against @data, instead of just @addr + * @data: the data to match against the guest write + * @fd: the eventfd to be triggered when @addr, @size, and @data all match. + **/ +void memory_region_add_eventfd(MemoryRegion *mr, + target_phys_addr_t addr, + unsigned size, + bool match_data, + uint64_t data, + int fd); + +/** + * memory_region_del_eventfd: Cancel and eventfd. + * + * Cancels an eventfd trigger request by a previous memory_region_add_eventfd() + * call. + * + * @mr: the memory region being updated. + * @addr: the address within @mr that is to be monitored + * @size: the size of the access to trigger the eventfd + * @match_data: whether to match against @data, instead of just @addr + * @data: the data to match against the guest write + * @fd: the eventfd to be triggered when @addr, @size, and @data all match. + */ +void memory_region_del_eventfd(MemoryRegion *mr, + target_phys_addr_t addr, + unsigned size, + bool match_data, + uint64_t data, + int fd); +/** + * memory_region_add_subregion: Add a sub-region to a container. + * + * Adds a sub-region at @offset. The sub-region may not overlap with other + * subregions (except for those explicitly marked as overlapping). A region + * may only be added once as a subregion (unless removed with + * memory_region_del_subregion()); use memory_region_init_alias() if you + * want a region to be a subregion in multiple locations. + * + * @mr: the region to contain the new subregion; must be a container + * initialized with memory_region_init(). + * @offset: the offset relative to @mr where @subregion is added. + * @subregion: the subregion to be added. + */ +void memory_region_add_subregion(MemoryRegion *mr, + target_phys_addr_t offset, + MemoryRegion *subregion); +/** + * memory_region_add_subregion: Add a sub-region to a container, with overlap. + * + * Adds a sub-region at @offset. The sub-region may overlap with other + * subregions. Conflicts are resolved by having a higher @priority hide a + * lower @priority. Subregions without priority are taken as @priority 0. + * A region may only be added once as a subregion (unless removed with + * memory_region_del_subregion()); use memory_region_init_alias() if you + * want a region to be a subregion in multiple locations. + * + * @mr: the region to contain the new subregion; must be a container + * initialized with memory_region_init(). + * @offset: the offset relative to @mr where @subregion is added. + * @subregion: the subregion to be added. + * @priority: used for resolving overlaps; highest priority wins. + */ +void memory_region_add_subregion_overlap(MemoryRegion *mr, + target_phys_addr_t offset, + MemoryRegion *subregion, + unsigned priority); +/** + * memory_region_del_subregion: Remove a subregion. + * + * Removes a subregion from its container. + * + * @mr: the container to be updated. + * @subregion: the region being removed; must be a current subregion of @mr. + */ +void memory_region_del_subregion(MemoryRegion *mr, + MemoryRegion *subregion); + +/* Start a transaction; changes will be accumulated and made visible only + * when the transaction ends. + */ +void memory_region_transaction_begin(void); +/* Commit a transaction and make changes visible to the guest. + */ +void memory_region_transaction_commit(void); + +#endif + +#endif @@ -1200,10 +1200,12 @@ static int add_graphics_client(Monitor *mon, const QDict *qdict, QObject **ret_d } qerror_report(QERR_ADD_CLIENT_FAILED); return -1; +#ifdef CONFIG_VNC } else if (strcmp(protocol, "vnc") == 0) { int fd = monitor_get_fd(mon, fdname); vnc_display_add_client(NULL, fd, skipauth); return 0; +#endif } else if ((s = qemu_chr_find(protocol)) != NULL) { int fd = monitor_get_fd(mon, fdname); if (qemu_chr_add_client(s, fd) < 0) { diff --git a/oslib-posix.c b/oslib-posix.c index 3a18e865f3..196099cc77 100644 --- a/oslib-posix.c +++ b/oslib-posix.c @@ -79,7 +79,10 @@ void *qemu_memalign(size_t alignment, size_t size) /* alloc shared memory pages */ void *qemu_vmalloc(size_t size) { - return qemu_memalign(getpagesize(), size); + void *ptr; + ptr = qemu_memalign(getpagesize(), size); + trace_qemu_vmalloc(size, ptr); + return ptr; } void qemu_vfree(void *ptr) diff --git a/qemu-common.h b/qemu-common.h index 391fadda56..1e3c66511e 100644 --- a/qemu-common.h +++ b/qemu-common.h @@ -5,6 +5,10 @@ #include "compiler.h" #include "config-host.h" +#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__) +#define WORDS_ALIGNED +#endif + #define TFR(expr) do { if ((expr) != -1) break; } while (errno == EINTR) typedef struct QEMUTimer QEMUTimer; diff --git a/qemu-config.c b/qemu-config.c index b2ec40bd66..1eb6b9a709 100644 --- a/qemu-config.c +++ b/qemu-config.c @@ -480,6 +480,32 @@ static QemuOptsList qemu_machine_opts = { }, }; +QemuOptsList qemu_boot_opts = { + .name = "boot-opts", + .head = QTAILQ_HEAD_INITIALIZER(qemu_boot_opts.head), + .desc = { + /* the three names below are not used now */ + { + .name = "order", + .type = QEMU_OPT_STRING, + }, { + .name = "once", + .type = QEMU_OPT_STRING, + }, { + .name = "menu", + .type = QEMU_OPT_STRING, + /* following are really used */ + }, { + .name = "splash", + .type = QEMU_OPT_STRING, + }, { + .name = "splash-time", + .type = QEMU_OPT_STRING, + }, + { /*End of list */ } + }, +}; + static QemuOptsList *vm_config_groups[32] = { &qemu_drive_opts, &qemu_chardev_opts, @@ -495,6 +521,7 @@ static QemuOptsList *vm_config_groups[32] = { #endif &qemu_option_rom_opts, &qemu_machine_opts, + &qemu_boot_opts, NULL, }; diff --git a/qemu-options.hx b/qemu-options.hx index 1d57f64888..c77f868d40 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -303,10 +303,13 @@ ETEXI DEF("boot", HAS_ARG, QEMU_OPTION_boot, "-boot [order=drives][,once=drives][,menu=on|off]\n" - " 'drives': floppy (a), hard disk (c), CD-ROM (d), network (n)\n", + " [,splash=sp_name][,splash-time=sp_time]\n" + " 'drives': floppy (a), hard disk (c), CD-ROM (d), network (n)\n" + " 'sp_name': the file's name that would be passed to bios as logo picture, if menu=on\n" + " 'sp_time': the period that splash picture last if menu=on, unit is ms\n", QEMU_ARCH_ALL) STEXI -@item -boot [order=@var{drives}][,once=@var{drives}][,menu=on|off] +@item -boot [order=@var{drives}][,once=@var{drives}][,menu=on|off][,splash=@var{sp_name}][,splash-time=@var{sp_time}] @findex -boot Specify boot order @var{drives} as a string of drive letters. Valid drive letters depend on the target achitecture. The x86 PC uses: a, b @@ -318,11 +321,20 @@ particular boot order only on the first startup, specify it via Interactive boot menus/prompts can be enabled via @option{menu=on} as far as firmware/BIOS supports them. The default is non-interactive boot. +A splash picture could be passed to bios, enabling user to show it as logo, +when option splash=@var{sp_name} is given and menu=on, If firmware/BIOS +supports them. Currently Seabios for X86 system support it. +limitation: The splash file could be a jpeg file or a BMP file in 24 BPP +format(true color). The resolution should be supported by the SVGA mode, so +the recommended is 320x240, 640x480, 800x640. + @example # try to boot from network first, then from hard disk qemu -boot order=nc # boot from CD-ROM first, switch back to default order after reboot qemu -boot once=d +# boot with a splash picture for 5 seconds. +qemu -boot menu=on,splash=/root/boot.bmp,splash-time=5000 @end example Note: The legacy format '-boot @var{drives}' is still supported but its @@ -1234,6 +1234,7 @@ int vmstate_register_with_alias_id(DeviceState *dev, int instance_id, se->opaque = opaque; se->vmsd = vmsd; se->alias_id = alias_id; + se->no_migrate = vmsd->unmigratable; if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) { char *id = dev->parent_bus->info->get_dev_path(dev); @@ -123,6 +123,9 @@ extern int no_shutdown; extern int semihosting_enabled; extern int old_param; extern int boot_menu; +extern uint8_t *boot_splash_filedata; +extern int boot_splash_filedata_size; +extern uint8_t qemu_extra_params_fw[2]; extern QEMUClock *rtc_clock; #define MAX_NODES 64 @@ -228,6 +228,9 @@ int ctrl_grab = 0; unsigned int nb_prom_envs = 0; const char *prom_envs[MAX_PROM_ENVS]; int boot_menu; +uint8_t *boot_splash_filedata; +int boot_splash_filedata_size; +uint8_t qemu_extra_params_fw[2]; typedef struct FWBootEntry FWBootEntry; @@ -293,6 +296,14 @@ static struct { { .driver = "qxl-vga", .flag = &default_vga }, }; +static void res_free(void) +{ + if (boot_splash_filedata != NULL) { + qemu_free(boot_splash_filedata); + boot_splash_filedata = NULL; + } +} + static int default_driver_check(QemuOpts *opts, void *opaque) { const char *driver = qemu_opt_get(opts, "driver"); @@ -2330,7 +2341,8 @@ int main(int argc, char **argv, char **envp) case QEMU_OPTION_boot: { static const char * const params[] = { - "order", "once", "menu", NULL + "order", "once", "menu", + "splash", "splash-time", NULL }; char buf[sizeof(boot_devices)]; char *standard_boot_devices; @@ -2373,6 +2385,8 @@ int main(int argc, char **argv, char **envp) exit(1); } } + qemu_opts_parse(qemu_find_opts("boot-opts"), + optarg, 0); } } break; @@ -2705,7 +2719,10 @@ int main(int argc, char **argv, char **envp) fprintf(stderr, "parse error: %s\n", optarg); exit(1); } - machine = machine_parse(qemu_opt_get(opts, "type")); + optarg = qemu_opt_get(opts, "type"); + if (optarg) { + machine = machine_parse(optarg); + } break; case QEMU_OPTION_usb: usb_enabled = 1; @@ -3339,6 +3356,7 @@ int main(int argc, char **argv, char **envp) main_loop(); quit_timers(); net_cleanup(); + res_free(); return 0; } diff --git a/xen-mapcache.c b/xen-mapcache.c index 007136af26..15d12413d4 100644 --- a/xen-mapcache.c +++ b/xen-mapcache.c @@ -237,7 +237,7 @@ uint8_t *xen_map_cache(target_phys_addr_t phys_addr, target_phys_addr_t size, ram_addr_t xen_ram_addr_from_mapcache(void *ptr) { - MapCacheEntry *entry = NULL, *pentry = NULL; + MapCacheEntry *entry = NULL; MapCacheRev *reventry; target_phys_addr_t paddr_index; target_phys_addr_t size; @@ -263,7 +263,6 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) entry = &mapcache->entry[paddr_index % mapcache->nr_buckets]; while (entry && (entry->paddr_index != paddr_index || entry->size != size)) { - pentry = entry; entry = entry->next; } if (!entry) { |