diff options
| -rw-r--r-- | hw/pxa2xx_dma.c | 4 | ||||
| -rw-r--r-- | hw/pxa2xx_gpio.c | 5 | ||||
| -rw-r--r-- | hw/pxa2xx_mmci.c | 2 | ||||
| -rw-r--r-- | hw/sd.c | 1 |
4 files changed, 9 insertions, 3 deletions
diff --git a/hw/pxa2xx_dma.c b/hw/pxa2xx_dma.c index 23bdae909b..4e33c53173 100644 --- a/hw/pxa2xx_dma.c +++ b/hw/pxa2xx_dma.c @@ -348,8 +348,10 @@ static void pxa2xx_dma_write(void *opaque, if (value & DCSR_NODESCFETCH) { /* No-descriptor-fetch mode */ - if (value & DCSR_RUN) + if (value & DCSR_RUN) { + s->chan[channel].state &= ~DCSR_STOPINTR; pxa2xx_dma_run(s); + } } else { /* Descriptor-fetch mode */ if (value & DCSR_RUN) { diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c index 9f5184438c..e3a30bc45e 100644 --- a/hw/pxa2xx_gpio.c +++ b/hw/pxa2xx_gpio.c @@ -154,6 +154,11 @@ static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset) __FUNCTION__, offset); return s->gpsr[bank]; /* Return last written value. */ + case GPCR: /* GPIO Pin-Output Clear registers */ + printf("%s: Read from a write-only register " REG_FMT "\n", + __FUNCTION__, offset); + return 31337; /* Specified as unpredictable in the docs. */ + case GRER: /* GPIO Rising-Edge Detect Enable registers */ return s->rising[bank]; diff --git a/hw/pxa2xx_mmci.c b/hw/pxa2xx_mmci.c index 6e244a96cc..9d26b7959e 100644 --- a/hw/pxa2xx_mmci.c +++ b/hw/pxa2xx_mmci.c @@ -549,5 +549,5 @@ struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base, void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly, qemu_irq coverswitch) { - sd_set_cb(s->card, read, coverswitch); + sd_set_cb(s->card, readonly, coverswitch); } @@ -377,7 +377,6 @@ static void sd_reset(SDState *sd, BlockDriverState *bdrv) qemu_free(sd->wp_groups); sd->wp_switch = bdrv_is_read_only(bdrv); sd->wp_groups = (int *) qemu_mallocz(sizeof(int) * sect); - memset(sd->wp_groups, 0, sizeof(int) * sect); memset(sd->function_group, 0, sizeof(int) * 6); sd->erase_start = 0; sd->erase_end = 0; |