diff options
| -rw-r--r-- | cpu-exec.c | 6 | ||||
| -rw-r--r-- | tcg/tcg.h | 2 | ||||
| -rw-r--r-- | tcg/tci/tcg-target.h | 2 | ||||
| -rw-r--r-- | tci.c | 4 |
4 files changed, 7 insertions, 7 deletions
diff --git a/cpu-exec.c b/cpu-exec.c index bd5791f8fa..0fa8325b27 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -55,7 +55,7 @@ void cpu_resume_from_signal(CPUArchState *env, void *puc) static void cpu_exec_nocache(CPUArchState *env, int max_cycles, TranslationBlock *orig_tb) { - unsigned long next_tb; + tcg_target_ulong next_tb; TranslationBlock *tb; /* Should never happen. @@ -186,7 +186,7 @@ int cpu_exec(CPUArchState *env) int ret, interrupt_request; TranslationBlock *tb; uint8_t *tc_ptr; - unsigned long next_tb; + tcg_target_ulong next_tb; if (env->halted) { if (!cpu_has_work(env)) { @@ -565,7 +565,7 @@ int cpu_exec(CPUArchState *env) if ((next_tb & 3) == 2) { /* Instruction counter expired. */ int insns_left; - tb = (TranslationBlock *)(long)(next_tb & ~3); + tb = (TranslationBlock *)(next_tb & ~3); /* Restore PC. */ cpu_pc_from_tb(env, tb); insns_left = env->icount_decr.u32; @@ -589,5 +589,5 @@ extern uint8_t code_gen_prologue[]; /* TCG targets may use a different definition of tcg_qemu_tb_exec. */ #if !defined(tcg_qemu_tb_exec) # define tcg_qemu_tb_exec(env, tb_ptr) \ - ((long REGPARM (*)(void *, void *))code_gen_prologue)(env, tb_ptr) + ((tcg_target_ulong REGPARM (*)(void *, void *))code_gen_prologue)(env, tb_ptr) #endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index b61e99aff1..30a0f21596 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -154,7 +154,7 @@ typedef enum { void tci_disas(uint8_t opc); -unsigned long tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); +tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); #define tcg_qemu_tb_exec tcg_qemu_tb_exec static inline void flush_icache_range(tcg_target_ulong start, @@ -429,9 +429,9 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) } /* Interpret pseudo code in tb. */ -unsigned long tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr) +tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr) { - unsigned long next_tb = 0; + tcg_target_ulong next_tb = 0; env = cpustate; tci_reg[TCG_AREG0] = (tcg_target_ulong)env; |