diff options
| -rw-r--r-- | hw/apb_pci.c | 15 | ||||
| -rw-r--r-- | hw/cs4231.c | 3 | ||||
| -rw-r--r-- | hw/eccmemctl.c | 5 | ||||
| -rw-r--r-- | hw/slavio_intctl.c | 34 | ||||
| -rw-r--r-- | hw/slavio_timer.c | 9 | ||||
| -rw-r--r-- | hw/sun4c_intctl.c | 6 | ||||
| -rw-r--r-- | hw/sun4m.c | 30 | ||||
| -rw-r--r-- | hw/sun4u.c | 27 | ||||
| -rw-r--r-- | hw/tcx.c | 3 | ||||
| -rw-r--r-- | target-sparc/cpu.h | 2 | ||||
| -rw-r--r-- | target-sparc/helper.c | 72 | ||||
| -rw-r--r-- | target-sparc/op_helper.c | 128 | ||||
| -rw-r--r-- | target-sparc/translate.c | 261 |
13 files changed, 395 insertions, 200 deletions
diff --git a/hw/apb_pci.c b/hw/apb_pci.c index 73dcf5c136..b56bb0733f 100644 --- a/hw/apb_pci.c +++ b/hw/apb_pci.c @@ -230,9 +230,12 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base, pci_apb_iowrite, s); cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config); - cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10, pci_mem_config); - cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, pci_ioport); - cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom + cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10, + pci_mem_config); + cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, + pci_ioport); + cpu_register_physical_memory(mem_base, 0x10000000, + pci_mem_data); // XXX size should be 4G-prom d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice), 0, NULL, NULL); @@ -252,8 +255,10 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base, d->config[0x0E] = 0x00; // header_type /* APB secondary busses */ - secondary = pci_bridge_init(s->bus, 8, 0x108e5000, pci_apb_map_irq, "Advanced PCI Bus secondary bridge 1"); - pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq, "Advanced PCI Bus secondary bridge 2"); + secondary = pci_bridge_init(s->bus, 8, 0x108e5000, pci_apb_map_irq, + "Advanced PCI Bus secondary bridge 1"); + pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq, + "Advanced PCI Bus secondary bridge 2"); return secondary; } diff --git a/hw/cs4231.c b/hw/cs4231.c index 11a6add756..8ba8253945 100644 --- a/hw/cs4231.c +++ b/hw/cs4231.c @@ -98,7 +98,8 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val); switch (saddr) { case 1: - DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s), s->dregs[CS_RAP(s)], val); + DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s), + s->dregs[CS_RAP(s)], val); switch(CS_RAP(s)) { case 11: case 25: // Read only diff --git a/hw/eccmemctl.c b/hw/eccmemctl.c index 772c1c2211..fe7f27e06c 100644 --- a/hw/eccmemctl.c +++ b/hw/eccmemctl.c @@ -53,7 +53,8 @@ /* ECC fault control register */ #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ -#define ECC_MER_EI 0x00000002 /* Enable Interrupts on correctable errors */ +#define ECC_MER_EI 0x00000002 /* Enable Interrupts on + correctable errors */ #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ @@ -65,7 +66,7 @@ #define ECC_MER_REU 0x00000200 /* Memory Refresh Enable (600MP) */ #define ECC_MER_MRR 0x000003fc /* MRR mask */ #define ECC_MEM_A 0x00000400 /* Memory controller addr map select */ -#define ECC_MER_DCI 0x00000800 /* Dsiables Coherent Invalidate ACK */ +#define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ #define ECC_MER_VER 0x0f000000 /* Version */ #define ECC_MER_IMPL 0xf0000000 /* Implementation */ diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c index 39851def1b..6a5d505030 100644 --- a/hw/slavio_intctl.c +++ b/hw/slavio_intctl.c @@ -99,7 +99,8 @@ static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) return ret; } -static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, + uint32_t val) { SLAVIO_INTCTLState *s = opaque; uint32_t saddr; @@ -115,13 +116,15 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint val &= CPU_SOFTIRQ_MASK; s->intreg_pending[cpu] &= ~val; slavio_check_interrupts(s); - DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); + DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, + s->intreg_pending[cpu]); break; case 2: // set softint val &= CPU_SOFTIRQ_MASK; s->intreg_pending[cpu] |= val; slavio_check_interrupts(s); - DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); + DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, + s->intreg_pending[cpu]); break; default: break; @@ -166,7 +169,8 @@ static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr) return ret; } -static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, + uint32_t val) { SLAVIO_INTCTLState *s = opaque; uint32_t saddr; @@ -178,7 +182,8 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin // Force clear unused bits val &= MASTER_IRQ_MASK; s->intregm_disabled &= ~val; - DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); + DPRINTF("Enabled master irq mask %x, curmask %x\n", val, + s->intregm_disabled); slavio_check_interrupts(s); break; case 3: // set (disable, clear pending) @@ -187,7 +192,8 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin s->intregm_disabled |= val; s->intregm_pending &= ~val; slavio_check_interrupts(s); - DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); + DPRINTF("Disabled master irq mask %x, curmask %x\n", val, + s->intregm_disabled); break; case 4: s->target_cpu = val & (MAX_CPUS - 1); @@ -219,7 +225,8 @@ void slavio_pic_info(void *opaque) for (i = 0; i < MAX_CPUS; i++) { term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]); } - term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled); + term_printf("master: pending 0x%08x, disabled 0x%08x\n", + s->intregm_pending, s->intregm_disabled); } void slavio_irq_info(void *opaque) @@ -376,16 +383,23 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg, s->intbit_to_level = intbit_to_level; for (i = 0; i < MAX_CPUS; i++) { - slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s); + slavio_intctl_io_memory = cpu_register_io_memory(0, + slavio_intctl_mem_read, + slavio_intctl_mem_write, + s); cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE, slavio_intctl_io_memory); s->cpu_irqs[i] = parent_irq[i]; } - slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s); + slavio_intctlm_io_memory = cpu_register_io_memory(0, + slavio_intctlm_mem_read, + slavio_intctlm_mem_write, + s); cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory); - register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s); + register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, + slavio_intctl_load, s); qemu_register_reset(slavio_intctl_reset, s); *irq = qemu_allocate_irqs(slavio_set_irq, s, 32); diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c index 3d9c110a2a..f091fbe5f9 100644 --- a/hw/slavio_timer.c +++ b/hw/slavio_timer.c @@ -206,7 +206,8 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, s->limit = val & TIMER_MAX_COUNT32; if (s->timer) { if (s->limit == 0) /* free-run */ - ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); + ptimer_set_limit(s->timer, + LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); else ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1); } @@ -233,7 +234,8 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, s->limit = val & TIMER_MAX_COUNT32; if (s->timer) { if (s->limit == 0) /* free-run */ - ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0); + ptimer_set_limit(s->timer, + LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0); else ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 0); } @@ -271,7 +273,8 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, // user timer limit is always the same s->slave[i]->limit = TIMER_MAX_COUNT64; ptimer_set_limit(s->slave[i]->timer, - LIMIT_TO_PERIODS(s->slave[i]->limit), 1); + LIMIT_TO_PERIODS(s->slave[i]->limit), + 1); // set this processors user timer bit in config // register s->slave_mode |= processor; diff --git a/hw/sun4c_intctl.c b/hw/sun4c_intctl.c index 510eb2e119..88cd4a53bd 100644 --- a/hw/sun4c_intctl.c +++ b/hw/sun4c_intctl.c @@ -68,7 +68,8 @@ static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr) return ret; } -static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr, + uint32_t val) { Sun4c_INTCTLState *s = opaque; @@ -94,7 +95,8 @@ void sun4c_pic_info(void *opaque) { Sun4c_INTCTLState *s = opaque; - term_printf("master: pending 0x%2.2x, enabled 0x%2.2x\n", s->pending, s->reg); + term_printf("master: pending 0x%2.2x, enabled 0x%2.2x\n", s->pending, + s->reg); } void sun4c_irq_info(void *opaque) diff --git a/hw/sun4m.c b/hw/sun4m.c index 76caa89605..5e0eca4946 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -41,7 +41,8 @@ * Sun4m architecture was used in the following machines: * * SPARCserver 6xxMP/xx - * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10) + * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), + * SPARCclassic X (4/10) * SPARCstation LX/ZX (4/30) * SPARCstation Voyager * SPARCstation 10/xx, SPARCserver 10/xx @@ -327,9 +328,11 @@ static unsigned long sun4m_load_kernel(const char *kernel_filename, kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, NULL); if (kernel_size < 0) - kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); + kernel_size = load_aout(kernel_filename, + phys_ram_base + KERNEL_LOAD_ADDR); if (kernel_size < 0) - kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); + kernel_size = load_image(kernel_filename, + phys_ram_base + KERNEL_LOAD_ADDR); if (kernel_size < 0) { fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); @@ -339,7 +342,8 @@ static unsigned long sun4m_load_kernel(const char *kernel_filename, /* load initrd */ initrd_size = 0; if (initrd_filename) { - initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); + initrd_size = load_image(initrd_filename, + phys_ram_base + INITRD_LOAD_ADDR); if (initrd_size < 0) { fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", initrd_filename); @@ -350,8 +354,10 @@ static unsigned long sun4m_load_kernel(const char *kernel_filename, for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, + INITRD_LOAD_ADDR); + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, + initrd_size); break; } } @@ -409,7 +415,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, /* allocate RAM */ if ((uint64_t)RAM_size > hwdef->max_mem) { - fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n", + fprintf(stderr, + "qemu: Too much memory for this machine: %d, maximum %d\n", (unsigned int)(RAM_size / (1024 * 1024)), (unsigned int)(hwdef->max_mem / (1024 * 1024))); exit(1); @@ -575,7 +582,8 @@ static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, /* allocate RAM */ if ((uint64_t)RAM_size > hwdef->max_mem) { - fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n", + fprintf(stderr, + "qemu: Too much memory for this machine: %d, maximum %d\n", (unsigned int)(RAM_size / (1024 * 1024)), (unsigned int)(hwdef->max_mem / (1024 * 1024))); exit(1); @@ -1127,7 +1135,8 @@ static void ss10_init(ram_addr_t RAM_size, int vga_ram_size, /* SPARCserver 600MP hardware initialisation */ static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size, const char *boot_device, DisplayState *ds, - const char *kernel_filename, const char *kernel_cmdline, + const char *kernel_filename, + const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename, @@ -1388,7 +1397,8 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, /* allocate RAM */ if ((uint64_t)RAM_size > hwdef->max_mem) { - fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n", + fprintf(stderr, + "qemu: Too much memory for this machine: %d, maximum %d\n", (unsigned int)(RAM_size / (1024 * 1024)), (unsigned int)(hwdef->max_mem / (1024 * 1024))); exit(1); diff --git a/hw/sun4u.c b/hw/sun4u.c index 55c6c63834..8c0617637b 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -72,7 +72,8 @@ extern int nographic; static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, const unsigned char *arch, - ram_addr_t RAM_size, const char *boot_devices, + ram_addr_t RAM_size, + const char *boot_devices, uint32_t kernel_image, uint32_t kernel_size, const char *cmdline, uint32_t initrd_image, uint32_t initrd_size, @@ -268,7 +269,8 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, prom_offset = RAM_size + vga_ram_size; cpu_register_physical_memory(PROM_ADDR, - (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, + (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & + TARGET_PAGE_MASK, prom_offset | IO_MEM_ROM); if (bios_name == NULL) @@ -287,9 +289,11 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, /* XXX: put correct offset */ kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); if (kernel_size < 0) - kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); + kernel_size = load_aout(kernel_filename, + phys_ram_base + KERNEL_LOAD_ADDR); if (kernel_size < 0) - kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); + kernel_size = load_image(kernel_filename, + phys_ram_base + KERNEL_LOAD_ADDR); if (kernel_size < 0) { fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); @@ -298,7 +302,8 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, /* load initrd */ if (initrd_filename) { - initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); + initrd_size = load_image(initrd_filename, + phys_ram_base + INITRD_LOAD_ADDR); if (initrd_size < 0) { fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", initrd_filename); @@ -309,8 +314,10 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, + INITRD_LOAD_ADDR); + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, + initrd_size); break; } } @@ -318,7 +325,8 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, } pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL); isa_mem_base = VGA_BASE; - pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size, vga_ram_size); + pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size, + vga_ram_size); for(i = 0; i < MAX_SERIAL_PORTS; i++) { if (serial_hds[i]) { @@ -329,7 +337,8 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, for(i = 0; i < MAX_PARALLEL_PORTS; i++) { if (parallel_hds[i]) { - parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]); + parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, + parallel_hds[i]); } } @@ -516,7 +516,8 @@ void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base, vram_base += size; io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s); - cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS, io_memory); + cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS, + io_memory); dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write, s); diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index fbd9c2a7e6..af0ebd177b 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -347,7 +347,7 @@ void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); #ifdef TARGET_SPARC64 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20)) #define PUT_CCR(env, val) do { int _tmp = val; \ - env->xcc = (_tmp >> 4) << 20; \ + env->xcc = (_tmp >> 4) << 20; \ env->psr = (_tmp & 0xf) << 20; \ } while (0) #define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp) diff --git a/target-sparc/helper.c b/target-sparc/helper.c index 759232a674..1bc2fededa 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -193,7 +193,8 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical, return (3 << 8) | (4 << 2); case 2: /* L3 PTE */ virt_addr = address & TARGET_PAGE_MASK; - page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1); + page_offset = (address & TARGET_PAGE_MASK) & + (TARGET_PAGE_SIZE - 1); } break; case 2: /* L2 PTE */ @@ -243,7 +244,8 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, target_ulong vaddr; int error_code = 0, prot, ret = 0, access_index; - error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx); + error_code = get_physical_address(env, &paddr, &prot, &access_index, + address, rw, mmu_idx); if (error_code == 0) { vaddr = address & TARGET_PAGE_MASK; paddr &= TARGET_PAGE_MASK; @@ -387,7 +389,8 @@ void dump_mmu(CPUState *env) /* * UltraSparc IIi I/DMMUs */ -static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot, +static int get_physical_address_data(CPUState *env, + target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int is_user) { target_ulong mask; @@ -423,7 +426,8 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical ((env->dtlb_tte[i] & 0x4) && is_user) || (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) { if (env->dmmuregs[3]) /* Fault status register */ - env->dmmuregs[3] = 2; /* overflow (not read before another fault) */ + env->dmmuregs[3] = 2; /* overflow (not read before + another fault) */ env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1; env->dmmuregs[4] = address; /* Fault address register */ env->exception_index = TT_DFAULT; @@ -432,7 +436,8 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical #endif return 1; } - *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); + *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + + (address & ~mask & 0x1fffffff000ULL); *prot = PAGE_READ; if (env->dtlb_tte[i] & 0x2) *prot |= PAGE_WRITE; @@ -446,7 +451,8 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical return 1; } -static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot, +static int get_physical_address_code(CPUState *env, + target_phys_addr_t *physical, int *prot, target_ulong address, int is_user) { target_ulong mask; @@ -481,7 +487,8 @@ static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 || ((env->itlb_tte[i] & 0x4) && is_user)) { if (env->immuregs[3]) /* Fault status register */ - env->immuregs[3] = 2; /* overflow (not read before another fault) */ + env->immuregs[3] = 2; /* overflow (not read before + another fault) */ env->immuregs[3] |= (is_user << 3) | 1; env->exception_index = TT_TFAULT; #ifdef DEBUG_MMU @@ -489,7 +496,8 @@ static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical #endif return 1; } - *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); + *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + + (address & ~mask & 0x1fffffff000ULL); *prot = PAGE_EXEC; return 0; } @@ -523,12 +531,15 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, target_phys_addr_t paddr; int error_code = 0, prot, ret = 0, access_index; - error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx); + error_code = get_physical_address(env, &paddr, &prot, &access_index, + address, rw, mmu_idx); if (error_code == 0) { virt_addr = address & TARGET_PAGE_MASK; - vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1)); + vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & + (TARGET_PAGE_SIZE - 1)); #ifdef DEBUG_MMU - printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr); + printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 + "\n", address, paddr, vaddr); #endif ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); return ret; @@ -543,7 +554,8 @@ void dump_mmu(CPUState *env) unsigned int i; const char *mask; - printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]); + printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", + env->dmmuregs[1], env->dmmuregs[2]); if ((env->lsu & DMMU_E) == 0) { printf("DMMU disabled\n"); } else { @@ -565,7 +577,8 @@ void dump_mmu(CPUState *env) break; } if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { - printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n", + printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx + ", %s, %s, %s, %s, ctx %" PRId64 "\n", env->dtlb_tag[i] & ~0x1fffULL, env->dtlb_tte[i] & 0x1ffffffe000ULL, mask, @@ -597,7 +610,8 @@ void dump_mmu(CPUState *env) break; } if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { - printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n", + printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx + ", %s, %s, %s, ctx %" PRId64 "\n", env->itlb_tag[i] & ~0x1fffULL, env->itlb_tte[i] & 0x1ffffffe000ULL, mask, @@ -1206,7 +1220,8 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) goto error; } } else { - fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr); + fprintf(stderr, "feature string `%s' not in format " + "(+feature|-feature|feature=xyz)\n", featurestr); goto error; } featurestr = strtok(NULL, ","); @@ -1224,7 +1239,7 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) return -1; } -void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) +void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) { unsigned int i; @@ -1234,14 +1249,17 @@ void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) sparc_defs[i].iu_version, sparc_defs[i].fpu_version, sparc_defs[i].mmu_version); - print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-"); - print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+"); + print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & + ~sparc_defs[i].features, "-"); + print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & + sparc_defs[i].features, "+"); (*cpu_fprintf)(f, "\n"); } (*cpu_fprintf)(f, "CPU feature flags (+/-): "); print_features(f, cpu_fprintf, -1, NULL); (*cpu_fprintf)(f, "\n"); - (*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version mmu_version\n"); + (*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version " + "mmu_version\n"); } #define GET_FLAG(a,b) ((env->psr & a)?b:'-') @@ -1252,7 +1270,8 @@ void cpu_dump_state(CPUState *env, FILE *f, { int i, x; - cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); + cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, + env->npc); cpu_fprintf(f, "General Registers:\n"); for (i = 0; i < 4; i++) cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); @@ -1283,15 +1302,16 @@ void cpu_dump_state(CPUState *env, FILE *f, #ifdef TARGET_SPARC64 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n", env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); - cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n", + cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d " + "cleanwin %d cwp %d\n", env->cansave, env->canrestore, env->otherwin, env->wstate, env->cleanwin, NWINDOWS - 1 - env->cwp); #else - cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env), - GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), - GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), - env->psrs?'S':'-', env->psrps?'P':'-', - env->psret?'E':'-', env->wim); + cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", + GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), + GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), + env->psrs?'S':'-', env->psrps?'P':'-', + env->psret?'E':'-', env->wim); #endif cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env)); } diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index cb2b38d56f..b6e2166809 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -795,15 +795,19 @@ GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); #endif -#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC) +#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \ + defined(DEBUG_MXCC) static void dump_mxcc(CPUState *env) { printf("mxccdata: %016llx %016llx %016llx %016llx\n", - env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]); + env->mxccdata[0], env->mxccdata[1], + env->mxccdata[2], env->mxccdata[3]); printf("mxccregs: %016llx %016llx %016llx %016llx\n" " %016llx %016llx %016llx %016llx\n", - env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3], - env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]); + env->mxccregs[0], env->mxccregs[1], + env->mxccregs[2], env->mxccregs[3], + env->mxccregs[4], env->mxccregs[5], + env->mxccregs[6], env->mxccregs[7]); } #endif @@ -851,32 +855,38 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) if (size == 8) ret = env->mxccregs[3]; else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); break; case 0x01c00a04: /* MXCC control register */ if (size == 4) ret = env->mxccregs[3]; else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); break; case 0x01c00c00: /* Module reset register */ if (size == 8) { ret = env->mxccregs[5]; // should we do something here? } else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); break; case 0x01c00f00: /* MBus port address register */ if (size == 8) ret = env->mxccregs[7]; else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); break; default: - DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, + size); break; } - DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x," + DPRINTF_MXCC("asi = %d, size = %d, sign = %d, " + "addr = %08x -> ret = %08x," "addr = %08x\n", asi, size, sign, last_addr, ret, addr); #ifdef DEBUG_MXCC dump_mxcc(env); @@ -1050,76 +1060,97 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) if (size == 8) env->mxccdata[0] = val; else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); break; case 0x01c00008: /* MXCC stream data register 1 */ if (size == 8) env->mxccdata[1] = val; else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); break; case 0x01c00010: /* MXCC stream data register 2 */ if (size == 8) env->mxccdata[2] = val; else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); break; case 0x01c00018: /* MXCC stream data register 3 */ if (size == 8) env->mxccdata[3] = val; else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); break; case 0x01c00100: /* MXCC stream source */ if (size == 8) env->mxccregs[0] = val; else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); - env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0); - env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8); - env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16); - env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); + env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + + 0); + env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + + 8); + env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + + 16); + env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + + 24); break; case 0x01c00200: /* MXCC stream destination */ if (size == 8) env->mxccregs[1] = val; else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); - stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]); - stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]); - stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]); - stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); + stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, + env->mxccdata[0]); + stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, + env->mxccdata[1]); + stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, + env->mxccdata[2]); + stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, + env->mxccdata[3]); break; case 0x01c00a00: /* MXCC control register */ if (size == 8) env->mxccregs[3] = val; else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); break; case 0x01c00a04: /* MXCC control register */ if (size == 4) - env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val; + env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) + | val; else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); break; case 0x01c00e00: /* MXCC error register */ // writing a 1 bit clears the error if (size == 8) env->mxccregs[6] &= ~val; else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); break; case 0x01c00f00: /* MBus port address register */ if (size == 8) env->mxccregs[7] = val; else - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, + size); break; default: - DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size); + DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, + size); break; } - DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val); + DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, + size, addr, val); #ifdef DEBUG_MXCC dump_mxcc(env); #endif @@ -1192,7 +1223,8 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) break; } if (oldreg != env->mmuregs[reg]) { - DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]); + DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", + reg, oldreg, env->mmuregs[reg]); } #ifdef DEBUG_MMU dump_mmu(env); @@ -1317,7 +1349,8 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic case 0x31: // store buffer data, Ross RT620 I-cache flush or // Turbosparc snoop RAM - case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic + case 0x32: // store buffer control or Turbosparc page table + // descriptor diagnostic case 0x36: /* I-cache flash clear */ case 0x37: /* D-cache flash clear */ case 0x38: /* breakpoint diagnostics */ @@ -1860,7 +1893,8 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) // Mappings generated during D/I MMU disabled mode are // invalid in normal mode if (oldreg != env->lsu) { - DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu); + DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", + oldreg, env->lsu); #ifdef DEBUG_MMU dump_mmu(env); #endif @@ -1894,7 +1928,8 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) } env->immuregs[reg] = val; if (oldreg != env->immuregs[reg]) { - DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]); + DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" + PRIx64 "\n", reg, oldreg, env->immuregs[reg]); } #ifdef DEBUG_MMU dump_mmu(env); @@ -1963,7 +1998,8 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) } env->dmmuregs[reg] = val; if (oldreg != env->dmmuregs[reg]) { - DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); + DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" + PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); } #ifdef DEBUG_MMU dump_mmu(env); @@ -2042,7 +2078,8 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd) } helper_check_align(addr, 0x3f); for (i = 0; i < 16; i++) { - *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0); + *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, + 0); addr += 4; } @@ -2697,7 +2734,8 @@ void do_interrupt(int intno) #endif #if !defined(CONFIG_USER_ONLY) if (env->tl == MAXTL) { - cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index); + cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", + env->exception_index); return; } #endif @@ -2807,7 +2845,8 @@ void do_interrupt(int intno) #endif #if !defined(CONFIG_USER_ONLY) if (env->psret == 0) { - cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index); + cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", + env->exception_index); return; } #endif @@ -2833,7 +2872,8 @@ static void do_unaligned_access(target_ulong addr, int is_write, int is_user, #define MMUSUFFIX _mmu #define ALIGNED_ONLY #ifdef __s390__ -# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL)) +# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & \ + 0x7fffffffUL)) #else # define GETPC() (__builtin_return_address(0)) #endif @@ -2915,8 +2955,8 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, env = cpu_single_env; #ifdef DEBUG_UNASSIGNED if (is_asi) - printf("Unassigned mem %s access to " TARGET_FMT_plx " asi 0x%02x from " - TARGET_FMT_lx "\n", + printf("Unassigned mem %s access to " TARGET_FMT_plx + " asi 0x%02x from " TARGET_FMT_lx "\n", is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi, env->pc); else @@ -2955,8 +2995,8 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, generated code */ saved_env = env; env = cpu_single_env; - printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n", - addr, env->pc); + printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx + "\n", addr, env->pc); env = saved_env; #endif if (is_exec) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 7b0363d6f0..5b1b291c92 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -38,7 +38,8 @@ according to jump_pc[T2] */ /* global register indexes */ -static TCGv cpu_env, cpu_T[2], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst; +static TCGv cpu_env, cpu_T[2], cpu_regwptr; +static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val; #ifdef TARGET_SPARC64 @@ -109,60 +110,78 @@ static void gen_op_store_FT0_fpr(unsigned int dst) static void gen_op_load_fpr_DT0(unsigned int src) { tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + + offsetof(CPU_DoubleU, l.upper)); tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + + offsetof(CPU_DoubleU, l.lower)); } static void gen_op_load_fpr_DT1(unsigned int src) { tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + + offsetof(CPU_DoubleU, l.upper)); tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + + offsetof(CPU_DoubleU, l.lower)); } static void gen_op_store_DT0_fpr(unsigned int dst) { - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + + offsetof(CPU_DoubleU, l.upper)); tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + + offsetof(CPU_DoubleU, l.lower)); tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1])); } static void gen_op_load_fpr_QT0(unsigned int src) { tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + + offsetof(CPU_QuadU, l.upmost)); tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + + offsetof(CPU_QuadU, l.upper)); tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2])); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + + offsetof(CPU_QuadU, l.lower)); tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3])); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + + offsetof(CPU_QuadU, l.lowest)); } static void gen_op_load_fpr_QT1(unsigned int src) { tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + + offsetof(CPU_QuadU, l.upmost)); tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + + offsetof(CPU_QuadU, l.upper)); tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2])); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + + offsetof(CPU_QuadU, l.lower)); tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3])); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + + offsetof(CPU_QuadU, l.lowest)); } static void gen_op_store_QT0_fpr(unsigned int dst) { - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + + offsetof(CPU_QuadU, l.upmost)); tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + + offsetof(CPU_QuadU, l.upper)); tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1])); - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + + offsetof(CPU_QuadU, l.lower)); tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2])); - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + + offsetof(CPU_QuadU, l.lowest)); tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3])); } @@ -1591,7 +1610,8 @@ static inline TCGv gen_get_asi(int insn, TCGv r_addr) return r_asi; } -static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign) +static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, + int sign) { TCGv r_asi; @@ -1664,7 +1684,8 @@ static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) tcg_const_i32(8)); } -static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd) +static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, + int rd) { TCGv r_val1, r_asi; @@ -1674,7 +1695,8 @@ static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd) tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi); } -static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd) +static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, + int rd) { TCGv r_asi; @@ -1685,7 +1707,8 @@ static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd #elif !defined(CONFIG_USER_ONLY) -static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign) +static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, + int sign) { int asi; @@ -1970,7 +1993,8 @@ static void disas_sparc_insn(DisasContext * dc) SPARCv8 manual, rdy on the microSPARC II */ #endif - tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y)); + tcg_gen_ld_tl(cpu_dst, cpu_env, + offsetof(CPUSPARCState, y)); gen_movl_TN_reg(rd, cpu_dst); break; #ifdef TARGET_SPARC64 @@ -1979,7 +2003,8 @@ static void disas_sparc_insn(DisasContext * dc) gen_movl_TN_reg(rd, cpu_dst); break; case 0x3: /* V9 rdasi */ - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, asi)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); gen_movl_TN_reg(rd, cpu_dst); break; @@ -1999,7 +2024,8 @@ static void disas_sparc_insn(DisasContext * dc) gen_movl_TN_reg(rd, tcg_const_tl(dc->pc)); break; case 0x6: /* V9 rdfprs */ - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, fprs)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); gen_movl_TN_reg(rd, cpu_dst); break; @@ -2008,11 +2034,13 @@ static void disas_sparc_insn(DisasContext * dc) case 0x13: /* Graphics Status */ if (gen_trap_ifnofpu(dc, cpu_cond)) goto jmp_insn; - tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr)); + tcg_gen_ld_tl(cpu_dst, cpu_env, + offsetof(CPUSPARCState, gsr)); gen_movl_TN_reg(rd, cpu_dst); break; case 0x17: /* Tick compare */ - tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tick_cmpr)); + tcg_gen_ld_tl(cpu_dst, cpu_env, + offsetof(CPUSPARCState, tick_cmpr)); gen_movl_TN_reg(rd, cpu_dst); break; case 0x18: /* System tick */ @@ -2028,7 +2056,8 @@ static void disas_sparc_insn(DisasContext * dc) } break; case 0x19: /* System tick compare */ - tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, stick_cmpr)); + tcg_gen_ld_tl(cpu_dst, cpu_env, + offsetof(CPUSPARCState, stick_cmpr)); gen_movl_TN_reg(rd, cpu_dst); break; case 0x10: /* Performance Control */ @@ -2059,20 +2088,24 @@ static void disas_sparc_insn(DisasContext * dc) // gen_op_rdhtstate(); break; case 3: // hintp - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, hintp)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); break; case 5: // htba - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, htba)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); break; case 6: // hver - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hver)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, hver)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); break; case 31: // hstick_cmpr tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hstick_cmpr)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, hstick_cmpr)); break; default: goto illegal_insn; @@ -2143,62 +2176,75 @@ static void disas_sparc_insn(DisasContext * dc) } break; case 5: // tba - tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr)); + tcg_gen_ld_tl(cpu_dst, cpu_env, + offsetof(CPUSPARCState, tbr)); break; case 6: // pstate - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, pstate)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, pstate)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); break; case 7: // tl - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, tl)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); break; case 8: // pil - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, psrpil)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); break; case 9: // cwp tcg_gen_helper_1_0(helper_rdcwp, cpu_dst); break; case 10: // cansave - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, cansave)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); break; case 11: // canrestore - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, canrestore)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); break; case 12: // cleanwin - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, cleanwin)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); break; case 13: // otherwin - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, otherwin)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); break; case 14: // wstate - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, wstate)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); break; case 16: // UA2005 gl - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, gl)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); break; case 26: // UA2005 strand status if (!hypervisor(dc)) goto priv_insn; - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, ssr)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); break; case 31: // ver - tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, version)); + tcg_gen_ld_tl(cpu_dst, cpu_env, + offsetof(CPUSPARCState, version)); break; case 15: // fq default: goto illegal_insn; } #else - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim)); + tcg_gen_ld_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, wim)); tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); #endif gen_movl_TN_reg(rd, cpu_dst); @@ -2603,8 +2649,10 @@ static void disas_sparc_insn(DisasContext * dc) gen_fcond(r_cond, fcc, cond); \ tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \ tcg_const_tl(0), l1); \ - glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \ - glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \ + glue(glue(gen_op_load_fpr_, size_FDQ), T0) \ + (glue(size_FDQ, FPREG(rs2))); \ + glue(glue(gen_op_store_, size_FDQ), T0_fpr) \ + (glue(size_FDQ, FPREG(rd))); \ gen_set_label(l1); \ } case 0x001: /* V9 fmovscc %fcc0 */ @@ -2659,8 +2707,10 @@ static void disas_sparc_insn(DisasContext * dc) gen_cond(r_cond, icc, cond); \ tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \ tcg_const_tl(0), l1); \ - glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \ - glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \ + glue(glue(gen_op_load_fpr_, size_FDQ), T0) \ + (glue(size_FDQ, FPREG(rs2))); \ + glue(glue(gen_op_store_, size_FDQ), T0_fpr) \ + (glue(size_FDQ, FPREG(rd))); \ gen_set_label(l1); \ } @@ -2916,13 +2966,15 @@ static void disas_sparc_insn(DisasContext * dc) #endif case 0xe: CHECK_IU_FEATURE(dc, DIV); - tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, cpu_src2); + tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, + cpu_src2); if (xop & 0x10) gen_op_div_cc(cpu_dst); break; case 0xf: CHECK_IU_FEATURE(dc, DIV); - tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, cpu_src2); + tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, + cpu_src2); if (xop & 0x10) gen_op_div_cc(cpu_dst); break; @@ -2976,7 +3028,8 @@ static void disas_sparc_insn(DisasContext * dc) switch(rd) { case 0: /* wry */ tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y)); + tcg_gen_st_tl(cpu_dst, cpu_env, + offsetof(CPUSPARCState, y)); break; #ifndef TARGET_SPARC64 case 0x01 ... 0x0f: /* undefined in the @@ -2996,12 +3049,14 @@ static void disas_sparc_insn(DisasContext * dc) case 0x3: /* V9 wrasi */ tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, asi)); break; case 0x6: /* V9 wrfprs */ tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, fprs)); save_state(dc, cpu_cond); gen_op_next_insn(); tcg_gen_exit_tb(0); @@ -3017,7 +3072,8 @@ static void disas_sparc_insn(DisasContext * dc) if (gen_trap_ifnofpu(dc, cpu_cond)) goto jmp_insn; tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr)); + tcg_gen_st_tl(cpu_dst, cpu_env, + offsetof(CPUSPARCState, gsr)); break; case 0x17: /* Tick compare */ #if !defined(CONFIG_USER_ONLY) @@ -3029,8 +3085,9 @@ static void disas_sparc_insn(DisasContext * dc) tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, - tick_cmpr)); + tcg_gen_st_tl(cpu_dst, cpu_env, + offsetof(CPUSPARCState, + tick_cmpr)); r_tickptr = tcg_temp_new(TCG_TYPE_PTR); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUState, tick)); @@ -3065,8 +3122,9 @@ static void disas_sparc_insn(DisasContext * dc) tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, - stick_cmpr)); + tcg_gen_st_tl(cpu_dst, cpu_env, + offsetof(CPUSPARCState, + stick_cmpr)); r_tickptr = tcg_temp_new(TCG_TYPE_PTR); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUState, stick)); @@ -3076,7 +3134,8 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x10: /* Performance Control */ - case 0x11: /* Performance Instrumentation Counter */ + case 0x11: /* Performance Instrumentation + Counter */ case 0x12: /* Dispatch Control */ case 0x14: /* Softint set */ case 0x15: /* Softint clear */ @@ -3155,7 +3214,8 @@ static void disas_sparc_insn(DisasContext * dc) tcg_gen_ld_ptr(r_tsptr, cpu_env, offsetof(CPUState, tsptr)); tcg_gen_st_tl(cpu_dst, r_tsptr, - offsetof(trap_state, tstate)); + offsetof(trap_state, + tstate)); } break; case 3: // tt @@ -3181,7 +3241,8 @@ static void disas_sparc_insn(DisasContext * dc) } break; case 5: // tba - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr)); + tcg_gen_st_tl(cpu_dst, cpu_env, + offsetof(CPUSPARCState, tbr)); break; case 6: // pstate save_state(dc, cpu_cond); @@ -3192,52 +3253,69 @@ static void disas_sparc_insn(DisasContext * dc) break; case 7: // tl tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, tl)); break; case 8: // pil tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, + psrpil)); break; case 9: // cwp tcg_gen_helper_0_1(helper_wrcwp, cpu_dst); break; case 10: // cansave tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, + cansave)); break; case 11: // canrestore tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, + canrestore)); break; case 12: // cleanwin tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, + cleanwin)); break; case 13: // otherwin tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, + otherwin)); break; case 14: // wstate tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, + wstate)); break; case 16: // UA2005 gl tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, gl)); break; case 26: // UA2005 strand status if (!hypervisor(dc)) goto priv_insn; tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, ssr)); break; default: goto illegal_insn; } #else - tcg_gen_andi_tl(cpu_dst, cpu_dst, ((1 << NWINDOWS) - 1)); + tcg_gen_andi_tl(cpu_dst, cpu_dst, + ((1 << NWINDOWS) - 1)); tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, wim)); #endif } break; @@ -3247,7 +3325,8 @@ static void disas_sparc_insn(DisasContext * dc) if (!supervisor(dc)) goto priv_insn; tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2); - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr)); + tcg_gen_st_tl(cpu_dst, cpu_env, + offsetof(CPUSPARCState, tbr)); #else if (!hypervisor(dc)) goto priv_insn; @@ -3265,18 +3344,21 @@ static void disas_sparc_insn(DisasContext * dc) break; case 3: // hintp tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, hintp)); break; case 5: // htba tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba)); + tcg_gen_st_i32(cpu_tmp32, cpu_env, + offsetof(CPUSPARCState, htba)); break; case 31: // hstick_cmpr { TCGv r_tickptr; - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, - hstick_cmpr)); + tcg_gen_st_tl(cpu_dst, cpu_env, + offsetof(CPUSPARCState, + hstick_cmpr)); r_tickptr = tcg_temp_new(TCG_TYPE_PTR); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUState, hstick)); @@ -3854,7 +3936,8 @@ static void disas_sparc_insn(DisasContext * dc) } tcg_gen_helper_0_0(helper_restore); gen_mov_pc_npc(dc, cpu_cond); - tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3)); + tcg_gen_helper_0_2(helper_check_align, cpu_dst, + tcg_const_i32(3)); tcg_gen_mov_tl(cpu_npc, cpu_dst); dc->npc = DYNAMIC_PC; goto jmp_insn; @@ -3877,7 +3960,8 @@ static void disas_sparc_insn(DisasContext * dc) { gen_movl_TN_reg(rd, tcg_const_tl(dc->pc)); gen_mov_pc_npc(dc, cpu_cond); - tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3)); + tcg_gen_helper_0_2(helper_check_align, cpu_dst, + tcg_const_i32(3)); tcg_gen_mov_tl(cpu_npc, cpu_dst); dc->npc = DYNAMIC_PC; } @@ -3888,7 +3972,8 @@ static void disas_sparc_insn(DisasContext * dc) if (!supervisor(dc)) goto priv_insn; gen_mov_pc_npc(dc, cpu_cond); - tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3)); + tcg_gen_helper_0_2(helper_check_align, cpu_dst, + tcg_const_i32(3)); tcg_gen_mov_tl(cpu_npc, cpu_dst); dc->npc = DYNAMIC_PC; tcg_gen_helper_0_0(helper_rett); @@ -4006,9 +4091,11 @@ static void disas_sparc_insn(DisasContext * dc) case 0xd: /* ldstub -- XXX: should be atomically */ ABI32_MASK(cpu_addr); tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); - tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr, dc->mem_idx); + tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr, + dc->mem_idx); break; - case 0x0f: /* swap register with memory. Also atomically */ + case 0x0f: /* swap register with memory. Also + atomically */ CHECK_IU_FEATURE(dc, SWAP); gen_movl_reg_TN(rd, cpu_val); ABI32_MASK(cpu_addr); @@ -4090,7 +4177,8 @@ static void disas_sparc_insn(DisasContext * dc) save_state(dc, cpu_cond); gen_ldstub_asi(cpu_val, cpu_addr, insn); break; - case 0x1f: /* swap reg with alt. memory. Also atomically */ + case 0x1f: /* swap reg with alt. memory. Also + atomically */ CHECK_IU_FEATURE(dc, SWAP); #ifndef TARGET_SPARC64 if (IS_IMM) @@ -4581,7 +4669,8 @@ void gen_intermediate_code_init(CPUSPARCState *env) cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, offsetof(CPUState, t1), "T1"); cpu_cond = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, cond), "cond"); + TCG_AREG0, offsetof(CPUState, cond), + "cond"); cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, offsetof(CPUState, cc_src), "cc_src"); |