diff options
| -rw-r--r-- | cpu-all.h | 23 | ||||
| -rw-r--r-- | exec-all.h | 20 | ||||
| -rw-r--r-- | exec.c | 42 | ||||
| -rw-r--r-- | hw/ppc_prep.c | 32 | ||||
| -rw-r--r-- | hw/vga.c | 12 |
5 files changed, 67 insertions, 62 deletions
@@ -620,8 +620,8 @@ extern int code_copy_enabled; #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */ void cpu_interrupt(CPUState *s, int mask); -int cpu_breakpoint_insert(CPUState *env, uint32_t pc); -int cpu_breakpoint_remove(CPUState *env, uint32_t pc); +int cpu_breakpoint_insert(CPUState *env, target_ulong pc); +int cpu_breakpoint_remove(CPUState *env, target_ulong pc); void cpu_single_step(CPUState *env, int enabled); /* Return the physical page corresponding to a virtual one. Use it @@ -681,24 +681,25 @@ extern uint8_t *phys_ram_dirty; #define IO_MEM_CODE (3 << IO_MEM_SHIFT) /* used internally, never use directly */ #define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */ -typedef void CPUWriteMemoryFunc(uint32_t addr, uint32_t value); -typedef uint32_t CPUReadMemoryFunc(uint32_t addr); +typedef void CPUWriteMemoryFunc(target_phys_addr_t addr, uint32_t value); +typedef uint32_t CPUReadMemoryFunc(target_phys_addr_t addr); -void cpu_register_physical_memory(unsigned long start_addr, unsigned long size, - long phys_offset); +void cpu_register_physical_memory(target_phys_addr_t start_addr, + unsigned long size, + unsigned long phys_offset); int cpu_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write); -void cpu_physical_memory_rw(target_ulong addr, uint8_t *buf, +void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, int len, int is_write); -static inline void cpu_physical_memory_read(target_ulong addr, uint8_t *buf, - int len) +static inline void cpu_physical_memory_read(target_phys_addr_t addr, + uint8_t *buf, int len) { cpu_physical_memory_rw(addr, buf, len, 0); } -static inline void cpu_physical_memory_write(target_ulong addr, const uint8_t *buf, - int len) +static inline void cpu_physical_memory_write(target_phys_addr_t addr, + const uint8_t *buf, int len) { cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1); } diff --git a/exec-all.h b/exec-all.h index 934808f10c..20c7d3ba35 100644 --- a/exec-all.h +++ b/exec-all.h @@ -86,13 +86,16 @@ int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, int cpu_restore_state_copy(struct TranslationBlock *tb, CPUState *env, unsigned long searched_pc, void *puc); +void cpu_resume_from_signal(CPUState *env1, void *puc); void cpu_exec_init(void); -int page_unprotect(unsigned long address); +int page_unprotect(unsigned long address, unsigned long pc, void *puc); +void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, + int is_cpu_write_access); void tb_invalidate_page_range(target_ulong start, target_ulong end); -void tlb_flush_page(CPUState *env, uint32_t addr); -void tlb_flush_page_write(CPUState *env, uint32_t addr); +void tlb_flush_page(CPUState *env, target_ulong addr); void tlb_flush(CPUState *env, int flush_global); -int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot, +int tlb_set_page(CPUState *env, target_ulong vaddr, + target_phys_addr_t paddr, int prot, int is_user, int is_softmmu); #define CODE_GEN_MAX_SIZE 65536 @@ -146,8 +149,8 @@ int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot, #endif typedef struct TranslationBlock { - unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */ - unsigned long cs_base; /* CS base for this block */ + target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ + target_ulong cs_base; /* CS base for this block */ unsigned int flags; /* flags defining in which context the code was generated */ uint16_t size; /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */ @@ -155,6 +158,7 @@ typedef struct TranslationBlock { #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ +#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ uint8_t *tc_ptr; /* pointer to the translated code */ struct TranslationBlock *hash_next; /* next matching tb for virtual address */ @@ -206,8 +210,8 @@ extern uint8_t *code_gen_ptr; /* find a translation block in the translation cache. If not found, return NULL and the pointer to the last element of the list in pptb */ static inline TranslationBlock *tb_find(TranslationBlock ***pptb, - unsigned long pc, - unsigned long cs_base, + target_ulong pc, + target_ulong cs_base, unsigned int flags) { TranslationBlock **ptb, *tb; @@ -64,7 +64,7 @@ uint8_t *phys_ram_base; uint8_t *phys_ram_dirty; typedef struct PageDesc { - /* offset in memory of the page + io_index in the low 12 bits */ + /* offset in host memory of the page + io_index in the low 12 bits */ unsigned long phys_offset; /* list of TBs intersecting this physical page */ TranslationBlock *first_tb; @@ -1011,7 +1011,7 @@ static void breakpoint_invalidate(CPUState *env, target_ulong pc) /* add a breakpoint. EXCP_DEBUG is returned by the CPU loop if a breakpoint is reached */ -int cpu_breakpoint_insert(CPUState *env, uint32_t pc) +int cpu_breakpoint_insert(CPUState *env, target_ulong pc) { #if defined(TARGET_I386) || defined(TARGET_PPC) int i; @@ -1033,7 +1033,7 @@ int cpu_breakpoint_insert(CPUState *env, uint32_t pc) } /* remove a breakpoint */ -int cpu_breakpoint_remove(CPUState *env, uint32_t pc) +int cpu_breakpoint_remove(CPUState *env, target_ulong pc) { #if defined(TARGET_I386) || defined(TARGET_PPC) int i; @@ -1221,7 +1221,7 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, uint32_t addr) tlb_entry->address = -1; } -void tlb_flush_page(CPUState *env, uint32_t addr) +void tlb_flush_page(CPUState *env, target_ulong addr) { int i, n; VirtPageDesc *vp; @@ -1415,7 +1415,8 @@ static inline void tlb_set_dirty(unsigned long addr, target_ulong vaddr) is permitted. Return 0 if OK or 2 if the page could not be mapped (can only happen in non SOFTMMU mode for I/O pages or pages conflicting with the host address space). */ -int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot, +int tlb_set_page(CPUState *env, target_ulong vaddr, + target_phys_addr_t paddr, int prot, int is_user, int is_softmmu) { PageDesc *p; @@ -1583,15 +1584,12 @@ void tlb_flush(CPUState *env, int flush_global) { } -void tlb_flush_page(CPUState *env, uint32_t addr) +void tlb_flush_page(CPUState *env, target_ulong addr) { } -void tlb_flush_page_write(CPUState *env, uint32_t addr) -{ -} - -int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot, +int tlb_set_page(CPUState *env, target_ulong vaddr, + target_phys_addr_t paddr, int prot, int is_user, int is_softmmu) { return 0; @@ -1739,8 +1737,9 @@ static inline void tlb_set_dirty(unsigned long addr, target_ulong vaddr) /* register physical memory. 'size' must be a multiple of the target page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an io memory page */ -void cpu_register_physical_memory(unsigned long start_addr, unsigned long size, - long phys_offset) +void cpu_register_physical_memory(target_phys_addr_t start_addr, + unsigned long size, + unsigned long phys_offset) { unsigned long addr, end_addr; PageDesc *p; @@ -1754,12 +1753,12 @@ void cpu_register_physical_memory(unsigned long start_addr, unsigned long size, } } -static uint32_t unassigned_mem_readb(uint32_t addr) +static uint32_t unassigned_mem_readb(target_phys_addr_t addr) { return 0; } -static void unassigned_mem_writeb(uint32_t addr, uint32_t val) +static void unassigned_mem_writeb(target_phys_addr_t addr, uint32_t val) { } @@ -1778,7 +1777,7 @@ static CPUWriteMemoryFunc *unassigned_mem_write[3] = { /* self modifying code support in soft mmu mode : writing to a page containing code comes to these functions */ -static void code_mem_writeb(uint32_t addr, uint32_t val) +static void code_mem_writeb(target_phys_addr_t addr, uint32_t val) { unsigned long phys_addr; @@ -1790,7 +1789,7 @@ static void code_mem_writeb(uint32_t addr, uint32_t val) phys_ram_dirty[phys_addr >> TARGET_PAGE_BITS] = 1; } -static void code_mem_writew(uint32_t addr, uint32_t val) +static void code_mem_writew(target_phys_addr_t addr, uint32_t val) { unsigned long phys_addr; @@ -1802,7 +1801,7 @@ static void code_mem_writew(uint32_t addr, uint32_t val) phys_ram_dirty[phys_addr >> TARGET_PAGE_BITS] = 1; } -static void code_mem_writel(uint32_t addr, uint32_t val) +static void code_mem_writel(target_phys_addr_t addr, uint32_t val) { unsigned long phys_addr; @@ -1892,7 +1891,7 @@ int cpu_register_io_memory(int io_index, /* physical memory access (slow version, mainly for debug) */ #if defined(CONFIG_USER_ONLY) -void cpu_physical_memory_rw(target_ulong addr, uint8_t *buf, +void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, int len, int is_write) { int l, flags; @@ -1921,13 +1920,14 @@ void cpu_physical_memory_rw(target_ulong addr, uint8_t *buf, } } #else -void cpu_physical_memory_rw(target_ulong addr, uint8_t *buf, +void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, int len, int is_write) { int l, io_index; uint8_t *ptr; uint32_t val; - target_ulong page, pd; + target_phys_addr_t page; + unsigned long pd; PageDesc *p; while (len > 0) { diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index dd23691625..42ae22e865 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -104,7 +104,7 @@ static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; /* IO ports emulation */ #define PPC_IO_BASE 0x80000000 -static void PPC_io_writeb (uint32_t addr, uint32_t value, uint32_t vaddr) +static void PPC_io_writeb (target_phys_addr_t addr, uint32_t value) { /* Don't polute serial port output */ #if 0 @@ -121,7 +121,7 @@ static void PPC_io_writeb (uint32_t addr, uint32_t value, uint32_t vaddr) cpu_outb(NULL, addr - PPC_IO_BASE, value); } -static uint32_t PPC_io_readb (uint32_t addr) +static uint32_t PPC_io_readb (target_phys_addr_t addr) { uint32_t ret = cpu_inb(NULL, addr - PPC_IO_BASE); @@ -141,7 +141,7 @@ static uint32_t PPC_io_readb (uint32_t addr) return ret; } -static void PPC_io_writew (uint32_t addr, uint32_t value, uint32_t vaddr) +static void PPC_io_writew (target_phys_addr_t addr, uint32_t value) { if ((addr < 0x800001f0 || addr > 0x800001f7) && (addr < 0x80000170 || addr > 0x80000177)) { @@ -150,7 +150,7 @@ static void PPC_io_writew (uint32_t addr, uint32_t value, uint32_t vaddr) cpu_outw(NULL, addr - PPC_IO_BASE, value); } -static uint32_t PPC_io_readw (uint32_t addr) +static uint32_t PPC_io_readw (target_phys_addr_t addr) { uint32_t ret = cpu_inw(NULL, addr - PPC_IO_BASE); @@ -162,13 +162,13 @@ static uint32_t PPC_io_readw (uint32_t addr) return ret; } -static void PPC_io_writel (uint32_t addr, uint32_t value, uint32_t vaddr) +static void PPC_io_writel (target_phys_addr_t addr, uint32_t value) { PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, value); cpu_outl(NULL, addr - PPC_IO_BASE, value); } -static uint32_t PPC_io_readl (uint32_t addr) +static uint32_t PPC_io_readl (target_phys_addr_t addr) { uint32_t ret = cpu_inl(NULL, addr - PPC_IO_BASE); @@ -190,12 +190,12 @@ static CPUReadMemoryFunc *PPC_io_read[] = { }; /* Read-only register (?) */ -static void _PPC_ioB_write (uint32_t addr, uint32_t value, uint32_t vaddr) +static void _PPC_ioB_write (target_phys_addr_t addr, uint32_t value) { // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value); } -static uint32_t _PPC_ioB_read (uint32_t addr) +static uint32_t _PPC_ioB_read (target_phys_addr_t addr) { uint32_t retval = 0; @@ -636,9 +636,9 @@ static void VGA_printf (uint8_t *s) for (i = 0; i < format_width; i++) { nibble = (arg >> (4 * digit)) & 0x000f; if (nibble <= 9) - PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + '0', 0); + PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + '0'); else - PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + 'A', 0); + PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + 'A'); digit--; } in_format = 0; @@ -647,7 +647,7 @@ static void VGA_printf (uint8_t *s) // in_format = 0; // } } else { - PPC_io_writeb(PPC_IO_BASE + 0x500, c, 0); + PPC_io_writeb(PPC_IO_BASE + 0x500, c); } s++; } @@ -659,10 +659,10 @@ static void VGA_init (void) printf("Init VGA...\n"); #if 1 /* switch to color mode and enable CPU access 480 lines */ - PPC_io_writeb(PPC_IO_BASE + 0x3C2, 0xC3, 0); + PPC_io_writeb(PPC_IO_BASE + 0x3C2, 0xC3); /* more than 64k 3C4/04 */ - PPC_io_writeb(PPC_IO_BASE + 0x3C4, 0x04, 0); - PPC_io_writeb(PPC_IO_BASE + 0x3C5, 0x02, 0); + PPC_io_writeb(PPC_IO_BASE + 0x3C4, 0x04); + PPC_io_writeb(PPC_IO_BASE + 0x3C5, 0x02); #endif VGA_printf("PPC VGA BIOS...\n"); } @@ -690,7 +690,7 @@ void PPC_init_hw (/*CPUPPCState *env,*/ uint32_t mem_size, { #if 1 uint32_t offset = - *((uint32_t *)((uint32_t)phys_ram_base + kernel_addr)); + *((uint32_t *)(phys_ram_base + kernel_addr)); #else uint32_t offset = 12; #endif @@ -816,7 +816,7 @@ void PPC_init_hw (/*CPUPPCState *env,*/ uint32_t mem_size, { #if 0 uint32_t offset = - *((uint32_t *)((uint32_t)phys_ram_base + kernel_addr)); + *((uint32_t *)(phys_ram_base + kernel_addr)); #else uint32_t offset = 12; #endif @@ -648,7 +648,7 @@ static void vbe_ioport_write(void *opaque, uint32_t addr, uint32_t val) #endif /* called for accesses between 0xa0000 and 0xc0000 */ -static uint32_t vga_mem_readb(uint32_t addr) +static uint32_t vga_mem_readb(target_phys_addr_t addr) { VGAState *s = &vga_state; int memory_map_mode, plane; @@ -704,7 +704,7 @@ static uint32_t vga_mem_readb(uint32_t addr) return ret; } -static uint32_t vga_mem_readw(uint32_t addr) +static uint32_t vga_mem_readw(target_phys_addr_t addr) { uint32_t v; v = vga_mem_readb(addr); @@ -712,7 +712,7 @@ static uint32_t vga_mem_readw(uint32_t addr) return v; } -static uint32_t vga_mem_readl(uint32_t addr) +static uint32_t vga_mem_readl(target_phys_addr_t addr) { uint32_t v; v = vga_mem_readb(addr); @@ -723,7 +723,7 @@ static uint32_t vga_mem_readl(uint32_t addr) } /* called for accesses between 0xa0000 and 0xc0000 */ -static void vga_mem_writeb(uint32_t addr, uint32_t val) +static void vga_mem_writeb(target_phys_addr_t addr, uint32_t val) { VGAState *s = &vga_state; int memory_map_mode, plane, write_mode, b, func_select; @@ -851,13 +851,13 @@ static void vga_mem_writeb(uint32_t addr, uint32_t val) } } -static void vga_mem_writew(uint32_t addr, uint32_t val) +static void vga_mem_writew(target_phys_addr_t addr, uint32_t val) { vga_mem_writeb(addr, val & 0xff); vga_mem_writeb(addr + 1, (val >> 8) & 0xff); } -static void vga_mem_writel(uint32_t addr, uint32_t val) +static void vga_mem_writel(target_phys_addr_t addr, uint32_t val) { vga_mem_writeb(addr, val & 0xff); vga_mem_writeb(addr + 1, (val >> 8) & 0xff); |