diff options
| -rw-r--r-- | hw/microblaze_boot.c | 8 | ||||
| -rw-r--r-- | hw/microblaze_boot.h | 4 | ||||
| -rw-r--r-- | hw/microblaze_pic_cpu.c | 4 | ||||
| -rw-r--r-- | hw/microblaze_pic_cpu.h | 2 | ||||
| -rw-r--r-- | hw/petalogix_ml605_mmu.c | 4 | ||||
| -rw-r--r-- | hw/petalogix_s3adsp1800_mmu.c | 4 |
6 files changed, 13 insertions, 13 deletions
diff --git a/hw/microblaze_boot.c b/hw/microblaze_boot.c index 7ce04dcd63..b4fbb10dd0 100644 --- a/hw/microblaze_boot.c +++ b/hw/microblaze_boot.c @@ -35,7 +35,7 @@ static struct { - void (*machine_cpu_reset)(CPUState *); + void (*machine_cpu_reset)(CPUMBState *); uint32_t bootstrap_pc; uint32_t cmdline; uint32_t fdt; @@ -43,7 +43,7 @@ static struct static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUMBState *env = opaque; cpu_state_reset(env); env->regs[5] = boot_info.cmdline; @@ -99,9 +99,9 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) return addr - 0x30000000LL; } -void microblaze_load_kernel(CPUState *env, target_phys_addr_t ddr_base, +void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base, uint32_t ramsize, const char *dtb_filename, - void (*machine_cpu_reset)(CPUState *)) + void (*machine_cpu_reset)(CPUMBState *)) { QemuOpts *machine_opts; diff --git a/hw/microblaze_boot.h b/hw/microblaze_boot.h index 69d4ac635b..bf9d136f12 100644 --- a/hw/microblaze_boot.h +++ b/hw/microblaze_boot.h @@ -3,8 +3,8 @@ #include "hw.h" -void microblaze_load_kernel(CPUState *env, target_phys_addr_t ddr_base, +void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base, uint32_t ramsize, const char *dtb_filename, - void (*machine_cpu_reset)(CPUState *)); + void (*machine_cpu_reset)(CPUMBState *)); #endif /* __MICROBLAZE_BOOT __ */ diff --git a/hw/microblaze_pic_cpu.c b/hw/microblaze_pic_cpu.c index 8b5623ce28..ff36a526fc 100644 --- a/hw/microblaze_pic_cpu.c +++ b/hw/microblaze_pic_cpu.c @@ -29,7 +29,7 @@ static void microblaze_pic_cpu_handler(void *opaque, int irq, int level) { - CPUState *env = (CPUState *)opaque; + CPUMBState *env = (CPUMBState *)opaque; int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; if (level) @@ -38,7 +38,7 @@ static void microblaze_pic_cpu_handler(void *opaque, int irq, int level) cpu_reset_interrupt(env, type); } -qemu_irq *microblaze_pic_init_cpu(CPUState *env) +qemu_irq *microblaze_pic_init_cpu(CPUMBState *env) { return qemu_allocate_irqs(microblaze_pic_cpu_handler, env, 2); } diff --git a/hw/microblaze_pic_cpu.h b/hw/microblaze_pic_cpu.h index 4c76275976..43090a48ef 100644 --- a/hw/microblaze_pic_cpu.h +++ b/hw/microblaze_pic_cpu.h @@ -3,6 +3,6 @@ #include "qemu-common.h" -qemu_irq *microblaze_pic_init_cpu(CPUState *env); +qemu_irq *microblaze_pic_init_cpu(CPUMBState *env); #endif /* MICROBLAZE_PIC_CPU_H */ diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c index c87fa1186c..31a434872d 100644 --- a/hw/petalogix_ml605_mmu.c +++ b/hw/petalogix_ml605_mmu.c @@ -54,7 +54,7 @@ #define AXIENET_BASEADDR 0x82780000 #define AXIDMA_BASEADDR 0x84600000 -static void machine_cpu_reset(CPUState *env) +static void machine_cpu_reset(CPUMBState *env) { env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ /* setup pvr to match kernel setting */ @@ -75,7 +75,7 @@ petalogix_ml605_init(ram_addr_t ram_size, { MemoryRegion *address_space_mem = get_system_memory(); DeviceState *dev; - CPUState *env; + CPUMBState *env; DriveInfo *dinfo; int i; target_phys_addr_t ddr_base = MEMORY_BASEADDR; diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c index 2cb0b1f10a..ff154c7aa9 100644 --- a/hw/petalogix_s3adsp1800_mmu.c +++ b/hw/petalogix_s3adsp1800_mmu.c @@ -49,7 +49,7 @@ #define UARTLITE_BASEADDR 0x84000000 #define ETHLITE_BASEADDR 0x81000000 -static void machine_cpu_reset(CPUState *env) +static void machine_cpu_reset(CPUMBState *env) { /* FIXME: move to machine specfic cpu reset */ env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */ @@ -63,7 +63,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { DeviceState *dev; - CPUState *env; + CPUMBState *env; DriveInfo *dinfo; int i; target_phys_addr_t ddr_base = MEMORY_BASEADDR; |