diff options
| -rw-r--r-- | cpu-exec.c | 6 | ||||
| -rw-r--r-- | target-sparc/cpu.h | 2 | ||||
| -rw-r--r-- | target-sparc/helper.c | 2 | ||||
| -rw-r--r-- | target-sparc/op_helper.c | 4 | ||||
| -rw-r--r-- | target-sparc/translate.c | 11 |
5 files changed, 15 insertions, 10 deletions
diff --git a/cpu-exec.c b/cpu-exec.c index 0f55229741..3bfa0bc1f2 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -181,10 +181,8 @@ static inline TranslationBlock *tb_find_fast(void) flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); #else - // FPU enable . MMU Boot . MMU enabled . MMU no-fault . Supervisor - flags = (env->psref << 4) | (((env->mmuregs[0] & MMU_BM) >> 14) << 3) - | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1) - | env->psrs; + // FPU enable . Supervisor + flags = (env->psref << 4) | env->psrs; #endif cs_base = env->npc; pc = env->pc; diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 51cbd4c328..0e5a4e2227 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -147,7 +147,6 @@ /* MMU */ #define MMU_E (1<<0) #define MMU_NF (1<<1) -#define MMU_BM (1<<14) #define PTE_ENTRYTYPE_MASK 3 #define PTE_ACCESS_MASK 0x1c @@ -200,6 +199,7 @@ typedef struct CPUSPARCState { int interrupt_index; int interrupt_request; int halted; + uint32_t mmu_bm; /* NOTE: we allow 8 more registers to handle wrapping */ target_ulong regbase[NWINDOWS * 16 + 8]; diff --git a/target-sparc/helper.c b/target-sparc/helper.c index ebe642f8cb..3ddda872ef 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -114,7 +114,7 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ // Boot mode: instruction fetches are taken from PROM - if (rw == 2 && (env->mmuregs[0] & MMU_BM)) { + if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) { *physical = 0xff0000000ULL | (address & 0x3ffffULL); *prot = PAGE_READ | PAGE_EXEC; return 0; diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 3746788796..13c16618fd 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -493,8 +493,8 @@ void helper_st_asi(int asi, int size) oldreg = env->mmuregs[reg]; switch(reg) { case 0: - env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM); - env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM); + env->mmuregs[reg] &= ~(MMU_E | MMU_NF | env->mmu_bm); + env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | env->mmu_bm); // Mappings generated during no-fault mode or MMU // disabled mode are invalid in normal mode if (oldreg != env->mmuregs[reg]) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index cd60c114cd..cc8402cada 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -59,6 +59,7 @@ struct sparc_def_t { target_ulong iu_version; uint32_t fpu_version; uint32_t mmu_version; + uint32_t mmu_bm; }; static uint16_t *gen_opc_ptr; @@ -3482,7 +3483,7 @@ void cpu_reset(CPUSPARCState *env) #else env->pc = 0; env->mmuregs[0] &= ~(MMU_E | MMU_NF); - env->mmuregs[0] |= MMU_BM; + env->mmuregs[0] |= env->mmu_bm; #endif env->npc = env->pc + 4; #endif @@ -3496,7 +3497,6 @@ CPUSPARCState *cpu_sparc_init(void) if (!env) return NULL; cpu_exec_init(env); - cpu_reset(env); return (env); } @@ -3515,30 +3515,35 @@ static const sparc_def_t sparc_defs[] = { .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ + .mmu_bm = 0x00004000, }, { .name = "Fujitsu MB86907", .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ + .mmu_bm = 0x00004000, }, { .name = "TI MicroSparc I", .iu_version = 0x41000000, .fpu_version = 4 << 17, .mmu_version = 0x41000000, + .mmu_bm = 0x00004000, }, { .name = "TI SuperSparc II", .iu_version = 0x40000000, .fpu_version = 0 << 17, .mmu_version = 0x04000000, + .mmu_bm = 0x00002000, }, { .name = "Ross RT620", .iu_version = 0x1e000000, .fpu_version = 1 << 17, .mmu_version = 0x17000000, + .mmu_bm = 0x00004000, }, #endif }; @@ -3579,9 +3584,11 @@ int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def, unsigned int env->version = def->iu_version; env->fsr = def->fpu_version; #if !defined(TARGET_SPARC64) + env->mmu_bm = def->mmu_bm; env->mmuregs[0] |= def->mmu_version; env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; #endif + cpu_reset(env); return 0; } |