diff options
123 files changed, 4362 insertions, 2256 deletions
diff --git a/Makefile.objs b/Makefile.objs index 23445b15bf..9e2077833e 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -82,7 +82,7 @@ common-obj-$(CONFIG_WIN32) += os-win32.o common-obj-$(CONFIG_POSIX) += os-posix.o common-obj-y += tcg-runtime.o host-utils.o -common-obj-y += irq.o ioport.o input.o +common-obj-y += irq.o input.o common-obj-$(CONFIG_PTIMER) += ptimer.o common-obj-$(CONFIG_MAX7310) += max7310.o common-obj-$(CONFIG_WM8750) += wm8750.o @@ -220,6 +220,7 @@ hw-obj-$(CONFIG_APPLESMC) += applesmc.o hw-obj-$(CONFIG_SMARTCARD) += usb-ccid.o ccid-card-passthru.o hw-obj-$(CONFIG_SMARTCARD_NSS) += ccid-card-emulated.o hw-obj-$(CONFIG_USB_REDIR) += usb-redir.o +hw-obj-$(CONFIG_I8259) += i8259.o # PPC devices hw-obj-$(CONFIG_PREP_PCI) += prep_pci.o @@ -258,6 +259,7 @@ hw-obj-$(CONFIG_RTL8139_PCI) += rtl8139.o hw-obj-$(CONFIG_SMC91C111) += smc91c111.o hw-obj-$(CONFIG_LAN9118) += lan9118.o hw-obj-$(CONFIG_NE2000_ISA) += ne2000-isa.o +hw-obj-$(CONFIG_OPENCORES_ETH) += opencores_eth.o # IDE hw-obj-$(CONFIG_IDE_CORE) += ide/core.o ide/atapi.o diff --git a/Makefile.target b/Makefile.target index 42adfecc35..417f23e00e 100644 --- a/Makefile.target +++ b/Makefile.target @@ -183,7 +183,7 @@ endif #CONFIG_BSD_USER # System emulator target ifdef CONFIG_SOFTMMU -obj-y = arch_init.o cpus.o monitor.o machine.o gdbstub.o balloon.o +obj-y = arch_init.o cpus.o monitor.o machine.o gdbstub.o balloon.o ioport.o # virtio has to be here due to weird dependency between PCI and virtio-net. # need to fix this properly obj-$(CONFIG_NO_PCI) += pci-stub.o @@ -219,7 +219,7 @@ obj-$(CONFIG_IVSHMEM) += ivshmem.o # Hardware support obj-i386-y += vga.o -obj-i386-y += mc146818rtc.o i8259.o pc.o +obj-i386-y += mc146818rtc.o pc.o obj-i386-y += cirrus_vga.o sga.o apic.o ioapic.o piix_pci.o obj-i386-y += vmport.o obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o wdt_ib700.o @@ -232,7 +232,7 @@ obj-i386-$(CONFIG_SPICE) += qxl.o qxl-logger.o qxl-render.o obj-ppc-y = ppc.o ppc_booke.o obj-ppc-y += vga.o # PREP target -obj-ppc-y += i8259.o mc146818rtc.o +obj-ppc-y += mc146818rtc.o obj-ppc-y += ppc_prep.o # OldWorld PowerMac obj-ppc-y += ppc_oldworld.o @@ -283,7 +283,7 @@ obj-lm32-y += framebuffer.o obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o obj-mips-y += mips_addr.o mips_timer.o mips_int.o -obj-mips-y += vga.o i8259.o +obj-mips-y += vga.o obj-mips-y += jazz_led.o obj-mips-y += gt64xxx.o mc146818rtc.o obj-mips-y += cirrus_vga.o @@ -365,14 +365,16 @@ obj-m68k-y += m68k-semi.o dummy_m68k.o obj-s390x-y = s390-virtio-bus.o s390-virtio.o -obj-alpha-y = i8259.o mc146818rtc.o +obj-alpha-y = mc146818rtc.o obj-alpha-y += vga.o cirrus_vga.o obj-alpha-y += alpha_pci.o alpha_dp264.o alpha_typhoon.o obj-xtensa-y += xtensa_pic.o -obj-xtensa-y += xtensa_sample.o -obj-xtensa-y += xtensa_dc232b.o +obj-xtensa-y += xtensa_sim.o +obj-xtensa-y += xtensa_lx60.o obj-xtensa-y += xtensa-semi.o +obj-xtensa-y += core-dc232b.o +obj-xtensa-y += core-fsf.o main.o: QEMU_CFLAGS+=$(GPROF_CFLAGS) @@ -44,6 +44,8 @@ #include <windows.h> #endif +#define NOT_DONE 0x7fffffff /* used while emulated sync operation in progress */ + static void bdrv_dev_change_media_cb(BlockDriverState *bs, bool load); static BlockDriverAIOCB *bdrv_aio_readv_em(BlockDriverState *bs, int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, @@ -55,16 +57,6 @@ static BlockDriverAIOCB *bdrv_aio_flush_em(BlockDriverState *bs, BlockDriverCompletionFunc *cb, void *opaque); static BlockDriverAIOCB *bdrv_aio_noop_em(BlockDriverState *bs, BlockDriverCompletionFunc *cb, void *opaque); -static int bdrv_read_em(BlockDriverState *bs, int64_t sector_num, - uint8_t *buf, int nb_sectors); -static int bdrv_write_em(BlockDriverState *bs, int64_t sector_num, - const uint8_t *buf, int nb_sectors); -static BlockDriverAIOCB *bdrv_co_aio_readv_em(BlockDriverState *bs, - int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, - BlockDriverCompletionFunc *cb, void *opaque); -static BlockDriverAIOCB *bdrv_co_aio_writev_em(BlockDriverState *bs, - int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, - BlockDriverCompletionFunc *cb, void *opaque); static int coroutine_fn bdrv_co_readv_em(BlockDriverState *bs, int64_t sector_num, int nb_sectors, QEMUIOVector *iov); @@ -72,6 +64,18 @@ static int coroutine_fn bdrv_co_writev_em(BlockDriverState *bs, int64_t sector_num, int nb_sectors, QEMUIOVector *iov); static int coroutine_fn bdrv_co_flush_em(BlockDriverState *bs); +static int coroutine_fn bdrv_co_do_readv(BlockDriverState *bs, + int64_t sector_num, int nb_sectors, QEMUIOVector *qiov); +static int coroutine_fn bdrv_co_do_writev(BlockDriverState *bs, + int64_t sector_num, int nb_sectors, QEMUIOVector *qiov); +static BlockDriverAIOCB *bdrv_co_aio_rw_vector(BlockDriverState *bs, + int64_t sector_num, + QEMUIOVector *qiov, + int nb_sectors, + BlockDriverCompletionFunc *cb, + void *opaque, + bool is_write); +static void coroutine_fn bdrv_co_do_rw(void *opaque); static QTAILQ_HEAD(, BlockDriverState) bdrv_states = QTAILQ_HEAD_INITIALIZER(bdrv_states); @@ -184,24 +188,18 @@ void path_combine(char *dest, int dest_size, void bdrv_register(BlockDriver *bdrv) { - if (bdrv->bdrv_co_readv) { - /* Emulate AIO by coroutines, and sync by AIO */ - bdrv->bdrv_aio_readv = bdrv_co_aio_readv_em; - bdrv->bdrv_aio_writev = bdrv_co_aio_writev_em; - bdrv->bdrv_read = bdrv_read_em; - bdrv->bdrv_write = bdrv_write_em; - } else { + /* Block drivers without coroutine functions need emulation */ + if (!bdrv->bdrv_co_readv) { bdrv->bdrv_co_readv = bdrv_co_readv_em; bdrv->bdrv_co_writev = bdrv_co_writev_em; + /* bdrv_co_readv_em()/brdv_co_writev_em() work in terms of aio, so if + * the block driver lacks aio we need to emulate that too. + */ if (!bdrv->bdrv_aio_readv) { /* add AIO emulation layer */ bdrv->bdrv_aio_readv = bdrv_aio_readv_em; bdrv->bdrv_aio_writev = bdrv_aio_writev_em; - } else if (!bdrv->bdrv_read) { - /* add synchronous IO emulation layer */ - bdrv->bdrv_read = bdrv_read_em; - bdrv->bdrv_write = bdrv_write_em; } } @@ -221,6 +219,7 @@ BlockDriverState *bdrv_new(const char *device_name) if (device_name[0] != '\0') { QTAILQ_INSERT_TAIL(&bdrv_states, bs, list); } + bdrv_iostatus_disable(bs); return bs; } @@ -772,6 +771,7 @@ int bdrv_attach_dev(BlockDriverState *bs, void *dev) return -EBUSY; } bs->dev = dev; + bdrv_iostatus_reset(bs); return 0; } @@ -1027,41 +1027,74 @@ static int bdrv_check_request(BlockDriverState *bs, int64_t sector_num, nb_sectors * BDRV_SECTOR_SIZE); } -static inline bool bdrv_has_async_rw(BlockDriver *drv) -{ - return drv->bdrv_co_readv != bdrv_co_readv_em - || drv->bdrv_aio_readv != bdrv_aio_readv_em; -} - static inline bool bdrv_has_async_flush(BlockDriver *drv) { return drv->bdrv_aio_flush != bdrv_aio_flush_em; } -/* return < 0 if error. See bdrv_write() for the return codes */ -int bdrv_read(BlockDriverState *bs, int64_t sector_num, - uint8_t *buf, int nb_sectors) +typedef struct RwCo { + BlockDriverState *bs; + int64_t sector_num; + int nb_sectors; + QEMUIOVector *qiov; + bool is_write; + int ret; +} RwCo; + +static void coroutine_fn bdrv_rw_co_entry(void *opaque) { - BlockDriver *drv = bs->drv; + RwCo *rwco = opaque; - if (!drv) - return -ENOMEDIUM; + if (!rwco->is_write) { + rwco->ret = bdrv_co_do_readv(rwco->bs, rwco->sector_num, + rwco->nb_sectors, rwco->qiov); + } else { + rwco->ret = bdrv_co_do_writev(rwco->bs, rwco->sector_num, + rwco->nb_sectors, rwco->qiov); + } +} - if (bdrv_has_async_rw(drv) && qemu_in_coroutine()) { - QEMUIOVector qiov; - struct iovec iov = { - .iov_base = (void *)buf, - .iov_len = nb_sectors * BDRV_SECTOR_SIZE, - }; +/* + * Process a synchronous request using coroutines + */ +static int bdrv_rw_co(BlockDriverState *bs, int64_t sector_num, uint8_t *buf, + int nb_sectors, bool is_write) +{ + QEMUIOVector qiov; + struct iovec iov = { + .iov_base = (void *)buf, + .iov_len = nb_sectors * BDRV_SECTOR_SIZE, + }; + Coroutine *co; + RwCo rwco = { + .bs = bs, + .sector_num = sector_num, + .nb_sectors = nb_sectors, + .qiov = &qiov, + .is_write = is_write, + .ret = NOT_DONE, + }; - qemu_iovec_init_external(&qiov, &iov, 1); - return bdrv_co_readv(bs, sector_num, nb_sectors, &qiov); - } + qemu_iovec_init_external(&qiov, &iov, 1); - if (bdrv_check_request(bs, sector_num, nb_sectors)) - return -EIO; + if (qemu_in_coroutine()) { + /* Fast-path if already in coroutine context */ + bdrv_rw_co_entry(&rwco); + } else { + co = qemu_coroutine_create(bdrv_rw_co_entry); + qemu_coroutine_enter(co, &rwco); + while (rwco.ret == NOT_DONE) { + qemu_aio_wait(); + } + } + return rwco.ret; +} - return drv->bdrv_read(bs, sector_num, buf, nb_sectors); +/* return < 0 if error. See bdrv_write() for the return codes */ +int bdrv_read(BlockDriverState *bs, int64_t sector_num, + uint8_t *buf, int nb_sectors) +{ + return bdrv_rw_co(bs, sector_num, buf, nb_sectors, false); } static void set_dirty_bitmap(BlockDriverState *bs, int64_t sector_num, @@ -1101,36 +1134,7 @@ static void set_dirty_bitmap(BlockDriverState *bs, int64_t sector_num, int bdrv_write(BlockDriverState *bs, int64_t sector_num, const uint8_t *buf, int nb_sectors) { - BlockDriver *drv = bs->drv; - - if (!bs->drv) - return -ENOMEDIUM; - - if (bdrv_has_async_rw(drv) && qemu_in_coroutine()) { - QEMUIOVector qiov; - struct iovec iov = { - .iov_base = (void *)buf, - .iov_len = nb_sectors * BDRV_SECTOR_SIZE, - }; - - qemu_iovec_init_external(&qiov, &iov, 1); - return bdrv_co_writev(bs, sector_num, nb_sectors, &qiov); - } - - if (bs->read_only) - return -EACCES; - if (bdrv_check_request(bs, sector_num, nb_sectors)) - return -EIO; - - if (bs->dirty_bitmap) { - set_dirty_bitmap(bs, sector_num, nb_sectors, 1); - } - - if (bs->wr_highest_sector < sector_num + nb_sectors - 1) { - bs->wr_highest_sector = sector_num + nb_sectors - 1; - } - - return drv->bdrv_write(bs, sector_num, buf, nb_sectors); + return bdrv_rw_co(bs, sector_num, (uint8_t *)buf, nb_sectors, true); } int bdrv_pread(BlockDriverState *bs, int64_t offset, @@ -1251,13 +1255,14 @@ int bdrv_pwrite_sync(BlockDriverState *bs, int64_t offset, return 0; } -int coroutine_fn bdrv_co_readv(BlockDriverState *bs, int64_t sector_num, - int nb_sectors, QEMUIOVector *qiov) +/* + * Handle a read request in coroutine context + */ +static int coroutine_fn bdrv_co_do_readv(BlockDriverState *bs, + int64_t sector_num, int nb_sectors, QEMUIOVector *qiov) { BlockDriver *drv = bs->drv; - trace_bdrv_co_readv(bs, sector_num, nb_sectors); - if (!drv) { return -ENOMEDIUM; } @@ -1268,12 +1273,22 @@ int coroutine_fn bdrv_co_readv(BlockDriverState *bs, int64_t sector_num, return drv->bdrv_co_readv(bs, sector_num, nb_sectors, qiov); } -int coroutine_fn bdrv_co_writev(BlockDriverState *bs, int64_t sector_num, +int coroutine_fn bdrv_co_readv(BlockDriverState *bs, int64_t sector_num, int nb_sectors, QEMUIOVector *qiov) { - BlockDriver *drv = bs->drv; + trace_bdrv_co_readv(bs, sector_num, nb_sectors); - trace_bdrv_co_writev(bs, sector_num, nb_sectors); + return bdrv_co_do_readv(bs, sector_num, nb_sectors, qiov); +} + +/* + * Handle a write request in coroutine context + */ +static int coroutine_fn bdrv_co_do_writev(BlockDriverState *bs, + int64_t sector_num, int nb_sectors, QEMUIOVector *qiov) +{ + BlockDriver *drv = bs->drv; + int ret; if (!bs->drv) { return -ENOMEDIUM; @@ -1285,6 +1300,8 @@ int coroutine_fn bdrv_co_writev(BlockDriverState *bs, int64_t sector_num, return -EIO; } + ret = drv->bdrv_co_writev(bs, sector_num, nb_sectors, qiov); + if (bs->dirty_bitmap) { set_dirty_bitmap(bs, sector_num, nb_sectors, 1); } @@ -1293,7 +1310,15 @@ int coroutine_fn bdrv_co_writev(BlockDriverState *bs, int64_t sector_num, bs->wr_highest_sector = sector_num + nb_sectors - 1; } - return drv->bdrv_co_writev(bs, sector_num, nb_sectors, qiov); + return ret; +} + +int coroutine_fn bdrv_co_writev(BlockDriverState *bs, int64_t sector_num, + int nb_sectors, QEMUIOVector *qiov) +{ + trace_bdrv_co_writev(bs, sector_num, nb_sectors); + + return bdrv_co_do_writev(bs, sector_num, nb_sectors, qiov); } /** @@ -1866,6 +1891,11 @@ static void bdrv_print_dict(QObject *obj, void *opaque) monitor_printf(mon, " tray-open=%d", qdict_get_bool(bs_dict, "tray-open")); } + + if (qdict_haskey(bs_dict, "io-status")) { + monitor_printf(mon, " io-status=%s", qdict_get_str(bs_dict, "io-status")); + } + if (qdict_haskey(bs_dict, "inserted")) { QDict *qdict = qobject_to_qdict(qdict_get(bs_dict, "inserted")); @@ -1891,6 +1921,12 @@ void bdrv_info_print(Monitor *mon, const QObject *data) qlist_iter(qobject_to_qlist(data), bdrv_print_dict, mon); } +static const char *const io_status_name[BDRV_IOS_MAX] = { + [BDRV_IOS_OK] = "ok", + [BDRV_IOS_FAILED] = "failed", + [BDRV_IOS_ENOSPC] = "nospace", +}; + void bdrv_info(Monitor *mon, QObject **ret_data) { QList *bs_list; @@ -1913,6 +1949,12 @@ void bdrv_info(Monitor *mon, QObject **ret_data) qdict_put(bs_dict, "tray-open", qbool_from_int(bdrv_dev_is_tray_open(bs))); } + + if (bdrv_iostatus_is_enabled(bs)) { + qdict_put(bs_dict, "io-status", + qstring_from_str(io_status_name[bs->iostatus])); + } + if (bs->drv) { QObject *obj; @@ -2314,89 +2356,20 @@ BlockDriverAIOCB *bdrv_aio_readv(BlockDriverState *bs, int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, BlockDriverCompletionFunc *cb, void *opaque) { - BlockDriver *drv = bs->drv; - trace_bdrv_aio_readv(bs, sector_num, nb_sectors, opaque); - if (!drv) - return NULL; - if (bdrv_check_request(bs, sector_num, nb_sectors)) - return NULL; - - return drv->bdrv_aio_readv(bs, sector_num, qiov, nb_sectors, - cb, opaque); -} - -typedef struct BlockCompleteData { - BlockDriverCompletionFunc *cb; - void *opaque; - BlockDriverState *bs; - int64_t sector_num; - int nb_sectors; -} BlockCompleteData; - -static void block_complete_cb(void *opaque, int ret) -{ - BlockCompleteData *b = opaque; - - if (b->bs->dirty_bitmap) { - set_dirty_bitmap(b->bs, b->sector_num, b->nb_sectors, 1); - } - b->cb(b->opaque, ret); - g_free(b); -} - -static BlockCompleteData *blk_dirty_cb_alloc(BlockDriverState *bs, - int64_t sector_num, - int nb_sectors, - BlockDriverCompletionFunc *cb, - void *opaque) -{ - BlockCompleteData *blkdata = g_malloc0(sizeof(BlockCompleteData)); - - blkdata->bs = bs; - blkdata->cb = cb; - blkdata->opaque = opaque; - blkdata->sector_num = sector_num; - blkdata->nb_sectors = nb_sectors; - - return blkdata; + return bdrv_co_aio_rw_vector(bs, sector_num, qiov, nb_sectors, + cb, opaque, false); } BlockDriverAIOCB *bdrv_aio_writev(BlockDriverState *bs, int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, BlockDriverCompletionFunc *cb, void *opaque) { - BlockDriver *drv = bs->drv; - BlockDriverAIOCB *ret; - BlockCompleteData *blk_cb_data; - trace_bdrv_aio_writev(bs, sector_num, nb_sectors, opaque); - if (!drv) - return NULL; - if (bs->read_only) - return NULL; - if (bdrv_check_request(bs, sector_num, nb_sectors)) - return NULL; - - if (bs->dirty_bitmap) { - blk_cb_data = blk_dirty_cb_alloc(bs, sector_num, nb_sectors, cb, - opaque); - cb = &block_complete_cb; - opaque = blk_cb_data; - } - - ret = drv->bdrv_aio_writev(bs, sector_num, qiov, nb_sectors, - cb, opaque); - - if (ret) { - if (bs->wr_highest_sector < sector_num + nb_sectors - 1) { - bs->wr_highest_sector = sector_num + nb_sectors - 1; - } - } - - return ret; + return bdrv_co_aio_rw_vector(bs, sector_num, qiov, nb_sectors, + cb, opaque, true); } @@ -2720,9 +2693,9 @@ static BlockDriverAIOCB *bdrv_aio_rw_vector(BlockDriverState *bs, if (is_write) { qemu_iovec_to_buffer(acb->qiov, acb->bounce); - acb->ret = bdrv_write(bs, sector_num, acb->bounce, nb_sectors); + acb->ret = bs->drv->bdrv_write(bs, sector_num, acb->bounce, nb_sectors); } else { - acb->ret = bdrv_read(bs, sector_num, acb->bounce, nb_sectors); + acb->ret = bs->drv->bdrv_read(bs, sector_num, acb->bounce, nb_sectors); } qemu_bh_schedule(acb->bh); @@ -2771,16 +2744,17 @@ static void bdrv_co_rw_bh(void *opaque) qemu_aio_release(acb); } -static void coroutine_fn bdrv_co_rw(void *opaque) +/* Invoke bdrv_co_do_readv/bdrv_co_do_writev */ +static void coroutine_fn bdrv_co_do_rw(void *opaque) { BlockDriverAIOCBCoroutine *acb = opaque; BlockDriverState *bs = acb->common.bs; if (!acb->is_write) { - acb->req.error = bs->drv->bdrv_co_readv(bs, acb->req.sector, + acb->req.error = bdrv_co_do_readv(bs, acb->req.sector, acb->req.nb_sectors, acb->req.qiov); } else { - acb->req.error = bs->drv->bdrv_co_writev(bs, acb->req.sector, + acb->req.error = bdrv_co_do_writev(bs, acb->req.sector, acb->req.nb_sectors, acb->req.qiov); } @@ -2805,28 +2779,12 @@ static BlockDriverAIOCB *bdrv_co_aio_rw_vector(BlockDriverState *bs, acb->req.qiov = qiov; acb->is_write = is_write; - co = qemu_coroutine_create(bdrv_co_rw); + co = qemu_coroutine_create(bdrv_co_do_rw); qemu_coroutine_enter(co, acb); return &acb->common; } -static BlockDriverAIOCB *bdrv_co_aio_readv_em(BlockDriverState *bs, - int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, - BlockDriverCompletionFunc *cb, void *opaque) -{ - return bdrv_co_aio_rw_vector(bs, sector_num, qiov, nb_sectors, cb, opaque, - false); -} - -static BlockDriverAIOCB *bdrv_co_aio_writev_em(BlockDriverState *bs, - int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, - BlockDriverCompletionFunc *cb, void *opaque) -{ - return bdrv_co_aio_rw_vector(bs, sector_num, qiov, nb_sectors, cb, opaque, - true); -} - static BlockDriverAIOCB *bdrv_aio_flush_em(BlockDriverState *bs, BlockDriverCompletionFunc *cb, void *opaque) { @@ -2865,70 +2823,6 @@ static BlockDriverAIOCB *bdrv_aio_noop_em(BlockDriverState *bs, return &acb->common; } -/**************************************************************/ -/* sync block device emulation */ - -static void bdrv_rw_em_cb(void *opaque, int ret) -{ - *(int *)opaque = ret; -} - -#define NOT_DONE 0x7fffffff - -static int bdrv_read_em(BlockDriverState *bs, int64_t sector_num, - uint8_t *buf, int nb_sectors) -{ - int async_ret; - BlockDriverAIOCB *acb; - struct iovec iov; - QEMUIOVector qiov; - - async_ret = NOT_DONE; - iov.iov_base = (void *)buf; - iov.iov_len = nb_sectors * BDRV_SECTOR_SIZE; - qemu_iovec_init_external(&qiov, &iov, 1); - acb = bdrv_aio_readv(bs, sector_num, &qiov, nb_sectors, - bdrv_rw_em_cb, &async_ret); - if (acb == NULL) { - async_ret = -1; - goto fail; - } - - while (async_ret == NOT_DONE) { - qemu_aio_wait(); - } - - -fail: - return async_ret; -} - -static int bdrv_write_em(BlockDriverState *bs, int64_t sector_num, - const uint8_t *buf, int nb_sectors) -{ - int async_ret; - BlockDriverAIOCB *acb; - struct iovec iov; - QEMUIOVector qiov; - - async_ret = NOT_DONE; - iov.iov_base = (void *)buf; - iov.iov_len = nb_sectors * BDRV_SECTOR_SIZE; - qemu_iovec_init_external(&qiov, &iov, 1); - acb = bdrv_aio_writev(bs, sector_num, &qiov, nb_sectors, - bdrv_rw_em_cb, &async_ret); - if (acb == NULL) { - async_ret = -1; - goto fail; - } - while (async_ret == NOT_DONE) { - qemu_aio_wait(); - } - -fail: - return async_ret; -} - void bdrv_init(void) { module_call_init(MODULE_INIT_BLOCK); @@ -2992,11 +2886,11 @@ static int coroutine_fn bdrv_co_io_em(BlockDriverState *bs, int64_t sector_num, BlockDriverAIOCB *acb; if (is_write) { - acb = bdrv_aio_writev(bs, sector_num, iov, nb_sectors, - bdrv_co_io_em_complete, &co); + acb = bs->drv->bdrv_aio_writev(bs, sector_num, iov, nb_sectors, + bdrv_co_io_em_complete, &co); } else { - acb = bdrv_aio_readv(bs, sector_num, iov, nb_sectors, - bdrv_co_io_em_complete, &co); + acb = bs->drv->bdrv_aio_readv(bs, sector_num, iov, nb_sectors, + bdrv_co_io_em_complete, &co); } trace_bdrv_co_io_em(bs, sector_num, nb_sectors, is_write, acb); @@ -3183,6 +3077,44 @@ int bdrv_in_use(BlockDriverState *bs) return bs->in_use; } +void bdrv_iostatus_enable(BlockDriverState *bs) +{ + bs->iostatus = BDRV_IOS_OK; +} + +/* The I/O status is only enabled if the drive explicitly + * enables it _and_ the VM is configured to stop on errors */ +bool bdrv_iostatus_is_enabled(const BlockDriverState *bs) +{ + return (bs->iostatus != BDRV_IOS_INVAL && + (bs->on_write_error == BLOCK_ERR_STOP_ENOSPC || + bs->on_write_error == BLOCK_ERR_STOP_ANY || + bs->on_read_error == BLOCK_ERR_STOP_ANY)); +} + +void bdrv_iostatus_disable(BlockDriverState *bs) +{ + bs->iostatus = BDRV_IOS_INVAL; +} + +void bdrv_iostatus_reset(BlockDriverState *bs) +{ + if (bdrv_iostatus_is_enabled(bs)) { + bs->iostatus = BDRV_IOS_OK; + } +} + +/* XXX: Today this is set by device models because it makes the implementation + quite simple. However, the block layer knows about the error, so it's + possible to implement this without device models being involved */ +void bdrv_iostatus_set_err(BlockDriverState *bs, int error) +{ + if (bdrv_iostatus_is_enabled(bs) && bs->iostatus == BDRV_IOS_OK) { + assert(error >= 0); + bs->iostatus = error == ENOSPC ? BDRV_IOS_ENOSPC : BDRV_IOS_FAILED; + } +} + void bdrv_acct_start(BlockDriverState *bs, BlockAcctCookie *cookie, int64_t bytes, enum BlockAcctType type) @@ -77,6 +77,16 @@ typedef enum { BDRV_ACTION_REPORT, BDRV_ACTION_IGNORE, BDRV_ACTION_STOP } BlockMonEventAction; +typedef enum { + BDRV_IOS_INVAL, BDRV_IOS_OK, BDRV_IOS_FAILED, BDRV_IOS_ENOSPC, + BDRV_IOS_MAX +} BlockIOStatus; + +void bdrv_iostatus_enable(BlockDriverState *bs); +void bdrv_iostatus_reset(BlockDriverState *bs); +void bdrv_iostatus_disable(BlockDriverState *bs); +bool bdrv_iostatus_is_enabled(const BlockDriverState *bs); +void bdrv_iostatus_set_err(BlockDriverState *bs, int error); void bdrv_mon_event(const BlockDriverState *bdrv, BlockMonEventAction action, int is_read); void bdrv_info_print(Monitor *mon, const QObject *data); diff --git a/block/qcow.c b/block/qcow.c index c8bfecc1cb..eba5a04c44 100644 --- a/block/qcow.c +++ b/block/qcow.c @@ -596,7 +596,7 @@ static int qcow_co_writev(BlockDriverState *bs, int64_t sector_num, if (qiov->niov > 1) { qemu_vfree(orig_buf); } - free(cluster_data); + g_free(cluster_data); return ret; } diff --git a/block/raw-posix.c b/block/raw-posix.c index 305998ddb3..c7f5544edd 100644 --- a/block/raw-posix.c +++ b/block/raw-posix.c @@ -297,273 +297,6 @@ static int raw_open(BlockDriverState *bs, const char *filename, int flags) */ /* - * offset and count are in bytes, but must be multiples of 512 for files - * opened with O_DIRECT. buf must be aligned to 512 bytes then. - * - * This function may be called without alignment if the caller ensures - * that O_DIRECT is not in effect. - */ -static int raw_pread_aligned(BlockDriverState *bs, int64_t offset, - uint8_t *buf, int count) -{ - BDRVRawState *s = bs->opaque; - int ret; - - ret = fd_open(bs); - if (ret < 0) - return ret; - - ret = pread(s->fd, buf, count, offset); - if (ret == count) - return ret; - - /* Allow reads beyond the end (needed for pwrite) */ - if ((ret == 0) && bs->growable) { - int64_t size = raw_getlength(bs); - if (offset >= size) { - memset(buf, 0, count); - return count; - } - } - - DEBUG_BLOCK_PRINT("raw_pread(%d:%s, %" PRId64 ", %p, %d) [%" PRId64 - "] read failed %d : %d = %s\n", - s->fd, bs->filename, offset, buf, count, - bs->total_sectors, ret, errno, strerror(errno)); - - /* Try harder for CDrom. */ - if (s->type != FTYPE_FILE) { - ret = pread(s->fd, buf, count, offset); - if (ret == count) - return ret; - ret = pread(s->fd, buf, count, offset); - if (ret == count) - return ret; - - DEBUG_BLOCK_PRINT("raw_pread(%d:%s, %" PRId64 ", %p, %d) [%" PRId64 - "] retry read failed %d : %d = %s\n", - s->fd, bs->filename, offset, buf, count, - bs->total_sectors, ret, errno, strerror(errno)); - } - - return (ret < 0) ? -errno : ret; -} - -/* - * offset and count are in bytes, but must be multiples of the sector size - * for files opened with O_DIRECT. buf must be aligned to sector size bytes - * then. - * - * This function may be called without alignment if the caller ensures - * that O_DIRECT is not in effect. - */ -static int raw_pwrite_aligned(BlockDriverState *bs, int64_t offset, - const uint8_t *buf, int count) -{ - BDRVRawState *s = bs->opaque; - int ret; - - ret = fd_open(bs); - if (ret < 0) - return -errno; - - ret = pwrite(s->fd, buf, count, offset); - if (ret == count) - return ret; - - DEBUG_BLOCK_PRINT("raw_pwrite(%d:%s, %" PRId64 ", %p, %d) [%" PRId64 - "] write failed %d : %d = %s\n", - s->fd, bs->filename, offset, buf, count, - bs->total_sectors, ret, errno, strerror(errno)); - - return (ret < 0) ? -errno : ret; -} - - -/* - * offset and count are in bytes and possibly not aligned. For files opened - * with O_DIRECT, necessary alignments are ensured before calling - * raw_pread_aligned to do the actual read. - */ -static int raw_pread(BlockDriverState *bs, int64_t offset, - uint8_t *buf, int count) -{ - BDRVRawState *s = bs->opaque; - unsigned sector_mask = bs->buffer_alignment - 1; - int size, ret, shift, sum; - - sum = 0; - - if (s->aligned_buf != NULL) { - - if (offset & sector_mask) { - /* align offset on a sector size bytes boundary */ - - shift = offset & sector_mask; - size = (shift + count + sector_mask) & ~sector_mask; - if (size > s->aligned_buf_size) - size = s->aligned_buf_size; - ret = raw_pread_aligned(bs, offset - shift, s->aligned_buf, size); - if (ret < 0) - return ret; - - size = bs->buffer_alignment - shift; - if (size > count) - size = count; - memcpy(buf, s->aligned_buf + shift, size); - - buf += size; - offset += size; - count -= size; - sum += size; - - if (count == 0) - return sum; - } - if (count & sector_mask || (uintptr_t) buf & sector_mask) { - - /* read on aligned buffer */ - - while (count) { - - size = (count + sector_mask) & ~sector_mask; - if (size > s->aligned_buf_size) - size = s->aligned_buf_size; - - ret = raw_pread_aligned(bs, offset, s->aligned_buf, size); - if (ret < 0) { - return ret; - } else if (ret == 0) { - fprintf(stderr, "raw_pread: read beyond end of file\n"); - abort(); - } - - size = ret; - if (size > count) - size = count; - - memcpy(buf, s->aligned_buf, size); - - buf += size; - offset += size; - count -= size; - sum += size; - } - - return sum; - } - } - - return raw_pread_aligned(bs, offset, buf, count) + sum; -} - -static int raw_read(BlockDriverState *bs, int64_t sector_num, - uint8_t *buf, int nb_sectors) -{ - int ret; - - ret = raw_pread(bs, sector_num * BDRV_SECTOR_SIZE, buf, - nb_sectors * BDRV_SECTOR_SIZE); - if (ret == (nb_sectors * BDRV_SECTOR_SIZE)) - ret = 0; - return ret; -} - -/* - * offset and count are in bytes and possibly not aligned. For files opened - * with O_DIRECT, necessary alignments are ensured before calling - * raw_pwrite_aligned to do the actual write. - */ -static int raw_pwrite(BlockDriverState *bs, int64_t offset, - const uint8_t *buf, int count) -{ - BDRVRawState *s = bs->opaque; - unsigned sector_mask = bs->buffer_alignment - 1; - int size, ret, shift, sum; - - sum = 0; - - if (s->aligned_buf != NULL) { - - if (offset & sector_mask) { - /* align offset on a sector size bytes boundary */ - shift = offset & sector_mask; - ret = raw_pread_aligned(bs, offset - shift, s->aligned_buf, - bs->buffer_alignment); - if (ret < 0) - return ret; - - size = bs->buffer_alignment - shift; - if (size > count) - size = count; - memcpy(s->aligned_buf + shift, buf, size); - - ret = raw_pwrite_aligned(bs, offset - shift, s->aligned_buf, - bs->buffer_alignment); - if (ret < 0) - return ret; - - buf += size; - offset += size; - count -= size; - sum += size; - - if (count == 0) - return sum; - } - if (count & sector_mask || (uintptr_t) buf & sector_mask) { - - while ((size = (count & ~sector_mask)) != 0) { - - if (size > s->aligned_buf_size) - size = s->aligned_buf_size; - - memcpy(s->aligned_buf, buf, size); - - ret = raw_pwrite_aligned(bs, offset, s->aligned_buf, size); - if (ret < 0) - return ret; - - buf += ret; - offset += ret; - count -= ret; - sum += ret; - } - /* here, count < sector_size because (count & ~sector_mask) == 0 */ - if (count) { - ret = raw_pread_aligned(bs, offset, s->aligned_buf, - bs->buffer_alignment); - if (ret < 0) - return ret; - memcpy(s->aligned_buf, buf, count); - - ret = raw_pwrite_aligned(bs, offset, s->aligned_buf, - bs->buffer_alignment); - if (ret < 0) - return ret; - if (count < ret) - ret = count; - - sum += ret; - } - return sum; - } - } - return raw_pwrite_aligned(bs, offset, buf, count) + sum; -} - -static int raw_write(BlockDriverState *bs, int64_t sector_num, - const uint8_t *buf, int nb_sectors) -{ - int ret; - ret = raw_pwrite(bs, sector_num * BDRV_SECTOR_SIZE, buf, - nb_sectors * BDRV_SECTOR_SIZE); - if (ret == (nb_sectors * BDRV_SECTOR_SIZE)) - ret = 0; - return ret; -} - -/* * Check if all memory in this vector is sector aligned. */ static int qiov_is_aligned(BlockDriverState *bs, QEMUIOVector *qiov) @@ -649,10 +382,24 @@ static void raw_close(BlockDriverState *bs) static int raw_truncate(BlockDriverState *bs, int64_t offset) { BDRVRawState *s = bs->opaque; - if (s->type != FTYPE_FILE) - return -ENOTSUP; - if (ftruncate(s->fd, offset) < 0) + struct stat st; + + if (fstat(s->fd, &st)) { return -errno; + } + + if (S_ISREG(st.st_mode)) { + if (ftruncate(s->fd, offset) < 0) { + return -errno; + } + } else if (S_ISCHR(st.st_mode) || S_ISBLK(st.st_mode)) { + if (offset > raw_getlength(bs)) { + return -EINVAL; + } + } else { + return -ENOTSUP; + } + return 0; } @@ -896,8 +643,6 @@ static BlockDriver bdrv_file = { .instance_size = sizeof(BDRVRawState), .bdrv_probe = NULL, /* no probe for protocols */ .bdrv_file_open = raw_open, - .bdrv_read = raw_read, - .bdrv_write = raw_write, .bdrv_close = raw_close, .bdrv_create = raw_create, .bdrv_flush = raw_flush, @@ -1176,8 +921,7 @@ static BlockDriver bdrv_host_device = { .bdrv_aio_writev = raw_aio_writev, .bdrv_aio_flush = raw_aio_flush, - .bdrv_read = raw_read, - .bdrv_write = raw_write, + .bdrv_truncate = raw_truncate, .bdrv_getlength = raw_getlength, .bdrv_get_allocated_file_size = raw_get_allocated_file_size, @@ -1297,8 +1041,7 @@ static BlockDriver bdrv_host_floppy = { .bdrv_aio_writev = raw_aio_writev, .bdrv_aio_flush = raw_aio_flush, - .bdrv_read = raw_read, - .bdrv_write = raw_write, + .bdrv_truncate = raw_truncate, .bdrv_getlength = raw_getlength, .bdrv_get_allocated_file_size = raw_get_allocated_file_size, @@ -1398,8 +1141,7 @@ static BlockDriver bdrv_host_cdrom = { .bdrv_aio_writev = raw_aio_writev, .bdrv_aio_flush = raw_aio_flush, - .bdrv_read = raw_read, - .bdrv_write = raw_write, + .bdrv_truncate = raw_truncate, .bdrv_getlength = raw_getlength, .bdrv_get_allocated_file_size = raw_get_allocated_file_size, @@ -1519,8 +1261,7 @@ static BlockDriver bdrv_host_cdrom = { .bdrv_aio_writev = raw_aio_writev, .bdrv_aio_flush = raw_aio_flush, - .bdrv_read = raw_read, - .bdrv_write = raw_write, + .bdrv_truncate = raw_truncate, .bdrv_getlength = raw_getlength, .bdrv_get_allocated_file_size = raw_get_allocated_file_size, diff --git a/block/raw.c b/block/raw.c index 63cf2d3bf3..5ca606b68a 100644 --- a/block/raw.c +++ b/block/raw.c @@ -9,30 +9,16 @@ static int raw_open(BlockDriverState *bs, int flags) return 0; } -static int raw_read(BlockDriverState *bs, int64_t sector_num, - uint8_t *buf, int nb_sectors) +static int coroutine_fn raw_co_readv(BlockDriverState *bs, int64_t sector_num, + int nb_sectors, QEMUIOVector *qiov) { - return bdrv_read(bs->file, sector_num, buf, nb_sectors); + return bdrv_co_readv(bs->file, sector_num, nb_sectors, qiov); } -static int raw_write(BlockDriverState *bs, int64_t sector_num, - const uint8_t *buf, int nb_sectors) +static int coroutine_fn raw_co_writev(BlockDriverState *bs, int64_t sector_num, + int nb_sectors, QEMUIOVector *qiov) { - return bdrv_write(bs->file, sector_num, buf, nb_sectors); -} - -static BlockDriverAIOCB *raw_aio_readv(BlockDriverState *bs, - int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, - BlockDriverCompletionFunc *cb, void *opaque) -{ - return bdrv_aio_readv(bs->file, sector_num, qiov, nb_sectors, cb, opaque); -} - -static BlockDriverAIOCB *raw_aio_writev(BlockDriverState *bs, - int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, - BlockDriverCompletionFunc *cb, void *opaque) -{ - return bdrv_aio_writev(bs->file, sector_num, qiov, nb_sectors, cb, opaque); + return bdrv_co_writev(bs->file, sector_num, nb_sectors, qiov); } static void raw_close(BlockDriverState *bs) @@ -129,15 +115,13 @@ static BlockDriver bdrv_raw = { .bdrv_open = raw_open, .bdrv_close = raw_close, - .bdrv_read = raw_read, - .bdrv_write = raw_write, + .bdrv_co_readv = raw_co_readv, + .bdrv_co_writev = raw_co_writev, .bdrv_flush = raw_flush, .bdrv_probe = raw_probe, .bdrv_getlength = raw_getlength, .bdrv_truncate = raw_truncate, - .bdrv_aio_readv = raw_aio_readv, - .bdrv_aio_writev = raw_aio_writev, .bdrv_aio_flush = raw_aio_flush, .bdrv_discard = raw_discard, diff --git a/block/sheepdog.c b/block/sheepdog.c index c1f6e07ec1..ae857e294c 100644 --- a/block/sheepdog.c +++ b/block/sheepdog.c @@ -66,7 +66,7 @@ * 20 - 31 (12 bits): reserved data object space * 32 - 55 (24 bits): vdi object space * 56 - 59 ( 4 bits): reserved vdi object space - * 60 - 63 ( 4 bits): object type indentifier space + * 60 - 63 ( 4 bits): object type identifier space */ #define VDI_SPACE_SHIFT 32 diff --git a/block/vvfat.c b/block/vvfat.c index f567c9adb9..7e9e35a3a3 100644 --- a/block/vvfat.c +++ b/block/vvfat.c @@ -86,8 +86,7 @@ static inline void array_init(array_t* array,unsigned int item_size) static inline void array_free(array_t* array) { - if(array->pointer) - free(array->pointer); + g_free(array->pointer); array->size=array->next=0; } @@ -169,7 +168,7 @@ static inline int array_roll(array_t* array,int index_to,int index_from,int coun memcpy(to,buf,is*count); - free(buf); + g_free(buf); return 0; } @@ -732,7 +731,7 @@ static int read_directory(BDRVVVFATState* s, int mapping_index) snprintf(buffer,length,"%s/%s",dirname,entry->d_name); if(stat(buffer,&st)<0) { - free(buffer); + g_free(buffer); continue; } @@ -755,7 +754,7 @@ static int read_directory(BDRVVVFATState* s, int mapping_index) direntry->begin=0; /* do that later */ if (st.st_size > 0x7fffffff) { fprintf(stderr, "File %s is larger than 2GB\n", buffer); - free(buffer); + g_free(buffer); closedir(dir); return -2; } @@ -825,20 +824,6 @@ static inline off_t cluster2sector(BDRVVVFATState* s, uint32_t cluster_num) return s->faked_sectors + s->sectors_per_cluster * cluster_num; } -static inline uint32_t sector_offset_in_cluster(BDRVVVFATState* s,off_t sector_num) -{ - return (sector_num-s->first_sectors_number-2*s->sectors_per_fat)%s->sectors_per_cluster; -} - -#ifdef DBG -static direntry_t* get_direntry_for_mapping(BDRVVVFATState* s,mapping_t* mapping) -{ - if(mapping->mode==MODE_UNDEFINED) - return 0; - return (direntry_t*)(s->directory.pointer+sizeof(direntry_t)*mapping->dir_index); -} -#endif - static int init_directories(BDRVVVFATState* s, const char* dirname) { @@ -1138,25 +1123,6 @@ static inline mapping_t* find_mapping_for_cluster(BDRVVVFATState* s,int cluster_ return mapping; } -/* - * This function simply compares path == mapping->path. Since the mappings - * are sorted by cluster, this is expensive: O(n). - */ -static inline mapping_t* find_mapping_for_path(BDRVVVFATState* s, - const char* path) -{ - int i; - - for (i = 0; i < s->mapping.next; i++) { - mapping_t* mapping = array_get(&(s->mapping), i); - if (mapping->first_mapping_index < 0 && - !strcmp(path, mapping->path)) - return mapping; - } - - return NULL; -} - static int open_file(BDRVVVFATState* s,mapping_t* mapping) { if(!mapping) @@ -1223,23 +1189,6 @@ read_cluster_directory: } #ifdef DEBUG -static void hexdump(const void* address, uint32_t len) -{ - const unsigned char* p = address; - int i, j; - - for (i = 0; i < len; i += 16) { - for (j = 0; j < 16 && i + j < len; j++) - fprintf(stderr, "%02x ", p[i + j]); - for (; j < 16; j++) - fprintf(stderr, " "); - fprintf(stderr, " "); - for (j = 0; j < 16 && i + j < len; j++) - fprintf(stderr, "%c", (p[i + j] < ' ' || p[i + j] > 0x7f) ? '.' : p[i + j]); - fprintf(stderr, "\n"); - } -} - static void print_direntry(const direntry_t* direntry) { int j = 0; @@ -1375,7 +1324,7 @@ DLOG(fprintf(stderr, "clear_commits (%d commits)\n", s->commits.next)); assert(commit->path || commit->action == ACTION_WRITEOUT); if (commit->action != ACTION_WRITEOUT) { assert(commit->path); - free(commit->path); + g_free(commit->path); } else assert(commit->path == NULL); } @@ -1741,7 +1690,7 @@ static int check_directory_consistency(BDRVVVFATState *s, long_file_name lfn; int path_len = strlen(path); - char path2[PATH_MAX]; + char path2[PATH_MAX + 1]; assert(path_len < PATH_MAX); /* len was tested before! */ pstrcpy(path2, sizeof(path2), path); @@ -1782,7 +1731,7 @@ DLOG(fprintf(stderr, "read cluster %d (sector %d)\n", (int)cluster_num, (int)clu if (subret) { fprintf(stderr, "Error fetching direntries\n"); fail: - free(cluster); + g_free(cluster); return 0; } @@ -1850,7 +1799,7 @@ DLOG(fprintf(stderr, "check direntry %d:\n", i); print_direntry(direntries + i)) cluster_num = modified_fat_get(s, cluster_num); } while(!fat_eof(s, cluster_num)); - free(cluster); + g_free(cluster); return ret; } @@ -1995,8 +1944,9 @@ static int remove_mapping(BDRVVVFATState* s, int mapping_index) mapping_t* first_mapping = array_get(&(s->mapping), 0); /* free mapping */ - if (mapping->first_mapping_index < 0) - free(mapping->path); + if (mapping->first_mapping_index < 0) { + g_free(mapping->path); + } /* remove from s->mapping */ array_remove(&(s->mapping), mapping_index); @@ -2232,11 +2182,15 @@ static int commit_one_file(BDRVVVFATState* s, if (fd < 0) { fprintf(stderr, "Could not open %s... (%s, %d)\n", mapping->path, strerror(errno), errno); + g_free(cluster); return fd; } - if (offset > 0) - if (lseek(fd, offset, SEEK_SET) != offset) - return -3; + if (offset > 0) { + if (lseek(fd, offset, SEEK_SET) != offset) { + g_free(cluster); + return -3; + } + } while (offset < size) { uint32_t c1; @@ -2252,11 +2206,15 @@ static int commit_one_file(BDRVVVFATState* s, ret = vvfat_read(s->bs, cluster2sector(s, c), (uint8_t*)cluster, (rest_size + 0x1ff) / 0x200); - if (ret < 0) - return ret; + if (ret < 0) { + g_free(cluster); + return ret; + } - if (write(fd, cluster, rest_size) < 0) - return -2; + if (write(fd, cluster, rest_size) < 0) { + g_free(cluster); + return -2; + } offset += rest_size; c = c1; @@ -2265,9 +2223,11 @@ static int commit_one_file(BDRVVVFATState* s, if (ftruncate(fd, size)) { perror("ftruncate()"); close(fd); + g_free(cluster); return -4; } close(fd); + g_free(cluster); return commit_mappings(s, first_cluster, dir_index); } @@ -2399,7 +2359,7 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s) } } - free(old_path); + g_free(old_path); array_remove(&(s->commits), i); continue; } else if (commit->action == ACTION_MKDIR) { @@ -2775,7 +2735,7 @@ static int write_target_commit(BlockDriverState *bs, int64_t sector_num, static void write_target_close(BlockDriverState *bs) { BDRVVVFATState* s = *((BDRVVVFATState**) bs->opaque); bdrv_delete(s->qcow); - free(s->qcow_filename); + g_free(s->qcow_filename); } static BlockDriver vvfat_write_target = { @@ -2836,8 +2796,7 @@ static void vvfat_close(BlockDriverState *bs) array_free(&(s->fat)); array_free(&(s->directory)); array_free(&(s->mapping)); - if(s->cluster_buffer) - free(s->cluster_buffer); + g_free(s->cluster_buffer); } static BlockDriver bdrv_vvfat = { @@ -2878,11 +2837,5 @@ static void checkpoint(void) { direntry = array_get(&(vvv->directory), mapping->dir_index); assert(!memcmp(direntry->name, "USB H ", 11) || direntry->name[0]==0); #endif - return; - /* avoid compiler warnings: */ - hexdump(NULL, 100); - remove_mapping(vvv, 0); - print_mapping(NULL); - print_direntry(NULL); } #endif diff --git a/block_int.h b/block_int.h index 8c3b86373c..f2f4f2db38 100644 --- a/block_int.h +++ b/block_int.h @@ -199,6 +199,7 @@ struct BlockDriverState { drivers. They are not used by the block driver */ int cyls, heads, secs, translation; BlockErrorAction on_read_error, on_write_error; + BlockIOStatus iostatus; char device_name[32]; unsigned long *dirty_bitmap; int64_t dirty_count; @@ -887,6 +887,17 @@ void vm_stop(RunState state) do_vm_stop(state); } +/* does a state transition even if the VM is already stopped, + current state is forgotten forever */ +void vm_stop_force_state(RunState state) +{ + if (runstate_is_running()) { + vm_stop(state); + } else { + runstate_set(state); + } +} + static int tcg_cpu_exec(CPUState *env) { int ret; diff --git a/default-configs/alpha-softmmu.mak b/default-configs/alpha-softmmu.mak index be86d0c4e6..bd1dd95a2a 100644 --- a/default-configs/alpha-softmmu.mak +++ b/default-configs/alpha-softmmu.mak @@ -9,3 +9,4 @@ CONFIG_IDE_CORE=y CONFIG_IDE_QDEV=y CONFIG_VMWARE_VGA=y CONFIG_IDE_CMD646=y +CONFIG_I8259=y diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak index 55589fa071..e67ebb360e 100644 --- a/default-configs/i386-softmmu.mak +++ b/default-configs/i386-softmmu.mak @@ -21,3 +21,4 @@ CONFIG_PIIX_PCI=y CONFIG_SOUND=y CONFIG_HPET=y CONFIG_APPLESMC=y +CONFIG_I8259=y diff --git a/default-configs/mips-softmmu.mak b/default-configs/mips-softmmu.mak index 45bdefb9b2..94a34862dc 100644 --- a/default-configs/mips-softmmu.mak +++ b/default-configs/mips-softmmu.mak @@ -27,3 +27,4 @@ CONFIG_DS1225Y=y CONFIG_MIPSNET=y CONFIG_PFLASH_CFI01=y CONFIG_G364FB=y +CONFIG_I8259=y diff --git a/default-configs/mips64-softmmu.mak b/default-configs/mips64-softmmu.mak index d43e33ca60..b5d310816f 100644 --- a/default-configs/mips64-softmmu.mak +++ b/default-configs/mips64-softmmu.mak @@ -27,3 +27,4 @@ CONFIG_DS1225Y=y CONFIG_MIPSNET=y CONFIG_PFLASH_CFI01=y CONFIG_G364FB=y +CONFIG_I8259=y diff --git a/default-configs/mips64el-softmmu.mak b/default-configs/mips64el-softmmu.mak index f307e8d8b0..2831f44f2a 100644 --- a/default-configs/mips64el-softmmu.mak +++ b/default-configs/mips64el-softmmu.mak @@ -29,3 +29,4 @@ CONFIG_MIPSNET=y CONFIG_PFLASH_CFI01=y CONFIG_FULONG=y CONFIG_G364FB=y +CONFIG_I8259=y diff --git a/default-configs/mipsel-softmmu.mak b/default-configs/mipsel-softmmu.mak index 1a66bc31bb..14c949df13 100644 --- a/default-configs/mipsel-softmmu.mak +++ b/default-configs/mipsel-softmmu.mak @@ -27,3 +27,4 @@ CONFIG_DS1225Y=y CONFIG_MIPSNET=y CONFIG_PFLASH_CFI01=y CONFIG_G364FB=y +CONFIG_I8259=y diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak index 45637429ed..c85cdceb15 100644 --- a/default-configs/ppc-softmmu.mak +++ b/default-configs/ppc-softmmu.mak @@ -31,3 +31,4 @@ CONFIG_SOUND=y CONFIG_PFLASH_CFI01=y CONFIG_PFLASH_CFI02=y CONFIG_PTIMER=y +CONFIG_I8259=y diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak index d5073b3e09..8874115d81 100644 --- a/default-configs/ppc64-softmmu.mak +++ b/default-configs/ppc64-softmmu.mak @@ -31,3 +31,4 @@ CONFIG_SOUND=y CONFIG_PFLASH_CFI01=y CONFIG_PFLASH_CFI02=y CONFIG_PTIMER=y +CONFIG_I8259=y diff --git a/default-configs/ppcemb-softmmu.mak b/default-configs/ppcemb-softmmu.mak index 9f0730c7a5..5db7205267 100644 --- a/default-configs/ppcemb-softmmu.mak +++ b/default-configs/ppcemb-softmmu.mak @@ -31,3 +31,4 @@ CONFIG_SOUND=y CONFIG_PFLASH_CFI01=y CONFIG_PFLASH_CFI02=y CONFIG_PTIMER=y +CONFIG_I8259=y diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak index 8895028e11..b75757ee5f 100644 --- a/default-configs/x86_64-softmmu.mak +++ b/default-configs/x86_64-softmmu.mak @@ -21,3 +21,4 @@ CONFIG_PIIX_PCI=y CONFIG_SOUND=y CONFIG_HPET=y CONFIG_APPLESMC=y +CONFIG_I8259=y diff --git a/default-configs/xtensa-softmmu.mak b/default-configs/xtensa-softmmu.mak index e5faa09012..7f0df3499e 100644 --- a/default-configs/xtensa-softmmu.mak +++ b/default-configs/xtensa-softmmu.mak @@ -1 +1,4 @@ # Default configuration for Xtensa + +CONFIG_SERIAL=y +CONFIG_OPENCORES_ETH=y diff --git a/default-configs/xtensaeb-softmmu.mak b/default-configs/xtensaeb-softmmu.mak index e5faa09012..7f0df3499e 100644 --- a/default-configs/xtensaeb-softmmu.mak +++ b/default-configs/xtensaeb-softmmu.mak @@ -1 +1,4 @@ # Default configuration for Xtensa + +CONFIG_SERIAL=y +CONFIG_OPENCORES_ETH=y diff --git a/hpet.h b/hpet.h deleted file mode 100644 index 754051a443..0000000000 --- a/hpet.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef __HPET__ -#define __HPET__ 1 - - - -struct hpet_info { - unsigned long hi_ireqfreq; /* Hz */ - unsigned long hi_flags; /* information */ - unsigned short hi_hpet; - unsigned short hi_timer; -}; - -#define HPET_INFO_PERIODIC 0x0001 /* timer is periodic */ - -#define HPET_IE_ON _IO('h', 0x01) /* interrupt on */ -#define HPET_IE_OFF _IO('h', 0x02) /* interrupt off */ -#define HPET_INFO _IOR('h', 0x03, struct hpet_info) -#define HPET_EPI _IO('h', 0x04) /* enable periodic */ -#define HPET_DPI _IO('h', 0x05) /* disable periodic */ -#define HPET_IRQFREQ _IOW('h', 0x6, unsigned long) /* IRQFREQ usec */ - -#endif /* !__HPET__ */ diff --git a/hw/an5206.c b/hw/an5206.c index 481ae60449..3fe1f00d9b 100644 --- a/hw/an5206.c +++ b/hw/an5206.c @@ -7,7 +7,6 @@ */ #include "hw.h" -#include "pc.h" #include "mcf.h" #include "boards.h" #include "loader.h" @@ -18,15 +17,6 @@ #define AN5206_MBAR_ADDR 0x10000000 #define AN5206_RAMBAR_ADDR 0x20000000 -/* Stub functions for hardware that doesn't exist. */ -void pic_info(Monitor *mon) -{ -} - -void irq_info(Monitor *mon) -{ -} - /* Board init. */ static void an5206_init(ram_addr_t ram_size, @@ -23,6 +23,7 @@ #include "host-utils.h" #include "sysbus.h" #include "trace.h" +#include "pc.h" /* APIC Local Vector Table */ #define APIC_LVT_TIMER 0 @@ -399,6 +400,9 @@ static void apic_update_irq(APICState *s) } if (apic_irq_pending(s) > 0) { cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); + } else if (apic_accept_pic_intr(&s->busdev.qdev) && + pic_get_output(isa_pic)) { + apic_deliver_pic_intr(&s->busdev.qdev, 1); } } diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c index 7d60ef6ba8..974a0d8262 100644 --- a/hw/arm11mpcore.c +++ b/hw/arm11mpcore.c @@ -48,17 +48,6 @@ static void mpcore_rirq_set_irq(void *opaque, int irq, int level) } } -static void mpcore_rirq_map(SysBusDevice *dev, target_phys_addr_t base) -{ - mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev); - sysbus_mmio_map(s->priv, 0, base); -} - -static void mpcore_rirq_unmap(SysBusDevice *dev, target_phys_addr_t base) -{ - /* nothing to do */ -} - static int realview_mpcore_init(SysBusDevice *dev) { mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev); @@ -84,7 +73,7 @@ static int realview_mpcore_init(SysBusDevice *dev) } } qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64); - sysbus_init_mmio_cb2(dev, mpcore_rirq_map, mpcore_rirq_unmap); + sysbus_init_mmio_region(dev, sysbus_mmio_get_region(s->priv, 0)); return 0; } diff --git a/hw/arm_pic.c b/hw/arm_pic.c index 985148a380..a2e8a73301 100644 --- a/hw/arm_pic.c +++ b/hw/arm_pic.c @@ -8,19 +8,8 @@ */ #include "hw.h" -#include "pc.h" #include "arm-misc.h" -/* Stub functions for hardware that doesn't exist. */ -void pic_info(Monitor *mon) -{ -} - -void irq_info(Monitor *mon) -{ -} - - /* Input 0 is IRQ and input 1 is FIQ. */ static void arm_pic_cpu_handler(void *opaque, int irq, int level) { @@ -39,7 +28,7 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level) cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ); break; default: - hw_error("arm_pic_cpu_handler: Bad interrput line %d\n", irq); + hw_error("arm_pic_cpu_handler: Bad interrupt line %d\n", irq); } } diff --git a/hw/cris_pic_cpu.c b/hw/cris_pic_cpu.c index 7f1e4ab855..06ae484950 100644 --- a/hw/cris_pic_cpu.c +++ b/hw/cris_pic_cpu.c @@ -24,16 +24,10 @@ #include "sysbus.h" #include "hw.h" -#include "pc.h" #include "etraxfs.h" #define D(x) -void pic_info(Monitor *mon) -{} -void irq_info(Monitor *mon) -{} - static void cris_pic_cpu_handler(void *opaque, int irq, int level) { CPUState *env = (CPUState *)opaque; diff --git a/hw/etraxfs.h b/hw/etraxfs.h index 1554b0b8e8..24e8fd880b 100644 --- a/hw/etraxfs.h +++ b/hw/etraxfs.h @@ -22,6 +22,7 @@ * THE SOFTWARE. */ +#include "net.h" #include "etraxfs_dma.h" qemu_irq *cris_pic_init_cpu(CPUState *env); @@ -424,7 +424,6 @@ typedef struct FDCtrlSysBus { typedef struct FDCtrlISABus { ISADevice busdev; - MemoryRegion io_0, io_7; struct FDCtrl state; int32_t bootindexA; int32_t bootindexB; @@ -1880,32 +1879,10 @@ static int fdctrl_init_common(FDCtrl *fdctrl) return fdctrl_connect_drives(fdctrl); } -static uint32_t fdctrl_read_port_7(void *opaque, uint32_t reg) -{ - return fdctrl_read(opaque, reg + 7); -} - -static void fdctrl_write_port_7(void *opaque, uint32_t reg, uint32_t value) -{ - fdctrl_write(opaque, reg + 7, value); -} - -static const MemoryRegionPortio fdc_portio_0[] = { +static const MemoryRegionPortio fdc_portio_list[] = { { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write }, - PORTIO_END_OF_LIST() -}; - -static const MemoryRegionPortio fdc_portio_7[] = { - { 0, 1, 1, .read = fdctrl_read_port_7, .write = fdctrl_write_port_7 }, - PORTIO_END_OF_LIST() -}; - -static const MemoryRegionOps fdc_ioport_0_ops = { - .old_portio = fdc_portio_0 -}; - -static const MemoryRegionOps fdc_ioport_7_ops = { - .old_portio = fdc_portio_7 + { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write }, + PORTIO_END_OF_LIST(), }; static int isabus_fdc_init1(ISADevice *dev) @@ -1917,10 +1894,7 @@ static int isabus_fdc_init1(ISADevice *dev) int dma_chann = 2; int ret; - memory_region_init_io(&isa->io_0, &fdc_ioport_0_ops, fdctrl, "fdc", 6); - memory_region_init_io(&isa->io_7, &fdc_ioport_7_ops, fdctrl, "fdc", 1); - isa_register_ioport(dev, &isa->io_0, iobase); - isa_register_ioport(dev, &isa->io_7, iobase + 7); + isa_register_portio_list(dev, iobase, fdc_portio_list, fdctrl, "fdc"); isa_init_irq(&isa->busdev, &fdctrl->irq, isairq); fdctrl->dma_chann = dma_chann; diff --git a/hw/g364fb.c b/hw/g364fb.c index b43341f8d7..f00ee27b17 100644 --- a/hw/g364fb.c +++ b/hw/g364fb.c @@ -245,6 +245,8 @@ static void g364fb_update_display(void *opaque) { G364State *s = opaque; + qemu_flush_coalesced_mmio_buffer(); + if (s->width == 0 || s->height == 0) return; @@ -297,6 +299,8 @@ static void g364fb_screen_dump(void *opaque, const char *filename) uint8_t *data_buffer; FILE *f; + qemu_flush_coalesced_mmio_buffer(); + if (s->depth != 8) { error_report("g364: unknown guest depth %d", s->depth); return; @@ -232,6 +232,22 @@ static const VMStateDescription vmstate_gus = { } }; +static const MemoryRegionPortio gus_portio_list1[] = { + {0x000, 1, 1, .write = gus_writeb }, + {0x000, 1, 2, .write = gus_writew }, + {0x006, 10, 1, .read = gus_readb, .write = gus_writeb }, + {0x006, 10, 2, .read = gus_readw, .write = gus_writew }, + {0x100, 8, 1, .read = gus_readb, .write = gus_writeb }, + {0x100, 8, 2, .read = gus_readw, .write = gus_writew }, + PORTIO_END_OF_LIST(), +}; + +static const MemoryRegionPortio gus_portio_list2[] = { + {0, 1, 1, .read = gus_readb }, + {0, 1, 2, .read = gus_readw }, + PORTIO_END_OF_LIST(), +}; + static int gus_initfn (ISADevice *dev) { GUSState *s = DO_UPCAST (GUSState, dev, dev); @@ -262,25 +278,9 @@ static int gus_initfn (ISADevice *dev) s->samples = AUD_get_buffer_size_out (s->voice) >> s->shift; s->mixbuf = g_malloc0 (s->samples << s->shift); - register_ioport_write (s->port, 1, 1, gus_writeb, s); - register_ioport_write (s->port, 1, 2, gus_writew, s); - isa_init_ioport_range (dev, s->port, 2); - - register_ioport_read ((s->port + 0x100) & 0xf00, 1, 1, gus_readb, s); - register_ioport_read ((s->port + 0x100) & 0xf00, 1, 2, gus_readw, s); - isa_init_ioport_range (dev, (s->port + 0x100) & 0xf00, 2); - - register_ioport_write (s->port + 6, 10, 1, gus_writeb, s); - register_ioport_write (s->port + 6, 10, 2, gus_writew, s); - register_ioport_read (s->port + 6, 10, 1, gus_readb, s); - register_ioport_read (s->port + 6, 10, 2, gus_readw, s); - isa_init_ioport_range (dev, s->port + 6, 10); - - register_ioport_write (s->port + 0x100, 8, 1, gus_writeb, s); - register_ioport_write (s->port + 0x100, 8, 2, gus_writew, s); - register_ioport_read (s->port + 0x100, 8, 1, gus_readb, s); - register_ioport_read (s->port + 0x100, 8, 2, gus_readw, s); - isa_init_ioport_range (dev, s->port + 0x100, 8); + isa_register_portio_list (dev, s->port, gus_portio_list1, s, "gus"); + isa_register_portio_list (dev, (s->port + 0x100) & 0xf00, + gus_portio_list2, s, "gus"); DMA_register_channel (s->emu.gusdma, GUS_read_DMA, s); s->emu.himemaddr = s->himem; diff --git a/hw/i8259.c b/hw/i8259.c index e5323ffa4d..ab519de5d8 100644 --- a/hw/i8259.c +++ b/hw/i8259.c @@ -40,7 +40,8 @@ //#define DEBUG_IRQ_LATENCY //#define DEBUG_IRQ_COUNT -typedef struct PicState { +struct PicState { + ISADevice dev; uint8_t last_irr; /* edge detection */ uint8_t irr; /* interrupt request register */ uint8_t imr; /* interrupt mask register */ @@ -58,63 +59,39 @@ typedef struct PicState { uint8_t single_mode; /* true if slave pic is not initialized */ uint8_t elcr; /* PIIX edge/trigger selection*/ uint8_t elcr_mask; - PicState2 *pics_state; + qemu_irq int_out[1]; + uint32_t master; /* reflects /SP input pin */ + uint32_t iobase; + uint32_t elcr_addr; MemoryRegion base_io; MemoryRegion elcr_io; -} PicState; - -struct PicState2 { - /* 0 is master pic, 1 is slave pic */ - /* XXX: better separation between the two pics */ - PicState pics[2]; - qemu_irq parent_irq; - void *irq_request_opaque; }; -#if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT) +#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) static int irq_level[16]; #endif #ifdef DEBUG_IRQ_COUNT static uint64_t irq_count[16]; #endif -PicState2 *isa_pic; - -/* set irq level. If an edge is detected, then the IRR is set to 1 */ -static inline void pic_set_irq1(PicState *s, int irq, int level) -{ - int mask; - mask = 1 << irq; - if (s->elcr & mask) { - /* level triggered */ - if (level) { - s->irr |= mask; - s->last_irr |= mask; - } else { - s->irr &= ~mask; - s->last_irr &= ~mask; - } - } else { - /* edge triggered */ - if (level) { - if ((s->last_irr & mask) == 0) - s->irr |= mask; - s->last_irr |= mask; - } else { - s->last_irr &= ~mask; - } - } -} +#ifdef DEBUG_IRQ_LATENCY +static int64_t irq_time[16]; +#endif +PicState *isa_pic; +static PicState *slave_pic; /* return the highest priority found in mask (highest = smallest number). Return 8 if no irq */ -static inline int get_priority(PicState *s, int mask) +static int get_priority(PicState *s, int mask) { int priority; - if (mask == 0) + + if (mask == 0) { return 8; + } priority = 0; - while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) + while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) { priority++; + } return priority; } @@ -125,16 +102,19 @@ static int pic_get_irq(PicState *s) mask = s->irr & ~s->imr; priority = get_priority(s, mask); - if (priority == 8) + if (priority == 8) { return -1; + } /* compute current priority. If special fully nested mode on the master, the IRQ coming from the slave is not taken into account for the priority computation. */ mask = s->isr; - if (s->special_mask) + if (s->special_mask) { mask &= ~s->imr; - if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) + } + if (s->special_fully_nested_mode && s->master) { mask &= ~(1 << 2); + } cur_priority = get_priority(s, mask); if (priority < cur_priority) { /* higher priority found: an irq should be generated */ @@ -144,116 +124,118 @@ static int pic_get_irq(PicState *s) } } -/* raise irq to CPU if necessary. must be called every time the active - irq may change */ -/* XXX: should not export it, but it is needed for an APIC kludge */ -void pic_update_irq(PicState2 *s) +/* Update INT output. Must be called every time the output may have changed. */ +static void pic_update_irq(PicState *s) { - int irq2, irq; - - /* first look at slave pic */ - irq2 = pic_get_irq(&s->pics[1]); - if (irq2 >= 0) { - /* if irq request by slave pic, signal master PIC */ - pic_set_irq1(&s->pics[0], 2, 1); - pic_set_irq1(&s->pics[0], 2, 0); - } - /* look at requested irq */ - irq = pic_get_irq(&s->pics[0]); - if (irq >= 0) { -#if defined(DEBUG_PIC) - { - int i; - for(i = 0; i < 2; i++) { - printf("pic%d: imr=%x irr=%x padd=%d\n", - i, s->pics[i].imr, s->pics[i].irr, - s->pics[i].priority_add); + int irq; - } - } - printf("pic: cpu_interrupt\n"); -#endif - qemu_irq_raise(s->parent_irq); - } - -/* all targets should do this rather than acking the IRQ in the cpu */ -#if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA) - else { - qemu_irq_lower(s->parent_irq); + irq = pic_get_irq(s); + if (irq >= 0) { + DPRINTF("pic%d: imr=%x irr=%x padd=%d\n", + s->master ? 0 : 1, s->imr, s->irr, s->priority_add); + qemu_irq_raise(s->int_out[0]); + } else { + qemu_irq_lower(s->int_out[0]); } -#endif } -#ifdef DEBUG_IRQ_LATENCY -int64_t irq_time[16]; -#endif - -static void i8259_set_irq(void *opaque, int irq, int level) +/* set irq level. If an edge is detected, then the IRR is set to 1 */ +static void pic_set_irq(void *opaque, int irq, int level) { - PicState2 *s = opaque; + PicState *s = opaque; + int mask = 1 << irq; +#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) || \ + defined(DEBUG_IRQ_LATENCY) + int irq_index = s->master ? irq : irq + 8; +#endif #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) - if (level != irq_level[irq]) { - DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level); - irq_level[irq] = level; + if (level != irq_level[irq_index]) { + DPRINTF("pic_set_irq: irq=%d level=%d\n", irq_index, level); + irq_level[irq_index] = level; #ifdef DEBUG_IRQ_COUNT - if (level == 1) - irq_count[irq]++; + if (level == 1) { + irq_count[irq_index]++; + } #endif } #endif #ifdef DEBUG_IRQ_LATENCY if (level) { - irq_time[irq] = qemu_get_clock_ns(vm_clock); + irq_time[irq_index] = qemu_get_clock_ns(vm_clock); } #endif - pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); + + if (s->elcr & mask) { + /* level triggered */ + if (level) { + s->irr |= mask; + s->last_irr |= mask; + } else { + s->irr &= ~mask; + s->last_irr &= ~mask; + } + } else { + /* edge triggered */ + if (level) { + if ((s->last_irr & mask) == 0) { + s->irr |= mask; + } + s->last_irr |= mask; + } else { + s->last_irr &= ~mask; + } + } pic_update_irq(s); } /* acknowledge interrupt 'irq' */ -static inline void pic_intack(PicState *s, int irq) +static void pic_intack(PicState *s, int irq) { if (s->auto_eoi) { - if (s->rotate_on_auto_eoi) + if (s->rotate_on_auto_eoi) { s->priority_add = (irq + 1) & 7; + } } else { s->isr |= (1 << irq); } /* We don't clear a level sensitive interrupt here */ - if (!(s->elcr & (1 << irq))) + if (!(s->elcr & (1 << irq))) { s->irr &= ~(1 << irq); + } + pic_update_irq(s); } -int pic_read_irq(PicState2 *s) +int pic_read_irq(PicState *s) { int irq, irq2, intno; - irq = pic_get_irq(&s->pics[0]); + irq = pic_get_irq(s); if (irq >= 0) { - pic_intack(&s->pics[0], irq); if (irq == 2) { - irq2 = pic_get_irq(&s->pics[1]); + irq2 = pic_get_irq(slave_pic); if (irq2 >= 0) { - pic_intack(&s->pics[1], irq2); + pic_intack(slave_pic, irq2); } else { /* spurious IRQ on slave controller */ irq2 = 7; } - intno = s->pics[1].irq_base + irq2; -#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY) - irq = irq2 + 8; -#endif + intno = slave_pic->irq_base + irq2; } else { - intno = s->pics[0].irq_base + irq; + intno = s->irq_base + irq; } + pic_intack(s, irq); } else { /* spurious IRQ on host controller */ irq = 7; - intno = s->pics[0].irq_base + irq; + intno = s->irq_base + irq; } - pic_update_irq(s); +#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY) + if (irq == 2) { + irq = irq2 + 8; + } +#endif #ifdef DEBUG_IRQ_LATENCY printf("IRQ%d latency=%0.3fus\n", irq, @@ -264,10 +246,8 @@ int pic_read_irq(PicState2 *s) return intno; } -static void pic_reset(void *opaque) +static void pic_init_reset(PicState *s) { - PicState *s = opaque; - s->last_irr = 0; s->irr = 0; s->imr = 0; @@ -284,6 +264,15 @@ static void pic_reset(void *opaque) s->init4 = 0; s->single_mode = 0; /* Note: ELCR is not reset */ + pic_update_irq(s); +} + +static void pic_reset(DeviceState *dev) +{ + PicState *s = container_of(dev, PicState, dev.qdev); + + pic_init_reset(s); + s->elcr = 0; } static void pic_ioport_write(void *opaque, target_phys_addr_t addr64, @@ -297,25 +286,26 @@ static void pic_ioport_write(void *opaque, target_phys_addr_t addr64, DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val); if (addr == 0) { if (val & 0x10) { - /* init */ - pic_reset(s); - /* deassert a pending interrupt */ - qemu_irq_lower(s->pics_state->parent_irq); + pic_init_reset(s); s->init_state = 1; s->init4 = val & 1; s->single_mode = val & 2; - if (val & 0x08) + if (val & 0x08) { hw_error("level sensitive irq not supported"); + } } else if (val & 0x08) { - if (val & 0x04) + if (val & 0x04) { s->poll = 1; - if (val & 0x02) + } + if (val & 0x02) { s->read_reg_select = val & 1; - if (val & 0x40) + } + if (val & 0x40) { s->special_mask = (val >> 5) & 1; + } } else { cmd = val >> 5; - switch(cmd) { + switch (cmd) { case 0: case 4: s->rotate_on_auto_eoi = cmd >> 2; @@ -326,25 +316,26 @@ static void pic_ioport_write(void *opaque, target_phys_addr_t addr64, if (priority != 8) { irq = (priority + s->priority_add) & 7; s->isr &= ~(1 << irq); - if (cmd == 5) + if (cmd == 5) { s->priority_add = (irq + 1) & 7; - pic_update_irq(s->pics_state); + } + pic_update_irq(s); } break; case 3: irq = val & 7; s->isr &= ~(1 << irq); - pic_update_irq(s->pics_state); + pic_update_irq(s); break; case 6: s->priority_add = (val + 1) & 7; - pic_update_irq(s->pics_state); + pic_update_irq(s); break; case 7: irq = val & 7; s->isr &= ~(1 << irq); s->priority_add = (irq + 1) & 7; - pic_update_irq(s->pics_state); + pic_update_irq(s); break; default: /* no operation */ @@ -352,11 +343,11 @@ static void pic_ioport_write(void *opaque, target_phys_addr_t addr64, } } } else { - switch(s->init_state) { + switch (s->init_state) { case 0: /* normal mode */ s->imr = val; - pic_update_irq(s->pics_state); + pic_update_irq(s); break; case 1: s->irq_base = val & 0xf8; @@ -378,46 +369,28 @@ static void pic_ioport_write(void *opaque, target_phys_addr_t addr64, } } -static uint32_t pic_poll_read(PicState *s) -{ - int ret; - - ret = pic_get_irq(s); - if (ret >= 0) { - bool slave = (s == &isa_pic->pics[1]); - - if (slave) { - s->pics_state->pics[0].isr &= ~(1 << 2); - s->pics_state->pics[0].irr &= ~(1 << 2); - } - s->irr &= ~(1 << ret); - s->isr &= ~(1 << ret); - if (slave || ret != 2) - pic_update_irq(s->pics_state); - } else { - ret = 0x07; - pic_update_irq(s->pics_state); - } - - return ret; -} - -static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr1, +static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr, unsigned size) { PicState *s = opaque; - unsigned int addr = addr1; int ret; if (s->poll) { - ret = pic_poll_read(s); + ret = pic_get_irq(s); + if (ret >= 0) { + pic_intack(s, ret); + ret |= 0x80; + } else { + ret = 0; + } s->poll = 0; } else { if (addr == 0) { - if (s->read_reg_select) + if (s->read_reg_select) { ret = s->isr; - else + } else { ret = s->irr; + } } else { ret = s->imr; } @@ -426,19 +399,9 @@ static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr1, return ret; } -/* memory mapped interrupt status */ -/* XXX: may be the same than pic_read_irq() */ -uint32_t pic_intack_read(PicState2 *s) +int pic_get_output(PicState *s) { - int ret; - - ret = pic_poll_read(&s->pics[0]); - if (ret == 2) - ret = pic_poll_read(&s->pics[1]) + 8; - /* Prepare for ISR read */ - s->pics[0].read_reg_select = 1; - - return ret; + return (pic_get_irq(s) >= 0); } static void elcr_ioport_write(void *opaque, target_phys_addr_t addr, @@ -460,7 +423,7 @@ static const VMStateDescription vmstate_pic = { .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, - .fields = (VMStateField []) { + .fields = (VMStateField[]) { VMSTATE_UINT8(last_irr, PicState), VMSTATE_UINT8(irr, PicState), VMSTATE_UINT8(imr, PicState), @@ -499,19 +462,24 @@ static const MemoryRegionOps pic_elcr_ioport_ops = { }, }; -/* XXX: add generic master/slave system */ -static void pic_init1(int io_addr, int elcr_addr, PicState *s) +static int pic_initfn(ISADevice *dev) { + PicState *s = DO_UPCAST(PicState, dev, dev); + memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2); memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1); - isa_register_ioport(NULL, &s->base_io, io_addr); - if (elcr_addr >= 0) { - isa_register_ioport(NULL, &s->elcr_io, elcr_addr); + isa_register_ioport(NULL, &s->base_io, s->iobase); + if (s->elcr_addr != -1) { + isa_register_ioport(NULL, &s->elcr_io, s->elcr_addr); } - vmstate_register(NULL, io_addr, &vmstate_pic, s); - qemu_register_reset(pic_reset, s); + qdev_init_gpio_out(&dev->qdev, s->int_out, ARRAY_SIZE(s->int_out)); + qdev_init_gpio_in(&dev->qdev, pic_set_irq, 8); + + qdev_set_legacy_instance_id(&dev->qdev, s->iobase, 1); + + return 0; } void pic_info(Monitor *mon) @@ -519,11 +487,11 @@ void pic_info(Monitor *mon) int i; PicState *s; - if (!isa_pic) + if (!isa_pic) { return; - - for(i=0;i<2;i++) { - s = &isa_pic->pics[i]; + } + for (i = 0; i < 2; i++) { + s = i == 0 ? isa_pic : slave_pic; monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d " "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", i, s->irr, s->imr, s->isr, s->priority_add, @@ -543,24 +511,69 @@ void irq_info(Monitor *mon) monitor_printf(mon, "IRQ statistics:\n"); for (i = 0; i < 16; i++) { count = irq_count[i]; - if (count > 0) + if (count > 0) { monitor_printf(mon, "%2d: %" PRId64 "\n", i, count); + } } #endif } qemu_irq *i8259_init(qemu_irq parent_irq) { - PicState2 *s; - - s = g_malloc0(sizeof(PicState2)); - pic_init1(0x20, 0x4d0, &s->pics[0]); - pic_init1(0xa0, 0x4d1, &s->pics[1]); - s->pics[0].elcr_mask = 0xf8; - s->pics[1].elcr_mask = 0xde; - s->parent_irq = parent_irq; - s->pics[0].pics_state = s; - s->pics[1].pics_state = s; - isa_pic = s; - return qemu_allocate_irqs(i8259_set_irq, s, 16); + qemu_irq *irq_set; + ISADevice *dev; + int i; + + irq_set = g_malloc(ISA_NUM_IRQS * sizeof(qemu_irq)); + + dev = isa_create("isa-i8259"); + qdev_prop_set_uint32(&dev->qdev, "iobase", 0x20); + qdev_prop_set_uint32(&dev->qdev, "elcr_addr", 0x4d0); + qdev_prop_set_uint8(&dev->qdev, "elcr_mask", 0xf8); + qdev_prop_set_bit(&dev->qdev, "master", true); + qdev_init_nofail(&dev->qdev); + + qdev_connect_gpio_out(&dev->qdev, 0, parent_irq); + for (i = 0 ; i < 8; i++) { + irq_set[i] = qdev_get_gpio_in(&dev->qdev, i); + } + + isa_pic = DO_UPCAST(PicState, dev, dev); + + dev = isa_create("isa-i8259"); + qdev_prop_set_uint32(&dev->qdev, "iobase", 0xa0); + qdev_prop_set_uint32(&dev->qdev, "elcr_addr", 0x4d1); + qdev_prop_set_uint8(&dev->qdev, "elcr_mask", 0xde); + qdev_init_nofail(&dev->qdev); + + qdev_connect_gpio_out(&dev->qdev, 0, irq_set[2]); + for (i = 0 ; i < 8; i++) { + irq_set[i + 8] = qdev_get_gpio_in(&dev->qdev, i); + } + + slave_pic = DO_UPCAST(PicState, dev, dev); + + return irq_set; +} + +static ISADeviceInfo i8259_info = { + .qdev.name = "isa-i8259", + .qdev.size = sizeof(PicState), + .qdev.vmsd = &vmstate_pic, + .qdev.reset = pic_reset, + .qdev.no_user = 1, + .init = pic_initfn, + .qdev.props = (Property[]) { + DEFINE_PROP_HEX32("iobase", PicState, iobase, -1), + DEFINE_PROP_HEX32("elcr_addr", PicState, elcr_addr, -1), + DEFINE_PROP_HEX8("elcr_mask", PicState, elcr_mask, -1), + DEFINE_PROP_BIT("master", PicState, master, 0, false), + DEFINE_PROP_END_OF_LIST(), + }, +}; + +static void pic_register(void) +{ + isa_qdev_register(&i8259_info); } +device_init(pic_register) diff --git a/hw/ide/core.c b/hw/ide/core.c index b71a356f39..280a117fe2 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -25,6 +25,7 @@ #include <hw/hw.h> #include <hw/pc.h> #include <hw/pci.h> +#include <hw/isa.h> #include "qemu-error.h" #include "qemu-timer.h" #include "sysemu.h" @@ -528,6 +529,7 @@ static int ide_handle_rw_error(IDEState *s, int error, int op) s->bus->error_status = op; bdrv_mon_event(s->bs, BDRV_ACTION_STOP, is_read); vm_stop(RUN_STATE_IO_ERROR); + bdrv_iostatus_set_err(s->bs, error); } else { if (op & BM_STATUS_DMA_RETRY) { dma_buf_commit(s, 0); @@ -1872,6 +1874,7 @@ int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind, } ide_reset(s); + bdrv_iostatus_enable(bs); return 0; } @@ -1969,20 +1972,27 @@ void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0, bus->dma = &ide_dma_nop; } -void ide_init_ioport(IDEBus *bus, int iobase, int iobase2) +static const MemoryRegionPortio ide_portio_list[] = { + { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write }, + { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew }, + { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel }, + PORTIO_END_OF_LIST(), +}; + +static const MemoryRegionPortio ide_portio2_list[] = { + { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write }, + PORTIO_END_OF_LIST(), +}; + +void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2) { - register_ioport_write(iobase, 8, 1, ide_ioport_write, bus); - register_ioport_read(iobase, 8, 1, ide_ioport_read, bus); + /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA + bridge has been setup properly to always register with ISA. */ + isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide"); + if (iobase2) { - register_ioport_read(iobase2, 1, 1, ide_status_read, bus); - register_ioport_write(iobase2, 1, 1, ide_cmd_write, bus); + isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide"); } - - /* data ports */ - register_ioport_write(iobase, 2, 2, ide_data_writew, bus); - register_ioport_read(iobase, 2, 2, ide_data_readw, bus); - register_ioport_write(iobase, 4, 4, ide_data_writel, bus); - register_ioport_read(iobase, 4, 4, ide_data_readl, bus); } static bool is_identify_set(void *opaque, int version_id) diff --git a/hw/ide/internal.h b/hw/ide/internal.h index 9046e96013..c39dc058f4 100644 --- a/hw/ide/internal.h +++ b/hw/ide/internal.h @@ -7,6 +7,7 @@ * non-internal declarations are in hw/ide.h */ #include <hw/ide.h> +#include <hw/isa.h> #include "iorange.h" #include "dma.h" #include "sysemu.h" @@ -600,7 +601,7 @@ int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind, void ide_init2(IDEBus *bus, qemu_irq irq); void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0, DriveInfo *hd1, qemu_irq irq); -void ide_init_ioport(IDEBus *bus, int iobase, int iobase2); +void ide_init_ioport(IDEBus *bus, ISADevice *isa, int iobase, int iobase2); void ide_exec_cmd(IDEBus *bus, uint32_t val); void ide_dma_cb(void *opaque, int ret); diff --git a/hw/ide/isa.c b/hw/ide/isa.c index 28b69d2cc3..01a9e59cb9 100644 --- a/hw/ide/isa.c +++ b/hw/ide/isa.c @@ -66,10 +66,8 @@ static int isa_ide_initfn(ISADevice *dev) ISAIDEState *s = DO_UPCAST(ISAIDEState, dev, dev); ide_bus_new(&s->bus, &s->dev.qdev, 0); - ide_init_ioport(&s->bus, s->iobase, s->iobase2); + ide_init_ioport(&s->bus, dev, s->iobase, s->iobase2); isa_init_irq(dev, &s->irq, s->isairq); - isa_init_ioport_range(dev, s->iobase, 8); - isa_init_ioport(dev, s->iobase2); ide_init2(&s->bus, s->irq); vmstate_register(&dev->qdev, 0, &vmstate_ide_isa, s); return 0; diff --git a/hw/ide/piix.c b/hw/ide/piix.c index 88d318127c..08cbbe2032 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -122,8 +122,7 @@ static void piix3_reset(void *opaque) } static void pci_piix_init_ports(PCIIDEState *d) { - int i; - struct { + static const struct { int iobase; int iobase2; int isairq; @@ -131,10 +130,12 @@ static void pci_piix_init_ports(PCIIDEState *d) { {0x1f0, 0x3f6, 14}, {0x170, 0x376, 15}, }; + int i; for (i = 0; i < 2; i++) { ide_bus_new(&d->bus[i], &d->dev.qdev, i); - ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2); + ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, + port_info[i].iobase2); ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq)); bmdma_init(&d->bus[i], &d->bmdma[i], d); diff --git a/hw/ide/via.c b/hw/ide/via.c index dab8a39f57..098f150bb2 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -146,8 +146,7 @@ static void via_reset(void *opaque) } static void vt82c686b_init_ports(PCIIDEState *d) { - int i; - struct { + static const struct { int iobase; int iobase2; int isairq; @@ -155,10 +154,12 @@ static void vt82c686b_init_ports(PCIIDEState *d) { {0x1f0, 0x3f6, 14}, {0x170, 0x376, 15}, }; + int i; for (i = 0; i < 2; i++) { ide_bus_new(&d->bus[i], &d->dev.qdev, i); - ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2); + ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, + port_info[i].iobase2); ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq)); bmdma_init(&d->bus[i], &d->bmdma[i], d); diff --git a/hw/ioapic.h b/hw/ioapic.h index cb2642ae53..86e63dac74 100644 --- a/hw/ioapic.h +++ b/hw/ioapic.h @@ -17,4 +17,11 @@ * License along with this library; if not, see <http://www.gnu.org/licenses/>. */ +#ifndef HW_IOAPIC_H +#define HW_IOAPIC_H + +#define IOAPIC_NUM_PINS 24 + void ioapic_eoi_broadcast(int vector); + +#endif /* !HW_IOAPIC_H */ diff --git a/hw/isa-bus.c b/hw/isa-bus.c index 6c15a31fe8..7c2c2619d0 100644 --- a/hw/isa-bus.c +++ b/hw/isa-bus.c @@ -83,39 +83,32 @@ void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq) dev->nirqs++; } -static void isa_init_ioport_one(ISADevice *dev, uint16_t ioport) +static inline void isa_init_ioport(ISADevice *dev, uint16_t ioport) { - assert(dev->nioports < ARRAY_SIZE(dev->ioports)); - dev->ioports[dev->nioports++] = ioport; + if (dev && (dev->ioport_id == 0 || ioport < dev->ioport_id)) { + dev->ioport_id = ioport; + } } -static int isa_cmp_ports(const void *p1, const void *p2) +void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start) { - return *(uint16_t*)p1 - *(uint16_t*)p2; + memory_region_add_subregion(isabus->address_space_io, start, io); + isa_init_ioport(dev, start); } -void isa_init_ioport_range(ISADevice *dev, uint16_t start, uint16_t length) +void isa_register_portio_list(ISADevice *dev, uint16_t start, + const MemoryRegionPortio *pio_start, + void *opaque, const char *name) { - int i; - for (i = start; i < start + length; i++) { - isa_init_ioport_one(dev, i); - } - qsort(dev->ioports, dev->nioports, sizeof(dev->ioports[0]), isa_cmp_ports); -} + PortioList *piolist = g_new(PortioList, 1); -void isa_init_ioport(ISADevice *dev, uint16_t ioport) -{ - isa_init_ioport_range(dev, ioport, 1); -} + /* START is how we should treat DEV, regardless of the actual + contents of the portio array. This is how the old code + actually handled e.g. the FDC device. */ + isa_init_ioport(dev, start); -void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start) -{ - memory_region_add_subregion(isabus->address_space_io, start, io); - if (dev != NULL) { - assert(dev->nio < ARRAY_SIZE(dev->io)); - dev->io[dev->nio++] = io; - isa_init_ioport_range(dev, start, memory_region_size(io)); - } + portio_list_init(piolist, pio_start, opaque, name); + portio_list_add(piolist, isabus->address_space_io, start); } static int isa_qdev_init(DeviceState *qdev, DeviceInfo *base) @@ -208,8 +201,8 @@ static char *isabus_get_fw_dev_path(DeviceState *dev) int off; off = snprintf(path, sizeof(path), "%s", qdev_fw_name(dev)); - if (d->nioports) { - snprintf(path + off, sizeof(path) - off, "@%04x", d->ioports[0]); + if (d->ioport_id) { + snprintf(path + off, sizeof(path) - off, "@%04x", d->ioport_id); } return strdup(path); @@ -7,18 +7,17 @@ #include "memory.h" #include "qdev.h" +#define ISA_NUM_IRQS 16 + typedef struct ISABus ISABus; typedef struct ISADevice ISADevice; typedef struct ISADeviceInfo ISADeviceInfo; struct ISADevice { DeviceState qdev; - MemoryRegion *io[32]; uint32_t isairq[2]; - uint16_t ioports[32]; int nirqs; - int nioports; - int nio; + int ioport_id; }; typedef int (*isa_qdev_initfn)(ISADevice *dev); @@ -31,15 +30,42 @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space_io); void isa_bus_irqs(qemu_irq *irqs); qemu_irq isa_get_irq(int isairq); void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq); -void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start); -void isa_init_ioport(ISADevice *dev, uint16_t ioport); -void isa_init_ioport_range(ISADevice *dev, uint16_t start, uint16_t length); void isa_qdev_register(ISADeviceInfo *info); MemoryRegion *isa_address_space(ISADevice *dev); ISADevice *isa_create(const char *name); ISADevice *isa_try_create(const char *name); ISADevice *isa_create_simple(const char *name); +/** + * isa_register_ioport: Install an I/O port region on the ISA bus. + * + * Register an I/O port region via memory_region_add_subregion + * inside the ISA I/O address space. + * + * @dev: the ISADevice against which these are registered; may be NULL. + * @io: the #MemoryRegion being registered. + * @start: the base I/O port. + */ +void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start); + +/** + * isa_register_portio_list: Initialize a set of ISA io ports + * + * Several ISA devices have many dis-joint I/O ports. Worse, these I/O + * ports can be interleaved with I/O ports from other devices. This + * function makes it easy to create multiple MemoryRegions for a single + * device and use the legacy portio routines. + * + * @dev: the ISADevice against which these are registered; may be NULL. + * @start: the base I/O port against which the portio->offset is applied. + * @portio: the ports, sorted by offset. + * @opaque: passed into the old_portio callbacks. + * @name: passed into memory_region_init_io. + */ +void isa_register_portio_list(ISADevice *dev, uint16_t start, + const MemoryRegionPortio *portio, + void *opaque, const char *name); + extern target_phys_addr_t isa_mem_base; void isa_mmio_setup(MemoryRegion *mr, target_phys_addr_t size); diff --git a/hw/lan9118.c b/hw/lan9118.c index 73a8661ca3..634b88ee14 100644 --- a/hw/lan9118.c +++ b/hw/lan9118.c @@ -152,7 +152,7 @@ typedef struct { NICState *nic; NICConf conf; qemu_irq irq; - int mmio_index; + MemoryRegion mmio; ptimer_state *timer; uint32_t irq_cfg; @@ -895,7 +895,7 @@ static void lan9118_tick(void *opaque) } static void lan9118_writel(void *opaque, target_phys_addr_t offset, - uint32_t val) + uint64_t val, unsigned size) { lan9118_state *s = (lan9118_state *)opaque; offset &= 0xff; @@ -1022,13 +1022,14 @@ static void lan9118_writel(void *opaque, target_phys_addr_t offset, break; default: - hw_error("lan9118_write: Bad reg 0x%x = %x\n", (int)offset, val); + hw_error("lan9118_write: Bad reg 0x%x = %x\n", (int)offset, (int)val); break; } lan9118_update(s); } -static uint32_t lan9118_readl(void *opaque, target_phys_addr_t offset) +static uint64_t lan9118_readl(void *opaque, target_phys_addr_t offset, + unsigned size) { lan9118_state *s = (lan9118_state *)opaque; @@ -1101,16 +1102,10 @@ static uint32_t lan9118_readl(void *opaque, target_phys_addr_t offset) return 0; } -static CPUReadMemoryFunc * const lan9118_readfn[] = { - lan9118_readl, - lan9118_readl, - lan9118_readl -}; - -static CPUWriteMemoryFunc * const lan9118_writefn[] = { - lan9118_writel, - lan9118_writel, - lan9118_writel +static const MemoryRegionOps lan9118_mem_ops = { + .read = lan9118_readl, + .write = lan9118_writel, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void lan9118_cleanup(VLANClientState *nc) @@ -1135,10 +1130,8 @@ static int lan9118_init1(SysBusDevice *dev) QEMUBH *bh; int i; - s->mmio_index = cpu_register_io_memory(lan9118_readfn, - lan9118_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x100, s->mmio_index); + memory_region_init_io(&s->mmio, &lan9118_mem_ops, s, "lan9118-mmio", 0x100); + sysbus_init_mmio_region(dev, &s->mmio); sysbus_init_irq(dev, &s->irq); qemu_macaddr_default_if_unset(&s->conf.macaddr); diff --git a/hw/lm32_pic.c b/hw/lm32_pic.c index 02941a7d0d..8dd005077c 100644 --- a/hw/lm32_pic.c +++ b/hw/lm32_pic.c @@ -39,7 +39,7 @@ struct LM32PicState { typedef struct LM32PicState LM32PicState; static LM32PicState *pic; -void pic_info(Monitor *mon) +void lm32_do_pic_info(Monitor *mon) { if (pic == NULL) { return; @@ -49,7 +49,7 @@ void pic_info(Monitor *mon) pic->im, pic->ip, pic->irq_state); } -void irq_info(Monitor *mon) +void lm32_irq_info(Monitor *mon) { int i; uint32_t count; diff --git a/hw/lm32_pic.h b/hw/lm32_pic.h index e6479b8f63..14456f37cb 100644 --- a/hw/lm32_pic.h +++ b/hw/lm32_pic.h @@ -8,4 +8,7 @@ uint32_t lm32_pic_get_im(DeviceState *d); void lm32_pic_set_ip(DeviceState *d, uint32_t ip); void lm32_pic_set_im(DeviceState *d, uint32_t im); +void lm32_do_pic_info(Monitor *mon); +void lm32_irq_info(Monitor *mon); + #endif /* QEMU_HW_LM32_PIC_H */ diff --git a/hw/m48t59.c b/hw/m48t59.c index 0cc361eedc..f318e67919 100644 --- a/hw/m48t59.c +++ b/hw/m48t59.c @@ -73,6 +73,7 @@ struct M48t59State { typedef struct M48t59ISAState { ISADevice busdev; M48t59State state; + MemoryRegion io; } M48t59ISAState; typedef struct M48t59SysBusState { @@ -626,6 +627,15 @@ static void m48t59_reset_sysbus(DeviceState *d) m48t59_reset_common(NVRAM); } +static const MemoryRegionPortio m48t59_portio[] = { + {0, 4, 1, .read = NVRAM_readb, .write = NVRAM_writeb }, + PORTIO_END_OF_LIST(), +}; + +static const MemoryRegionOps m48t59_io_ops = { + .old_portio = m48t59_portio, +}; + /* Initialisation routine */ M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base, uint32_t io_base, uint16_t size, int type) @@ -669,10 +679,9 @@ M48t59State *m48t59_init_isa(uint32_t io_base, uint16_t size, int type) d = DO_UPCAST(M48t59ISAState, busdev, dev); s = &d->state; + memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); if (io_base != 0) { - register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); - register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); - isa_init_ioport_range(dev, io_base, 4); + isa_register_ioport(dev, &d->io, io_base); } return s; diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index feb3b25acd..2aaca2ff41 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -81,6 +81,7 @@ typedef struct RTCState { ISADevice dev; + MemoryRegion io; uint8_t cmos_data[128]; uint8_t cmos_index; struct tm current_tm; @@ -604,6 +605,15 @@ static void rtc_reset(void *opaque) #endif } +static const MemoryRegionPortio cmos_portio[] = { + {0, 2, 1, .read = cmos_ioport_read, .write = cmos_ioport_write }, + PORTIO_END_OF_LIST(), +}; + +static const MemoryRegionOps cmos_ops = { + .old_portio = cmos_portio +}; + static int rtc_initfn(ISADevice *dev) { RTCState *s = DO_UPCAST(RTCState, dev, dev); @@ -632,9 +642,8 @@ static int rtc_initfn(ISADevice *dev) qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100; qemu_mod_timer(s->second_timer2, s->next_second_time); - register_ioport_write(base, 2, 1, cmos_ioport_write, s); - register_ioport_read(base, 2, 1, cmos_ioport_read, s); - isa_init_ioport_range(dev, base, 2); + memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2); + isa_register_ioport(dev, &s->io, base); qdev_set_legacy_instance_id(&dev->qdev, base, 2); qemu_register_reset(rtc_reset, s); diff --git a/hw/microblaze_pic_cpu.c b/hw/microblaze_pic_cpu.c index 9ad48b4b95..8b5623ce28 100644 --- a/hw/microblaze_pic_cpu.c +++ b/hw/microblaze_pic_cpu.c @@ -23,16 +23,10 @@ */ #include "hw.h" -#include "pc.h" #include "microblaze_pic_cpu.h" #define D(x) -void pic_info(Monitor *mon) -{} -void irq_info(Monitor *mon) -{} - static void microblaze_pic_cpu_handler(void *opaque, int irq, int level) { CPUState *env = (CPUState *)opaque; diff --git a/hw/ne2000-isa.c b/hw/ne2000-isa.c index 756ed5ca46..11ffee7d7c 100644 --- a/hw/ne2000-isa.c +++ b/hw/ne2000-isa.c @@ -68,10 +68,7 @@ static int isa_ne2000_initfn(ISADevice *dev) NE2000State *s = &isa->ne2000; ne2000_setup_io(s, 0x20); - isa_init_ioport_range(dev, isa->iobase, 16); - isa_init_ioport_range(dev, isa->iobase + 0x10, 2); - isa_init_ioport(dev, isa->iobase + 0x1f); - memory_region_add_subregion(get_system_io(), isa->iobase, &s->io); + isa_register_ioport(dev, &s->io, isa->iobase); isa_init_irq(dev, &s->irq, isa->isairq); diff --git a/hw/opencores_eth.c b/hw/opencores_eth.c new file mode 100644 index 0000000000..64b616ec1c --- /dev/null +++ b/hw/opencores_eth.c @@ -0,0 +1,728 @@ +/* + * OpenCores Ethernet MAC 10/100 + subset of + * National Semiconductors DP83848C 10/100 PHY + * + * http://opencores.org/svnget,ethmac?file=%2Ftrunk%2F%2Fdoc%2Feth_speci.pdf + * http://cache.national.com/ds/DP/DP83848C.pdf + * + * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "hw.h" +#include "sysbus.h" +#include "net.h" +#include "sysemu.h" +#include "trace.h" + +/* RECSMALL is not used because it breaks tap networking in linux: + * incoming ARP responses are too short + */ +#undef USE_RECSMALL + +#define GET_FIELD(v, field) (((v) & (field)) >> (field ## _LBN)) +#define GET_REGBIT(s, reg, field) ((s)->regs[reg] & (reg ## _ ## field)) +#define GET_REGFIELD(s, reg, field) \ + GET_FIELD((s)->regs[reg], reg ## _ ## field) + +#define SET_FIELD(v, field, data) \ + ((v) = (((v) & ~(field)) | (((data) << (field ## _LBN)) & (field)))) +#define SET_REGFIELD(s, reg, field, data) \ + SET_FIELD((s)->regs[reg], reg ## _ ## field, data) + +/* PHY MII registers */ +enum { + MII_BMCR, + MII_BMSR, + MII_PHYIDR1, + MII_PHYIDR2, + MII_ANAR, + MII_ANLPAR, + MII_REG_MAX = 16, +}; + +typedef struct Mii { + uint16_t regs[MII_REG_MAX]; + bool link_ok; +} Mii; + +static void mii_set_link(Mii *s, bool link_ok) +{ + if (link_ok) { + s->regs[MII_BMSR] |= 0x4; + s->regs[MII_ANLPAR] |= 0x01e1; + } else { + s->regs[MII_BMSR] &= ~0x4; + s->regs[MII_ANLPAR] &= 0x01ff; + } + s->link_ok = link_ok; +} + +static void mii_reset(Mii *s) +{ + memset(s->regs, 0, sizeof(s->regs)); + s->regs[MII_BMCR] = 0x1000; + s->regs[MII_BMSR] = 0x7848; /* no ext regs */ + s->regs[MII_PHYIDR1] = 0x2000; + s->regs[MII_PHYIDR2] = 0x5c90; + s->regs[MII_ANAR] = 0x01e1; + mii_set_link(s, s->link_ok); +} + +static void mii_ro(Mii *s, uint16_t v) +{ +} + +static void mii_write_bmcr(Mii *s, uint16_t v) +{ + if (v & 0x8000) { + mii_reset(s); + } else { + s->regs[MII_BMCR] = v; + } +} + +static void mii_write_host(Mii *s, unsigned idx, uint16_t v) +{ + static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = { + [MII_BMCR] = mii_write_bmcr, + [MII_BMSR] = mii_ro, + [MII_PHYIDR1] = mii_ro, + [MII_PHYIDR2] = mii_ro, + }; + + if (idx < MII_REG_MAX) { + trace_open_eth_mii_write(idx, v); + if (reg_write[idx]) { + reg_write[idx](s, v); + } else { + s->regs[idx] = v; + } + } +} + +static uint16_t mii_read_host(Mii *s, unsigned idx) +{ + trace_open_eth_mii_read(idx, s->regs[idx]); + return s->regs[idx]; +} + +/* OpenCores Ethernet registers */ +enum { + MODER, + INT_SOURCE, + INT_MASK, + IPGT, + IPGR1, + IPGR2, + PACKETLEN, + COLLCONF, + TX_BD_NUM, + CTRLMODER, + MIIMODER, + MIICOMMAND, + MIIADDRESS, + MIITX_DATA, + MIIRX_DATA, + MIISTATUS, + MAC_ADDR0, + MAC_ADDR1, + HASH0, + HASH1, + TXCTRL, + REG_MAX, +}; + +enum { + MODER_RECSMALL = 0x10000, + MODER_PAD = 0x8000, + MODER_HUGEN = 0x4000, + MODER_RST = 0x800, + MODER_LOOPBCK = 0x80, + MODER_PRO = 0x20, + MODER_IAM = 0x10, + MODER_BRO = 0x8, + MODER_TXEN = 0x2, + MODER_RXEN = 0x1, +}; + +enum { + INT_SOURCE_RXB = 0x4, + INT_SOURCE_TXB = 0x1, +}; + +enum { + PACKETLEN_MINFL = 0xffff0000, + PACKETLEN_MINFL_LBN = 16, + PACKETLEN_MAXFL = 0xffff, + PACKETLEN_MAXFL_LBN = 0, +}; + +enum { + MIICOMMAND_WCTRLDATA = 0x4, + MIICOMMAND_RSTAT = 0x2, + MIICOMMAND_SCANSTAT = 0x1, +}; + +enum { + MIIADDRESS_RGAD = 0x1f00, + MIIADDRESS_RGAD_LBN = 8, + MIIADDRESS_FIAD = 0x1f, + MIIADDRESS_FIAD_LBN = 0, +}; + +enum { + MIITX_DATA_CTRLDATA = 0xffff, + MIITX_DATA_CTRLDATA_LBN = 0, +}; + +enum { + MIIRX_DATA_PRSD = 0xffff, + MIIRX_DATA_PRSD_LBN = 0, +}; + +enum { + MIISTATUS_LINKFAIL = 0x1, + MIISTATUS_LINKFAIL_LBN = 0, +}; + +enum { + MAC_ADDR0_BYTE2 = 0xff000000, + MAC_ADDR0_BYTE2_LBN = 24, + MAC_ADDR0_BYTE3 = 0xff0000, + MAC_ADDR0_BYTE3_LBN = 16, + MAC_ADDR0_BYTE4 = 0xff00, + MAC_ADDR0_BYTE4_LBN = 8, + MAC_ADDR0_BYTE5 = 0xff, + MAC_ADDR0_BYTE5_LBN = 0, +}; + +enum { + MAC_ADDR1_BYTE0 = 0xff00, + MAC_ADDR1_BYTE0_LBN = 8, + MAC_ADDR1_BYTE1 = 0xff, + MAC_ADDR1_BYTE1_LBN = 0, +}; + +enum { + TXD_LEN = 0xffff0000, + TXD_LEN_LBN = 16, + TXD_RD = 0x8000, + TXD_IRQ = 0x4000, + TXD_WR = 0x2000, + TXD_PAD = 0x1000, + TXD_CRC = 0x800, + TXD_UR = 0x100, + TXD_RTRY = 0xf0, + TXD_RTRY_LBN = 4, + TXD_RL = 0x8, + TXD_LC = 0x4, + TXD_DF = 0x2, + TXD_CS = 0x1, +}; + +enum { + RXD_LEN = 0xffff0000, + RXD_LEN_LBN = 16, + RXD_E = 0x8000, + RXD_IRQ = 0x4000, + RXD_WRAP = 0x2000, + RXD_CF = 0x100, + RXD_M = 0x80, + RXD_OR = 0x40, + RXD_IS = 0x20, + RXD_DN = 0x10, + RXD_TL = 0x8, + RXD_SF = 0x4, + RXD_CRC = 0x2, + RXD_LC = 0x1, +}; + +typedef struct desc { + uint32_t len_flags; + uint32_t buf_ptr; +} desc; + +#define DEFAULT_PHY 1 + +typedef struct OpenEthState { + SysBusDevice dev; + NICState *nic; + NICConf conf; + MemoryRegion reg_io; + MemoryRegion desc_io; + qemu_irq irq; + + Mii mii; + uint32_t regs[REG_MAX]; + unsigned tx_desc; + unsigned rx_desc; + desc desc[128]; +} OpenEthState; + +static desc *rx_desc(OpenEthState *s) +{ + return s->desc + s->rx_desc; +} + +static desc *tx_desc(OpenEthState *s) +{ + return s->desc + s->tx_desc; +} + +static void open_eth_update_irq(OpenEthState *s, + uint32_t old, uint32_t new) +{ + if (!old != !new) { + trace_open_eth_update_irq(new); + qemu_set_irq(s->irq, new); + } +} + +static void open_eth_int_source_write(OpenEthState *s, + uint32_t val) +{ + uint32_t old_val = s->regs[INT_SOURCE]; + + s->regs[INT_SOURCE] = val; + open_eth_update_irq(s, old_val & s->regs[INT_MASK], + s->regs[INT_SOURCE] & s->regs[INT_MASK]); +} + +static void open_eth_set_link_status(VLANClientState *nc) +{ + OpenEthState *s = DO_UPCAST(NICState, nc, nc)->opaque; + + if (GET_REGBIT(s, MIICOMMAND, SCANSTAT)) { + SET_REGFIELD(s, MIISTATUS, LINKFAIL, nc->link_down); + } + mii_set_link(&s->mii, !nc->link_down); +} + +static void open_eth_reset(void *opaque) +{ + OpenEthState *s = opaque; + + memset(s->regs, 0, sizeof(s->regs)); + s->regs[MODER] = 0xa000; + s->regs[IPGT] = 0x12; + s->regs[IPGR1] = 0xc; + s->regs[IPGR2] = 0x12; + s->regs[PACKETLEN] = 0x400600; + s->regs[COLLCONF] = 0xf003f; + s->regs[TX_BD_NUM] = 0x40; + s->regs[MIIMODER] = 0x64; + + s->tx_desc = 0; + s->rx_desc = 0x40; + + mii_reset(&s->mii); + open_eth_set_link_status(&s->nic->nc); +} + +static int open_eth_can_receive(VLANClientState *nc) +{ + OpenEthState *s = DO_UPCAST(NICState, nc, nc)->opaque; + + return GET_REGBIT(s, MODER, RXEN) && + (s->regs[TX_BD_NUM] < 0x80) && + (rx_desc(s)->len_flags & RXD_E); +} + +#define POLYNOMIAL 0x04c11db6 + +/* From FreeBSD */ +/* XXX: optimize */ +static unsigned compute_mcast_idx(const uint8_t *ep) +{ + uint32_t crc; + int carry, i, j; + uint8_t b; + + crc = 0xffffffff; + for (i = 0; i < 6; i++) { + b = *ep++; + for (j = 0; j < 8; j++) { + carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); + crc <<= 1; + b >>= 1; + if (carry) { + crc = ((crc ^ POLYNOMIAL) | carry); + } + } + } + return crc >> 26; +} + +static ssize_t open_eth_receive(VLANClientState *nc, + const uint8_t *buf, size_t size) +{ + OpenEthState *s = DO_UPCAST(NICState, nc, nc)->opaque; + size_t maxfl = GET_REGFIELD(s, PACKETLEN, MAXFL); + size_t minfl = GET_REGFIELD(s, PACKETLEN, MINFL); + bool miss = true; + + trace_open_eth_receive((unsigned)size); + + if (size >= 6) { + static const uint8_t bcast_addr[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + }; + if (memcmp(buf, bcast_addr, sizeof(bcast_addr)) == 0) { + miss = GET_REGBIT(s, MODER, BRO); + } else if ((buf[0] & 0x1) || GET_REGBIT(s, MODER, IAM)) { + unsigned mcast_idx = compute_mcast_idx(buf); + miss = !(s->regs[HASH0 + mcast_idx / 32] & + (1 << (mcast_idx % 32))); + trace_open_eth_receive_mcast( + mcast_idx, s->regs[HASH0], s->regs[HASH1]); + } else { + miss = GET_REGFIELD(s, MAC_ADDR1, BYTE0) != buf[0] || + GET_REGFIELD(s, MAC_ADDR1, BYTE1) != buf[1] || + GET_REGFIELD(s, MAC_ADDR0, BYTE2) != buf[2] || + GET_REGFIELD(s, MAC_ADDR0, BYTE3) != buf[3] || + GET_REGFIELD(s, MAC_ADDR0, BYTE4) != buf[4] || + GET_REGFIELD(s, MAC_ADDR0, BYTE5) != buf[5]; + } + } + + if (miss && !GET_REGBIT(s, MODER, PRO)) { + trace_open_eth_receive_reject(); + return size; + } + +#ifdef USE_RECSMALL + if (GET_REGBIT(s, MODER, RECSMALL) || size >= minfl) { +#else + { +#endif + desc *desc = rx_desc(s); + size_t copy_size = GET_REGBIT(s, MODER, HUGEN) ? 65536 : maxfl; + + desc->len_flags &= ~(RXD_CF | RXD_M | RXD_OR | + RXD_IS | RXD_DN | RXD_TL | RXD_SF | RXD_CRC | RXD_LC); + + if (copy_size > size) { + copy_size = size; + } + if (miss) { + desc->len_flags |= RXD_M; + } + if (size > maxfl) { + desc->len_flags |= RXD_TL; + } +#ifdef USE_RECSMALL + if (size < minfl) { + desc->len_flags |= RXD_SF; + } +#endif + + cpu_physical_memory_write(desc->buf_ptr, buf, copy_size); + + if (GET_REGBIT(s, MODER, PAD) && copy_size < minfl) { + static const uint8_t zero[65536] = {0}; + + cpu_physical_memory_write(desc->buf_ptr + copy_size, + zero, minfl - copy_size); + copy_size = minfl; + } + + SET_FIELD(desc->len_flags, RXD_LEN, copy_size); + + if ((desc->len_flags & RXD_WRAP) || s->rx_desc == 0x7f) { + s->rx_desc = s->regs[TX_BD_NUM]; + } else { + ++s->rx_desc; + } + desc->len_flags &= ~RXD_E; + + trace_open_eth_receive_desc(desc->buf_ptr, desc->len_flags); + + if (desc->len_flags & RXD_IRQ) { + open_eth_int_source_write(s, + s->regs[INT_SOURCE] | INT_SOURCE_RXB); + } + } + return size; +} + +static void open_eth_cleanup(VLANClientState *nc) +{ +} + +static NetClientInfo net_open_eth_info = { + .type = NET_CLIENT_TYPE_NIC, + .size = sizeof(NICState), + .can_receive = open_eth_can_receive, + .receive = open_eth_receive, + .cleanup = open_eth_cleanup, + .link_status_changed = open_eth_set_link_status, +}; + +static void open_eth_start_xmit(OpenEthState *s, desc *tx) +{ + uint8_t buf[65536]; + unsigned len = GET_FIELD(tx->len_flags, TXD_LEN); + unsigned tx_len = len; + + if ((tx->len_flags & TXD_PAD) && + tx_len < GET_REGFIELD(s, PACKETLEN, MINFL)) { + tx_len = GET_REGFIELD(s, PACKETLEN, MINFL); + } + if (!GET_REGBIT(s, MODER, HUGEN) && + tx_len > GET_REGFIELD(s, PACKETLEN, MAXFL)) { + tx_len = GET_REGFIELD(s, PACKETLEN, MAXFL); + } + + trace_open_eth_start_xmit(tx->buf_ptr, len, tx_len); + + if (len > tx_len) { + len = tx_len; + } + cpu_physical_memory_read(tx->buf_ptr, buf, len); + if (tx_len > len) { + memset(buf + len, 0, tx_len - len); + } + qemu_send_packet(&s->nic->nc, buf, tx_len); + + if (tx->len_flags & TXD_WR) { + s->tx_desc = 0; + } else { + ++s->tx_desc; + if (s->tx_desc >= s->regs[TX_BD_NUM]) { + s->tx_desc = 0; + } + } + tx->len_flags &= ~(TXD_RD | TXD_UR | + TXD_RTRY | TXD_RL | TXD_LC | TXD_DF | TXD_CS); + if (tx->len_flags & TXD_IRQ) { + open_eth_int_source_write(s, s->regs[INT_SOURCE] | INT_SOURCE_TXB); + } + +} + +static void open_eth_check_start_xmit(OpenEthState *s) +{ + desc *tx = tx_desc(s); + if (GET_REGBIT(s, MODER, TXEN) && s->regs[TX_BD_NUM] > 0 && + (tx->len_flags & TXD_RD) && + GET_FIELD(tx->len_flags, TXD_LEN) > 4) { + open_eth_start_xmit(s, tx); + } +} + +static uint64_t open_eth_reg_read(void *opaque, + target_phys_addr_t addr, unsigned int size) +{ + static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = { + }; + OpenEthState *s = opaque; + unsigned idx = addr / 4; + uint64_t v = 0; + + if (idx < REG_MAX) { + if (reg_read[idx]) { + v = reg_read[idx](s); + } else { + v = s->regs[idx]; + } + } + trace_open_eth_reg_read((uint32_t)addr, (uint32_t)v); + return v; +} + +static void open_eth_ro(OpenEthState *s, uint32_t val) +{ +} + +static void open_eth_moder_host_write(OpenEthState *s, uint32_t val) +{ + uint32_t set = val & ~s->regs[MODER]; + + if (set & MODER_RST) { + open_eth_reset(s); + } + + s->regs[MODER] = val; + + if (set & MODER_RXEN) { + s->rx_desc = s->regs[TX_BD_NUM]; + } + if (set & MODER_TXEN) { + s->tx_desc = 0; + open_eth_check_start_xmit(s); + } +} + +static void open_eth_int_source_host_write(OpenEthState *s, uint32_t val) +{ + uint32_t old = s->regs[INT_SOURCE]; + + s->regs[INT_SOURCE] &= ~val; + open_eth_update_irq(s, old & s->regs[INT_MASK], + s->regs[INT_SOURCE] & s->regs[INT_MASK]); +} + +static void open_eth_int_mask_host_write(OpenEthState *s, uint32_t val) +{ + uint32_t old = s->regs[INT_MASK]; + + s->regs[INT_MASK] = val; + open_eth_update_irq(s, s->regs[INT_SOURCE] & old, + s->regs[INT_SOURCE] & s->regs[INT_MASK]); +} + +static void open_eth_mii_command_host_write(OpenEthState *s, uint32_t val) +{ + unsigned fiad = GET_REGFIELD(s, MIIADDRESS, FIAD); + unsigned rgad = GET_REGFIELD(s, MIIADDRESS, RGAD); + + if (val & MIICOMMAND_WCTRLDATA) { + if (fiad == DEFAULT_PHY) { + mii_write_host(&s->mii, rgad, + GET_REGFIELD(s, MIITX_DATA, CTRLDATA)); + } + } + if (val & MIICOMMAND_RSTAT) { + if (fiad == DEFAULT_PHY) { + SET_REGFIELD(s, MIIRX_DATA, PRSD, + mii_read_host(&s->mii, rgad)); + } else { + s->regs[MIIRX_DATA] = 0xffff; + } + SET_REGFIELD(s, MIISTATUS, LINKFAIL, s->nic->nc.link_down); + } +} + +static void open_eth_mii_tx_host_write(OpenEthState *s, uint32_t val) +{ + SET_REGFIELD(s, MIITX_DATA, CTRLDATA, val); + if (GET_REGFIELD(s, MIIADDRESS, FIAD) == DEFAULT_PHY) { + mii_write_host(&s->mii, GET_REGFIELD(s, MIIADDRESS, RGAD), + GET_REGFIELD(s, MIITX_DATA, CTRLDATA)); + } +} + +static void open_eth_reg_write(void *opaque, + target_phys_addr_t addr, uint64_t val, unsigned int size) +{ + static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = { + [MODER] = open_eth_moder_host_write, + [INT_SOURCE] = open_eth_int_source_host_write, + [INT_MASK] = open_eth_int_mask_host_write, + [MIICOMMAND] = open_eth_mii_command_host_write, + [MIITX_DATA] = open_eth_mii_tx_host_write, + [MIISTATUS] = open_eth_ro, + }; + OpenEthState *s = opaque; + unsigned idx = addr / 4; + + if (idx < REG_MAX) { + trace_open_eth_reg_write((uint32_t)addr, (uint32_t)val); + if (reg_write[idx]) { + reg_write[idx](s, val); + } else { + s->regs[idx] = val; + } + } +} + +static uint64_t open_eth_desc_read(void *opaque, + target_phys_addr_t addr, unsigned int size) +{ + OpenEthState *s = opaque; + uint64_t v = 0; + + addr &= 0x3ff; + memcpy(&v, (uint8_t *)s->desc + addr, size); + trace_open_eth_desc_read((uint32_t)addr, (uint32_t)v); + return v; +} + +static void open_eth_desc_write(void *opaque, + target_phys_addr_t addr, uint64_t val, unsigned int size) +{ + OpenEthState *s = opaque; + + addr &= 0x3ff; + trace_open_eth_desc_write((uint32_t)addr, (uint32_t)val); + memcpy((uint8_t *)s->desc + addr, &val, size); + open_eth_check_start_xmit(s); +} + + +static MemoryRegionOps open_eth_reg_ops = { + .read = open_eth_reg_read, + .write = open_eth_reg_write, +}; + +static MemoryRegionOps open_eth_desc_ops = { + .read = open_eth_desc_read, + .write = open_eth_desc_write, +}; + +static int sysbus_open_eth_init(SysBusDevice *dev) +{ + OpenEthState *s = DO_UPCAST(OpenEthState, dev, dev); + + memory_region_init_io(&s->reg_io, &open_eth_reg_ops, s, + "open_eth.regs", 0x54); + sysbus_init_mmio_region(dev, &s->reg_io); + + memory_region_init_io(&s->desc_io, &open_eth_desc_ops, s, + "open_eth.desc", 0x400); + sysbus_init_mmio_region(dev, &s->desc_io); + + sysbus_init_irq(dev, &s->irq); + + s->nic = qemu_new_nic(&net_open_eth_info, &s->conf, + s->dev.qdev.info->name, s->dev.qdev.id, s); + return 0; +} + +static void qdev_open_eth_reset(DeviceState *dev) +{ + OpenEthState *d = DO_UPCAST(OpenEthState, dev.qdev, dev); + open_eth_reset(d); +} + +static SysBusDeviceInfo open_eth_info = { + .qdev.name = "open_eth", + .qdev.desc = "Opencores 10/100 Mbit Ethernet", + .qdev.size = sizeof(OpenEthState), + .qdev.reset = qdev_open_eth_reset, + .init = sysbus_open_eth_init, + .qdev.props = (Property[]) { + DEFINE_NIC_PROPERTIES(OpenEthState, conf), + DEFINE_PROP_END_OF_LIST(), + } +}; + +static void open_eth_register_devices(void) +{ + sysbus_register_withprop(&open_eth_info); +} + +device_init(open_eth_register_devices) @@ -54,16 +54,12 @@ static void static_write(void *opaque, target_phys_addr_t offset, #endif } -static CPUReadMemoryFunc * const static_readfn[] = { - static_readb, - static_readh, - static_readw, -}; - -static CPUWriteMemoryFunc * const static_writefn[] = { - static_write, - static_write, - static_write, +static const MemoryRegionOps static_ops = { + .old_mmio = { + .read = { static_readb, static_readh, static_readw, }, + .write = { static_write, static_write, static_write, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; /* Palm Tunsgten|E support */ @@ -203,34 +199,35 @@ static void palmte_init(ram_addr_t ram_size, struct omap_mpu_state_s *cpu; int flash_size = 0x00800000; int sdram_size = palmte_binfo.ram_size; - int io; static uint32_t cs0val = 0xffffffff; static uint32_t cs1val = 0x0000e1a0; static uint32_t cs2val = 0x0000e1a0; static uint32_t cs3val = 0xe1a0e1a0; int rom_size, rom_loaded = 0; DisplayState *ds = get_displaystate(); + MemoryRegion *flash = g_new(MemoryRegion, 1); + MemoryRegion *cs = g_new(MemoryRegion, 4); cpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model); /* External Flash (EMIFS) */ - cpu_register_physical_memory(OMAP_CS0_BASE, flash_size, - qemu_ram_alloc(NULL, "palmte.flash", - flash_size) | IO_MEM_ROM); - - io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(OMAP_CS0_BASE + flash_size, - OMAP_CS0_SIZE - flash_size, io); - io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io); - io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io); - io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io); + memory_region_init_ram(flash, NULL, "palmte.flash", flash_size); + memory_region_set_readonly(flash, true); + memory_region_add_subregion(address_space_mem, OMAP_CS0_BASE, flash); + + memory_region_init_io(&cs[0], &static_ops, &cs0val, "palmte-cs0", + OMAP_CS0_SIZE - flash_size); + memory_region_add_subregion(address_space_mem, OMAP_CS0_BASE + flash_size, + &cs[0]); + memory_region_init_io(&cs[1], &static_ops, &cs1val, "palmte-cs1", + OMAP_CS1_SIZE); + memory_region_add_subregion(address_space_mem, OMAP_CS1_BASE, &cs[1]); + memory_region_init_io(&cs[2], &static_ops, &cs2val, "palmte-cs2", + OMAP_CS2_SIZE); + memory_region_add_subregion(address_space_mem, OMAP_CS2_BASE, &cs[2]); + memory_region_init_io(&cs[3], &static_ops, &cs3val, "palmte-cs3", + OMAP_CS3_SIZE); + memory_region_add_subregion(address_space_mem, OMAP_CS3_BASE, &cs[3]); palmte_microwire_setup(cpu); diff --git a/hw/parallel.c b/hw/parallel.c index ecbc8c3b77..8494d94f69 100644 --- a/hw/parallel.c +++ b/hw/parallel.c @@ -448,6 +448,29 @@ static void parallel_reset(void *opaque) static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; +static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { + { 0, 8, 1, + .read = parallel_ioport_read_hw, + .write = parallel_ioport_write_hw }, + { 4, 1, 2, + .read = parallel_ioport_eppdata_read_hw2, + .write = parallel_ioport_eppdata_write_hw2 }, + { 4, 1, 4, + .read = parallel_ioport_eppdata_read_hw4, + .write = parallel_ioport_eppdata_write_hw4 }, + { 0x400, 8, 1, + .read = parallel_ioport_ecp_read, + .write = parallel_ioport_ecp_write }, + PORTIO_END_OF_LIST(), +}; + +static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { + { 0, 8, 1, + .read = parallel_ioport_read_sw, + .write = parallel_ioport_write_sw }, + PORTIO_END_OF_LIST(), +}; + static int parallel_isa_initfn(ISADevice *dev) { static int index; @@ -478,25 +501,11 @@ static int parallel_isa_initfn(ISADevice *dev) s->status = dummy; } - if (s->hw_driver) { - register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s); - register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s); - isa_init_ioport_range(dev, base, 8); - - register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s); - register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s); - register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s); - register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s); - isa_init_ioport(dev, base+4); - register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s); - register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s); - isa_init_ioport_range(dev, base+0x400, 8); - } - else { - register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s); - register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s); - isa_init_ioport_range(dev, base, 8); - } + isa_register_portio_list(dev, base, + (s->hw_driver + ? &isa_parallel_portio_hw_list[0] + : &isa_parallel_portio_sw_list[0]), + s, "parallel"); return 0; } @@ -88,17 +88,16 @@ struct e820_table { static struct e820_table e820_table; struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; -void isa_irq_handler(void *opaque, int n, int level) +void gsi_handler(void *opaque, int n, int level) { - IsaIrqState *isa = (IsaIrqState *)opaque; + GSIState *s = opaque; - DPRINTF("isa_irqs: %s irq %d\n", level? "raise" : "lower", n); - if (n < 16) { - qemu_set_irq(isa->i8259[n], level); + DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); + if (n < ISA_NUM_IRQS) { + qemu_set_irq(s->i8259_irq[n], level); } - if (isa->ioapic) - qemu_set_irq(isa->ioapic[n], level); -}; + qemu_set_irq(s->ioapic_irq[n], level); +} static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) { @@ -156,9 +155,6 @@ int cpu_get_pic_interrupt(CPUState *env) intno = apic_get_interrupt(env->apic_state); if (intno >= 0) { - /* set irq request if a PIC irq is still pending */ - /* XXX: improve that */ - pic_update_irq(isa_pic); return intno; } /* read the irq from the PIC */ @@ -428,6 +424,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, /* port 92 stuff: could be split off */ typedef struct Port92State { ISADevice dev; + MemoryRegion io; uint8_t outport; qemu_irq *a20_out; } Port92State; @@ -479,13 +476,22 @@ static void port92_reset(DeviceState *d) s->outport &= ~1; } +static const MemoryRegionPortio port92_portio[] = { + { 0, 1, 1, .read = port92_read, .write = port92_write }, + PORTIO_END_OF_LIST(), +}; + +static const MemoryRegionOps port92_ops = { + .old_portio = port92_portio +}; + static int port92_initfn(ISADevice *dev) { Port92State *s = DO_UPCAST(Port92State, dev, dev); - register_ioport_read(0x92, 1, 1, port92_read, s); - register_ioport_write(0x92, 1, 1, port92_write, s); - isa_init_ioport(dev, 0x92); + memory_region_init_io(&s->io, &port92_ops, s, "port92", 1); + isa_register_ioport(dev, &s->io, 0x92); + s->outport = 0; return 0; } @@ -1116,7 +1122,7 @@ static void cpu_request_exit(void *opaque, int irq, int level) } } -void pc_basic_device_init(qemu_irq *isa_irq, +void pc_basic_device_init(qemu_irq *gsi, ISADevice **rtc_state, bool no_vmport) { @@ -1135,8 +1141,8 @@ void pc_basic_device_init(qemu_irq *isa_irq, DeviceState *hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); if (hpet) { - for (i = 0; i < 24; i++) { - sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]); + for (i = 0; i < GSI_NUM_PINS; i++) { + sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]); } rtc_irq = qdev_get_gpio_in(hpet, 0); } @@ -8,6 +8,7 @@ #include "fdc.h" #include "net.h" #include "memory.h" +#include "ioapic.h" /* PC-style peripherals (also used by other machines). */ @@ -59,26 +60,24 @@ bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, /* i8259.c */ -typedef struct PicState2 PicState2; -extern PicState2 *isa_pic; -void pic_set_irq(int irq, int level); -void pic_set_irq_new(void *opaque, int irq, int level); +typedef struct PicState PicState; +extern PicState *isa_pic; qemu_irq *i8259_init(qemu_irq parent_irq); -int pic_read_irq(PicState2 *s); -void pic_update_irq(PicState2 *s); -uint32_t pic_intack_read(PicState2 *s); +int pic_read_irq(PicState *s); +int pic_get_output(PicState *s); void pic_info(Monitor *mon); void irq_info(Monitor *mon); -/* ISA */ -#define IOAPIC_NUM_PINS 0x18 +/* Global System Interrupts */ -typedef struct isa_irq_state { - qemu_irq *i8259; - qemu_irq ioapic[IOAPIC_NUM_PINS]; -} IsaIrqState; +#define GSI_NUM_PINS IOAPIC_NUM_PINS -void isa_irq_handler(void *opaque, int n, int level); +typedef struct GSIState { + qemu_irq i8259_irq[ISA_NUM_IRQS]; + qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; +} GSIState; + +void gsi_handler(void *opaque, int n, int level); /* i8254.c */ @@ -141,7 +140,7 @@ void pc_memory_init(MemoryRegion *system_memory, MemoryRegion **ram_memory); qemu_irq *pc_allocate_cpu_irq(void); void pc_vga_init(PCIBus *pci_bus); -void pc_basic_device_init(qemu_irq *isa_irq, +void pc_basic_device_init(qemu_irq *gsi, ISADevice **rtc_state, bool no_vmport); void pc_init_ne2k_isa(NICInfo *nd); diff --git a/hw/pc_piix.c b/hw/pc_piix.c index ce1c87fba9..c89042f1ce 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -53,7 +53,7 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 }; static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 }; static const int ide_irq[MAX_IDE_BUS] = { 14, 15 }; -static void ioapic_init(IsaIrqState *isa_irq_state) +static void ioapic_init(GSIState *gsi_state) { DeviceState *dev; SysBusDevice *d; @@ -65,7 +65,7 @@ static void ioapic_init(IsaIrqState *isa_irq_state) sysbus_mmio_map(d, 0, 0xfec00000); for (i = 0; i < IOAPIC_NUM_PINS; i++) { - isa_irq_state->ioapic[i] = qdev_get_gpio_in(dev, i); + gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); } } @@ -87,11 +87,11 @@ static void pc_init1(MemoryRegion *system_memory, PCII440FXState *i440fx_state; int piix3_devfn = -1; qemu_irq *cpu_irq; - qemu_irq *isa_irq; + qemu_irq *gsi; qemu_irq *i8259; qemu_irq *cmos_s3; qemu_irq *smi_irq; - IsaIrqState *isa_irq_state; + GSIState *gsi_state; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; BusState *idebus[MAX_IDE_BUS]; ISADevice *rtc_state; @@ -130,11 +130,11 @@ static void pc_init1(MemoryRegion *system_memory, pci_enabled ? rom_memory : system_memory, &ram_memory); } - isa_irq_state = g_malloc0(sizeof(*isa_irq_state)); - isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24); + gsi_state = g_malloc0(sizeof(*gsi_state)); + gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); if (pci_enabled) { - pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq, + pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, gsi, system_memory, system_io, ram_size, below_4g_mem_size, 0x100000000ULL - below_4g_mem_size, @@ -149,7 +149,7 @@ static void pc_init1(MemoryRegion *system_memory, isa_bus_new(NULL, system_io); no_hpet = 1; } - isa_bus_irqs(isa_irq); + isa_bus_irqs(gsi); if (!xen_enabled()) { cpu_irq = pc_allocate_cpu_irq(); @@ -158,12 +158,14 @@ static void pc_init1(MemoryRegion *system_memory, i8259 = xen_interrupt_controller_init(); } - isa_irq_state->i8259 = i8259; + for (i = 0; i < ISA_NUM_IRQS; i++) { + gsi_state->i8259_irq[i] = i8259[i]; + } if (pci_enabled) { - ioapic_init(isa_irq_state); + ioapic_init(gsi_state); } - pc_register_ferr_irq(isa_get_irq(13)); + pc_register_ferr_irq(gsi[13]); pc_vga_init(pci_enabled? pci_bus: NULL); @@ -172,7 +174,7 @@ static void pc_init1(MemoryRegion *system_memory, } /* init basic PC hardware */ - pc_basic_device_init(isa_irq, &rtc_state, xen_enabled()); + pc_basic_device_init(gsi, &rtc_state, xen_enabled()); for(i = 0; i < nb_nics; i++) { NICInfo *nd = &nd_table[i]; @@ -202,7 +204,7 @@ static void pc_init1(MemoryRegion *system_memory, } } - audio_init(isa_irq, pci_enabled ? pci_bus : NULL); + audio_init(gsi, pci_enabled ? pci_bus : NULL); pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, idebus[0], idebus[1], rtc_state); @@ -222,7 +224,7 @@ static void pc_init1(MemoryRegion *system_memory, smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu, 1); /* TODO: Populate SPD eeprom data. */ smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, - isa_get_irq(9), *cmos_s3, *smi_irq, + gsi[9], *cmos_s3, *smi_irq, kvm_enabled()); smbus_eeprom_init(smbus, 8, NULL, 0); } diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c index 2a0f7fd031..fb4ba29bf8 100644 --- a/hw/petalogix_ml605_mmu.c +++ b/hw/petalogix_ml605_mmu.c @@ -149,8 +149,8 @@ petalogix_ml605_init(ram_addr_t ram_size, DriveInfo *dinfo; int i; target_phys_addr_t ddr_base = MEMORY_BASEADDR; - ram_addr_t phys_lmb_bram; - ram_addr_t phys_ram; + MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); + MemoryRegion *phys_ram = g_new(MemoryRegion, 1); qemu_irq irq[32], *cpu_irq; /* init CPUs */ @@ -162,13 +162,12 @@ petalogix_ml605_init(ram_addr_t ram_size, qemu_register_reset(main_cpu_reset, env); /* Attach emulated BRAM through the LMB. */ - phys_lmb_bram = qemu_ram_alloc(NULL, "petalogix_ml605.lmb_bram", - LMB_BRAM_SIZE); - cpu_register_physical_memory(0x00000000, LMB_BRAM_SIZE, - phys_lmb_bram | IO_MEM_RAM); + memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram", + LMB_BRAM_SIZE); + memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram); - phys_ram = qemu_ram_alloc(NULL, "petalogix_ml605.ram", ram_size); - cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM); + memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size); + memory_region_add_subregion(address_space_mem, ddr_base, phys_ram); dinfo = drive_get(IF_PFLASH, 0, 0); /* 5th parameter 2 means bank-width diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c index 66fb96d8eb..17da2fd87c 100644 --- a/hw/petalogix_s3adsp1800_mmu.c +++ b/hw/petalogix_s3adsp1800_mmu.c @@ -35,6 +35,7 @@ #include "loader.h" #include "elf.h" #include "blockdev.h" +#include "exec-memory.h" #include "microblaze_pic_cpu.h" @@ -125,9 +126,10 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size, DriveInfo *dinfo; int i; target_phys_addr_t ddr_base = 0x90000000; - ram_addr_t phys_lmb_bram; - ram_addr_t phys_ram; + MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); + MemoryRegion *phys_ram = g_new(MemoryRegion, 1); qemu_irq irq[32], *cpu_irq; + MemoryRegion *sysmem = get_system_memory(); /* init CPUs */ if (cpu_model == NULL) { @@ -139,13 +141,13 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size, qemu_register_reset(main_cpu_reset, env); /* Attach emulated BRAM through the LMB. */ - phys_lmb_bram = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.lmb_bram", - LMB_BRAM_SIZE); - cpu_register_physical_memory(0x00000000, LMB_BRAM_SIZE, - phys_lmb_bram | IO_MEM_RAM); + memory_region_init_ram(phys_lmb_bram, NULL, + "petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE); + memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram); - phys_ram = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.ram", ram_size); - cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM); + memory_region_init_ram(phys_ram, NULL, "petalogix_s3adsp1800.ram", + ram_size); + memory_region_add_subregion(sysmem, ddr_base, phys_ram); dinfo = drive_get(IF_PFLASH, 0, 0); pflash_cfi01_register(0xa0000000, diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c index 9136288d08..672e9347ac 100644 --- a/hw/ppc405_boards.c +++ b/hw/ppc405_boards.c @@ -137,16 +137,16 @@ static void ref405ep_fpga_writel (void *opaque, ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); } -static CPUReadMemoryFunc * const ref405ep_fpga_read[] = { - &ref405ep_fpga_readb, - &ref405ep_fpga_readw, - &ref405ep_fpga_readl, -}; - -static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = { - &ref405ep_fpga_writeb, - &ref405ep_fpga_writew, - &ref405ep_fpga_writel, +static const MemoryRegionOps ref405ep_fpga_ops = { + .old_mmio = { + .read = { + ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, + }, + .write = { + ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel, + }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void ref405ep_fpga_reset (void *opaque) @@ -158,16 +158,15 @@ static void ref405ep_fpga_reset (void *opaque) fpga->reg1 = 0x0F; } -static void ref405ep_fpga_init (uint32_t base) +static void ref405ep_fpga_init (MemoryRegion *sysmem, uint32_t base) { ref405ep_fpga_t *fpga; - int fpga_memory; + MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); fpga = g_malloc0(sizeof(ref405ep_fpga_t)); - fpga_memory = cpu_register_io_memory(ref405ep_fpga_read, - ref405ep_fpga_write, fpga, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x00000100, fpga_memory); + memory_region_init_io(fpga_memory, &ref405ep_fpga_ops, fpga, + "fpga", 0x00000100); + memory_region_add_subregion(sysmem, base, fpga_memory); qemu_register_reset(&ref405ep_fpga_reset, fpga); } @@ -183,7 +182,8 @@ static void ref405ep_init (ram_addr_t ram_size, CPUPPCState *env; qemu_irq *pic; MemoryRegion *bios; - ram_addr_t sram_offset, bdloc; + MemoryRegion *sram = g_new(MemoryRegion, 1); + ram_addr_t bdloc; MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); target_phys_addr_t ram_bases[2], ram_sizes[2]; target_ulong sram_size; @@ -195,6 +195,7 @@ static void ref405ep_init (ram_addr_t ram_size, int linux_boot; int fl_idx, fl_sectors, len; DriveInfo *dinfo; + MemoryRegion *sysmem = get_system_memory(); /* XXX: fix this */ memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000); @@ -207,17 +208,12 @@ static void ref405ep_init (ram_addr_t ram_size, #ifdef DEBUG_BOARD_INIT printf("%s: register cpu\n", __func__); #endif - env = ppc405ep_init(get_system_memory(), ram_memories, ram_bases, ram_sizes, + env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 33333333, &pic, kernel_filename == NULL ? 0 : 1); /* allocate SRAM */ sram_size = 512 * 1024; - sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size); -#ifdef DEBUG_BOARD_INIT - printf("%s: register SRAM at offset " RAM_ADDR_FMT "\n", - __func__, sram_offset); -#endif - cpu_register_physical_memory(0xFFF00000, sram_size, - sram_offset | IO_MEM_RAM); + memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size); + memory_region_add_subregion(sysmem, 0xFFF00000, sram); /* allocate and load BIOS */ #ifdef DEBUG_BOARD_INIT printf("%s: register BIOS\n", __func__); @@ -264,14 +260,13 @@ static void ref405ep_init (ram_addr_t ram_size, } bios_size = (bios_size + 0xfff) & ~0xfff; memory_region_set_readonly(bios, true); - memory_region_add_subregion(get_system_memory(), - (uint32_t)(-bios_size), bios); + memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); } /* Register FPGA */ #ifdef DEBUG_BOARD_INIT printf("%s: register FPGA\n", __func__); #endif - ref405ep_fpga_init(0xF0300000); + ref405ep_fpga_init(sysmem, 0xF0300000); /* Register NVRAM */ #ifdef DEBUG_BOARD_INIT printf("%s: register NVRAM\n", __func__); @@ -469,16 +464,12 @@ static void taihu_cpld_writel (void *opaque, taihu_cpld_writeb(opaque, addr + 3, value & 0xFF); } -static CPUReadMemoryFunc * const taihu_cpld_read[] = { - &taihu_cpld_readb, - &taihu_cpld_readw, - &taihu_cpld_readl, -}; - -static CPUWriteMemoryFunc * const taihu_cpld_write[] = { - &taihu_cpld_writeb, - &taihu_cpld_writew, - &taihu_cpld_writel, +static const MemoryRegionOps taihu_cpld_ops = { + .old_mmio = { + .read = { taihu_cpld_readb, taihu_cpld_readw, taihu_cpld_readl, }, + .write = { taihu_cpld_writeb, taihu_cpld_writew, taihu_cpld_writel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void taihu_cpld_reset (void *opaque) @@ -490,16 +481,14 @@ static void taihu_cpld_reset (void *opaque) cpld->reg1 = 0x80; } -static void taihu_cpld_init (uint32_t base) +static void taihu_cpld_init (MemoryRegion *sysmem, uint32_t base) { taihu_cpld_t *cpld; - int cpld_memory; + MemoryRegion *cpld_memory = g_new(MemoryRegion, 1); cpld = g_malloc0(sizeof(taihu_cpld_t)); - cpld_memory = cpu_register_io_memory(taihu_cpld_read, - taihu_cpld_write, cpld, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x00000100, cpld_memory); + memory_region_init_io(cpld_memory, &taihu_cpld_ops, cpld, "cpld", 0x100); + memory_region_add_subregion(sysmem, base, cpld_memory); qemu_register_reset(&taihu_cpld_reset, cpld); } @@ -512,6 +501,7 @@ static void taihu_405ep_init(ram_addr_t ram_size, { char *filename; qemu_irq *pic; + MemoryRegion *sysmem = get_system_memory(); MemoryRegion *bios; MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); target_phys_addr_t ram_bases[2], ram_sizes[2]; @@ -535,7 +525,7 @@ static void taihu_405ep_init(ram_addr_t ram_size, #ifdef DEBUG_BOARD_INIT printf("%s: register cpu\n", __func__); #endif - ppc405ep_init(get_system_memory(), ram_memories, ram_bases, ram_sizes, + ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 33333333, &pic, kernel_filename == NULL ? 0 : 1); /* allocate and load BIOS */ #ifdef DEBUG_BOARD_INIT @@ -585,8 +575,7 @@ static void taihu_405ep_init(ram_addr_t ram_size, } bios_size = (bios_size + 0xfff) & ~0xfff; memory_region_set_readonly(bios, true); - memory_region_add_subregion(get_system_memory(), (uint32_t)(-bios_size), - bios); + memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); } /* Register Linux flash */ dinfo = drive_get(IF_PFLASH, 0, fl_idx); @@ -611,7 +600,7 @@ static void taihu_405ep_init(ram_addr_t ram_size, #ifdef DEBUG_BOARD_INIT printf("%s: register CPLD\n", __func__); #endif - taihu_cpld_init(0x50100000); + taihu_cpld_init(sysmem, 0x50100000); /* Load kernel */ linux_boot = (kernel_filename != NULL); if (linux_boot) { diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c index b9a50db3fa..8c84f9e9a5 100644 --- a/hw/ppc_newworld.c +++ b/hw/ppc_newworld.c @@ -84,12 +84,13 @@ #endif /* UniN device */ -static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +static void unin_write(void *opaque, target_phys_addr_t addr, uint64_t value, + unsigned size) { - UNIN_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n", addr, value); + UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value); } -static uint32_t unin_readl (void *opaque, target_phys_addr_t addr) +static uint64_t unin_read(void *opaque, target_phys_addr_t addr, unsigned size) { uint32_t value; @@ -99,16 +100,10 @@ static uint32_t unin_readl (void *opaque, target_phys_addr_t addr) return value; } -static CPUWriteMemoryFunc * const unin_write[] = { - &unin_writel, - &unin_writel, - &unin_writel, -}; - -static CPUReadMemoryFunc * const unin_read[] = { - &unin_readl, - &unin_readl, - &unin_readl, +static const MemoryRegionOps unin_ops = { + .read = unin_read, + .write = unin_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int fw_cfg_boot_set(void *opaque, const char *boot_device) @@ -138,9 +133,9 @@ static void ppc_core99_init (ram_addr_t ram_size, CPUState *env = NULL; char *filename; qemu_irq *pic, **openpic_irqs; - int unin_memory; + MemoryRegion *unin_memory = g_new(MemoryRegion, 1); int linux_boot, i; - ram_addr_t ram_offset, bios_offset; + MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); target_phys_addr_t kernel_base, initrd_base, cmdline_base = 0; long kernel_size, initrd_size; PCIBus *pci_bus; @@ -176,15 +171,16 @@ static void ppc_core99_init (ram_addr_t ram_size, } /* allocate RAM */ - ram_offset = qemu_ram_alloc(NULL, "ppc_core99.ram", ram_size); - cpu_register_physical_memory(0, ram_size, ram_offset); + memory_region_init_ram(ram, NULL, "ppc_core99.ram", ram_size); + memory_region_add_subregion(get_system_memory(), 0, ram); /* allocate and load BIOS */ - bios_offset = qemu_ram_alloc(NULL, "ppc_core99.bios", BIOS_SIZE); + memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE); if (bios_name == NULL) bios_name = PROM_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); - cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM); + memory_region_set_readonly(bios, true); + memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); /* Load OpenBIOS (ELF) */ if (filename) { @@ -267,9 +263,8 @@ static void ppc_core99_init (ram_addr_t ram_size, isa_mmio_init(0xf2000000, 0x00800000); /* UniN init */ - unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory); + memory_region_init_io(unin_memory, &unin_ops, NULL, "unin", 0x1000); + memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); openpic_irqs[0] = diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index d26049b1d1..6427baa562 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -130,7 +130,7 @@ static inline uint32_t _PPC_intack_read(target_phys_addr_t addr) uint32_t retval = 0; if ((addr & 0xf) == 0) - retval = pic_intack_read(isa_pic); + retval = pic_read_irq(isa_pic); #if 0 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, retval); diff --git a/hw/qdev-properties.c b/hw/qdev-properties.c index e0e54aa857..f0b811c806 100644 --- a/hw/qdev-properties.c +++ b/hw/qdev-properties.c @@ -93,6 +93,35 @@ PropertyInfo qdev_prop_uint8 = { .print = print_uint8, }; +/* --- 8bit hex value --- */ + +static int parse_hex8(DeviceState *dev, Property *prop, const char *str) +{ + uint8_t *ptr = qdev_get_prop_ptr(dev, prop); + char *end; + + *ptr = strtoul(str, &end, 16); + if ((*end != '\0') || (end == str)) { + return -EINVAL; + } + + return 0; +} + +static int print_hex8(DeviceState *dev, Property *prop, char *dest, size_t len) +{ + uint8_t *ptr = qdev_get_prop_ptr(dev, prop); + return snprintf(dest, len, "0x%" PRIx8, *ptr); +} + +PropertyInfo qdev_prop_hex8 = { + .name = "hex8", + .type = PROP_TYPE_UINT8, + .size = sizeof(uint8_t), + .parse = parse_hex8, + .print = print_hex8, +}; + /* --- 16bit integer --- */ static int parse_uint16(DeviceState *dev, Property *prop, const char *str) @@ -224,6 +224,7 @@ extern PropertyInfo qdev_prop_uint16; extern PropertyInfo qdev_prop_uint32; extern PropertyInfo qdev_prop_int32; extern PropertyInfo qdev_prop_uint64; +extern PropertyInfo qdev_prop_hex8; extern PropertyInfo qdev_prop_hex32; extern PropertyInfo qdev_prop_hex64; extern PropertyInfo qdev_prop_string; @@ -267,6 +268,8 @@ extern PropertyInfo qdev_prop_pci_devfn; DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_int32, int32_t) #define DEFINE_PROP_UINT64(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_uint64, uint64_t) +#define DEFINE_PROP_HEX8(_n, _s, _f, _d) \ + DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_hex8, uint8_t) #define DEFINE_PROP_HEX32(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_hex32, uint32_t) #define DEFINE_PROP_HEX64(_n, _s, _f, _d) \ @@ -1601,7 +1601,7 @@ static int qxl_init_primary(PCIDevice *dev) ram_size = 32 * 1024 * 1024; } vga_common_init(vga, ram_size); - vga_init(vga, pci_address_space(dev)); + vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false); register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga); register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write, vga); register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write, vga); diff --git a/hw/realview.c b/hw/realview.c index 549bb150c6..11ffb8a824 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -272,8 +272,16 @@ static void realview_init(ram_addr_t ram_size, sysbus_create_simple("pl031", 0x10017000, pic[10]); if (!is_pb) { - dev = sysbus_create_varargs("realview_pci", 0x60000000, - pic[48], pic[49], pic[50], pic[51], NULL); + dev = qdev_create(NULL, "realview_pci"); + busdev = sysbus_from_qdev(dev); + qdev_init_nofail(dev); + sysbus_mmio_map(busdev, 0, 0x61000000); /* PCI self-config */ + sysbus_mmio_map(busdev, 1, 0x62000000); /* PCI config */ + sysbus_mmio_map(busdev, 2, 0x63000000); /* PCI I/O */ + sysbus_connect_irq(busdev, 0, pic[48]); + sysbus_connect_irq(busdev, 1, pic[49]); + sysbus_connect_irq(busdev, 2, pic[50]); + sysbus_connect_irq(busdev, 3, pic[51]); pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); if (usb_enabled) { usb_ohci_init_pci(pci_bus, -1); diff --git a/hw/s390-virtio.c b/hw/s390-virtio.c index acbf02604b..778cffe39c 100644 --- a/hw/s390-virtio.c +++ b/hw/s390-virtio.c @@ -62,17 +62,6 @@ static VirtIOS390Bus *s390_bus; static CPUState **ipi_states; -void irq_info(Monitor *mon); -void pic_info(Monitor *mon); - -void irq_info(Monitor *mon) -{ -} - -void pic_info(Monitor *mon) -{ -} - CPUState *s390_cpu_addr2state(uint16_t cpu_addr) { if (cpu_addr >= smp_cpus) { @@ -1341,12 +1341,21 @@ static const VMStateDescription vmstate_sb16 = { } }; +static const MemoryRegionPortio sb16_ioport_list[] = { + { 4, 1, 1, .write = mixer_write_indexb }, + { 4, 1, 2, .write = mixer_write_indexw }, + { 5, 1, 1, .read = mixer_read, .write = mixer_write_datab }, + { 6, 1, 1, .read = dsp_read, .write = dsp_write }, + { 10, 1, 1, .read = dsp_read }, + { 12, 1, 1, .write = dsp_write }, + { 12, 4, 1, .read = dsp_read }, + PORTIO_END_OF_LIST(), +}; + + static int sb16_initfn (ISADevice *dev) { - static const uint8_t dsp_write_ports[] = {0x6, 0xc}; - static const uint8_t dsp_read_ports[] = {0x6, 0xa, 0xc, 0xd, 0xe, 0xf}; SB16State *s; - int i; s = DO_UPCAST (SB16State, dev, dev); @@ -1366,22 +1375,7 @@ static int sb16_initfn (ISADevice *dev) dolog ("warning: Could not create auxiliary timer\n"); } - for (i = 0; i < ARRAY_SIZE (dsp_write_ports); i++) { - register_ioport_write (s->port + dsp_write_ports[i], 1, 1, dsp_write, s); - isa_init_ioport (dev, s->port + dsp_write_ports[i]); - } - - for (i = 0; i < ARRAY_SIZE (dsp_read_ports); i++) { - register_ioport_read (s->port + dsp_read_ports[i], 1, 1, dsp_read, s); - isa_init_ioport (dev, s->port + dsp_read_ports[i]); - } - - register_ioport_write (s->port + 0x4, 1, 1, mixer_write_indexb, s); - register_ioport_write (s->port + 0x4, 1, 2, mixer_write_indexw, s); - isa_init_ioport (dev, s->port + 0x4); - register_ioport_read (s->port + 0x5, 1, 1, mixer_read, s); - register_ioport_write (s->port + 0x5, 1, 1, mixer_write_datab, s); - isa_init_ioport (dev, s->port + 0x5); + isa_register_portio_list (dev, s->port, sb16_ioport_list, s, "sb16"); DMA_register_channel (s->hdma, SB_read_DMA, s); DMA_register_channel (s->dma, SB_read_DMA, s); diff --git a/hw/scsi-disk.c b/hw/scsi-disk.c index 4f681ef092..69095780ac 100644 --- a/hw/scsi-disk.c +++ b/hw/scsi-disk.c @@ -228,6 +228,7 @@ static int scsi_handle_rw_error(SCSIDiskReq *r, int error, int type) bdrv_mon_event(s->bs, BDRV_ACTION_STOP, is_read); vm_stop(RUN_STATE_IO_ERROR); + bdrv_iostatus_set_err(s->bs, error); } else { switch (error) { case ENOMEM: @@ -1260,6 +1261,7 @@ static int scsi_initfn(SCSIDevice *dev, uint8_t scsi_type) s->qdev.type = scsi_type; qemu_add_vm_change_state_handler(scsi_dma_restart_cb, s); + bdrv_iostatus_enable(s->bs); add_boot_device_path(s->qdev.conf.bootindex, &dev->qdev, ",0"); return 0; } @@ -28,7 +28,6 @@ More information in target-sh4/README.sh4 */ #include "hw.h" -#include "pc.h" #include "sh.h" #include "sysemu.h" #include "boards.h" @@ -37,16 +36,6 @@ #define BIOS_FILENAME "shix_bios.bin" #define BIOS_ADDRESS 0xA0000000 -void irq_info(Monitor *mon) -{ - /* XXXXX */ -} - -void pic_info(Monitor *mon) -{ - /* XXXXX */ -} - static void shix_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, diff --git a/hw/sun4m.c b/hw/sun4m.c index dcaed38773..71bf648e69 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -216,13 +216,13 @@ static void nvram_init(M48t59State *nvram, uint8_t *macaddr, static DeviceState *slavio_intctl; -void pic_info(Monitor *mon) +void sun4m_pic_info(Monitor *mon) { if (slavio_intctl) slavio_pic_info(mon, slavio_intctl); } -void irq_info(Monitor *mon) +void sun4m_irq_info(Monitor *mon) { if (slavio_intctl) slavio_irq_info(mon, slavio_intctl); diff --git a/hw/sun4m.h b/hw/sun4m.h index ce97ee5a79..504c3af413 100644 --- a/hw/sun4m.h +++ b/hw/sun4m.h @@ -30,6 +30,10 @@ void slavio_irq_info(Monitor *mon, DeviceState *dev); void sun4c_pic_info(Monitor *mon, void *opaque); void sun4c_irq_info(Monitor *mon, void *opaque); +/* sun4m.c */ +void sun4m_pic_info(Monitor *mon); +void sun4m_irq_info(Monitor *mon); + /* sparc32_dma.c */ #include "sparc32_dma.h" diff --git a/hw/sun4u.c b/hw/sun4u.c index 88c633d491..96fc3d0488 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -243,14 +243,6 @@ static unsigned long sun4u_load_kernel(const char *kernel_filename, return kernel_size; } -void pic_info(Monitor *mon) -{ -} - -void irq_info(Monitor *mon) -{ -} - void cpu_check_irqs(CPUState *env) { uint32_t pil = env->pil_in | diff --git a/hw/usb-ehci.c b/hw/usb-ehci.c index 27376a2351..bd374c1de6 100644 --- a/hw/usb-ehci.c +++ b/hw/usb-ehci.c @@ -880,6 +880,7 @@ static void ehci_reset(void *opaque) } if (devs[i] && devs[i]->attached) { usb_attach(&s->ports[i]); + usb_send_msg(devs[i], USB_MSG_RESET); } } ehci_queues_rip_all(s); @@ -978,8 +979,7 @@ static void handle_port_status_write(EHCIState *s, int port, uint32_t val) if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { trace_usb_ehci_port_reset(port, 0); if (dev && dev->attached) { - usb_attach(&s->ports[port]); - usb_send_msg(dev, USB_MSG_RESET); + usb_reset(&s->ports[port]); *portsc &= ~PORTSC_CSC; } diff --git a/hw/usb-hid.c b/hw/usb-hid.c index ba79466401..a110c74dda 100644 --- a/hw/usb-hid.c +++ b/hw/usb-hid.c @@ -527,10 +527,21 @@ static int usb_keyboard_initfn(USBDevice *dev) return usb_hid_initfn(dev, HID_KEYBOARD); } +static int usb_ptr_post_load(void *opaque, int version_id) +{ + USBHIDState *s = opaque; + + if (s->dev.remote_wakeup) { + hid_pointer_activate(&s->hid); + } + return 0; +} + static const VMStateDescription vmstate_usb_ptr = { .name = "usb-ptr", .version_id = 1, .minimum_version_id = 1, + .post_load = usb_ptr_post_load, .fields = (VMStateField []) { VMSTATE_USB_DEVICE(dev, USBHIDState), VMSTATE_HID_POINTER_DEVICE(hid, USBHIDState), diff --git a/hw/usb-hub.c b/hw/usb-hub.c index 286e3ad85d..09c65160c2 100644 --- a/hw/usb-hub.c +++ b/hw/usb-hub.c @@ -207,10 +207,14 @@ static void usb_hub_complete(USBPort *port, USBPacket *packet) /* * Just pass it along upstream for now. * - * If we ever inplement usb 2.0 split transactions this will + * If we ever implement usb 2.0 split transactions this will * become a little more complicated ... + * + * Can't use usb_packet_complete() here because packet->owner is + * cleared already, go call the ->complete() callback directly + * instead. */ - usb_packet_complete(&s->dev, packet); + s->dev.port->ops->complete(s->dev.port, packet); } static void usb_hub_handle_reset(USBDevice *dev) @@ -289,7 +293,7 @@ static int usb_hub_handle_control(USBDevice *dev, USBPacket *p, port->wPortStatus |= PORT_STAT_SUSPEND; break; case PORT_RESET: - if (dev) { + if (dev && dev->attached) { usb_send_msg(dev, USB_MSG_RESET); port->wPortChange |= PORT_STAT_C_RESET; /* set enable bit */ @@ -429,7 +433,7 @@ static int usb_hub_broadcast_packet(USBHubState *s, USBPacket *p) for(i = 0; i < NUM_PORTS; i++) { port = &s->ports[i]; dev = port->port.dev; - if (dev && (port->wPortStatus & PORT_STAT_ENABLE)) { + if (dev && dev->attached && (port->wPortStatus & PORT_STAT_ENABLE)) { ret = usb_handle_packet(dev, p); if (ret != USB_RET_NODEV) { return ret; diff --git a/hw/usb-msd.c b/hw/usb-msd.c index e92434cc94..08d2d2ac77 100644 --- a/hw/usb-msd.c +++ b/hw/usb-msd.c @@ -325,7 +325,10 @@ static int usb_msd_handle_control(USBDevice *dev, USBPacket *p, static void usb_msd_cancel_io(USBDevice *dev, USBPacket *p) { MSDState *s = DO_UPCAST(MSDState, dev, dev); - scsi_req_cancel(s->req); + + if (s->req) { + scsi_req_cancel(s->req); + } } static int usb_msd_handle_data(USBDevice *dev, USBPacket *p) diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c index c3be65a2e9..c2981c59a4 100644 --- a/hw/usb-ohci.c +++ b/hw/usb-ohci.c @@ -150,7 +150,7 @@ static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev); #define OHCI_TD_DI_SHIFT 21 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) #define OHCI_TD_T0 (1<<24) -#define OHCI_TD_T1 (1<<24) +#define OHCI_TD_T1 (1<<25) #define OHCI_TD_EC_SHIFT 26 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) #define OHCI_TD_CC_SHIFT 28 @@ -449,7 +449,7 @@ static void ohci_reset(void *opaque) port = &ohci->rhport[i]; port->ctrl = 0; if (port->port.dev && port->port.dev->attached) { - usb_attach(&port->port); + usb_reset(&port->port); } } if (ohci->async_td) { @@ -872,7 +872,7 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) { int dir; - size_t len = 0; + size_t len = 0, pktlen = 0; #ifdef DEBUG_PACKET const char *str = NULL; #endif @@ -940,20 +940,30 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) len = (td.be - td.cbp) + 1; } - if (len && dir != OHCI_TD_DIR_IN && !completion) { - ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0); + pktlen = len; + if (len && dir != OHCI_TD_DIR_IN) { + /* The endpoint may not allow us to transfer it all now */ + pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT; + if (pktlen > len) { + pktlen = len; + } + if (!completion) { + ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen, 0); + } } } flag_r = (td.flags & OHCI_TD_R) != 0; #ifdef DEBUG_PACKET - DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n", - addr, (int64_t)len, str, flag_r, td.cbp, td.be); + DPRINTF(" TD @ 0x%.8x %" PRId64 " of %" PRId64 + " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n", + addr, (int64_t)pktlen, (int64_t)len, str, flag_r, td.cbp, td.be); - if (len > 0 && dir != OHCI_TD_DIR_IN) { + if (pktlen > 0 && dir != OHCI_TD_DIR_IN) { DPRINTF(" data:"); - for (i = 0; i < len; i++) + for (i = 0; i < pktlen; i++) { printf(" %.2x", ohci->usb_buf[i]); + } DPRINTF("\n"); } #endif @@ -982,7 +992,7 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) usb_packet_setup(&ohci->usb_packet, pid, OHCI_BM(ed->flags, ED_FA), OHCI_BM(ed->flags, ED_EN)); - usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len); + usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen); ret = usb_handle_packet(dev, &ohci->usb_packet); if (ret != USB_RET_NODEV) break; @@ -1005,12 +1015,12 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) DPRINTF("\n"); #endif } else { - ret = len; + ret = pktlen; } } /* Writeback */ - if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { + if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { /* Transmission succeeded. */ if (ret == len) { td.cbp = 0; @@ -1026,6 +1036,12 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); OHCI_SET_BM(td.flags, TD_EC, 0); + if ((dir != OHCI_TD_DIR_IN) && (ret != len)) { + /* Partial packet transfer: TD not ready to retire yet */ + goto exit_no_retire; + } + + /* Setting ED_C is part of the TD retirement process */ ed->head &= ~OHCI_ED_C; if (td.flags & OHCI_TD_T0) ed->head |= OHCI_ED_C; @@ -1066,6 +1082,7 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) i = OHCI_BM(td.flags, TD_DI); if (i < ohci->done_count) ohci->done_count = i; +exit_no_retire: ohci_put_td(ohci, addr, &td); return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR; } diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c index 17992cf003..171d7870b7 100644 --- a/hw/usb-uhci.c +++ b/hw/usb-uhci.c @@ -341,7 +341,7 @@ static void uhci_reset(void *opaque) port = &s->ports[i]; port->ctrl = 0x0080; if (port->port.dev && port->port.dev->attached) { - usb_attach(&port->port); + usb_reset(&port->port); } } @@ -33,6 +33,7 @@ void usb_attach(USBPort *port) assert(dev != NULL); assert(dev->attached); + assert(dev->state == USB_STATE_NOTATTACHED); port->ops->attach(port); usb_send_msg(dev, USB_MSG_ATTACH); } @@ -42,10 +43,21 @@ void usb_detach(USBPort *port) USBDevice *dev = port->dev; assert(dev != NULL); + assert(dev->state != USB_STATE_NOTATTACHED); port->ops->detach(port); usb_send_msg(dev, USB_MSG_DETACH); } +void usb_reset(USBPort *port) +{ + USBDevice *dev = port->dev; + + assert(dev != NULL); + usb_detach(port); + usb_attach(port); + usb_send_msg(dev, USB_MSG_RESET); +} + void usb_wakeup(USBDevice *dev) { if (dev->remote_wakeup && dev->port && dev->port->ops->wakeup) { @@ -306,6 +306,7 @@ void usb_cancel_packet(USBPacket * p); void usb_attach(USBPort *port); void usb_detach(USBPort *port); +void usb_reset(USBPort *port); void usb_wakeup(USBDevice *dev); int usb_generic_handle_packet(USBDevice *s, USBPacket *p); void usb_generic_async_ctrl_complete(USBDevice *s, USBPacket *p); diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c index 98e56f1610..8a88696f2c 100644 --- a/hw/versatile_pci.c +++ b/hw/versatile_pci.c @@ -58,38 +58,6 @@ static void pci_vpb_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(pic[irq_num], level); } - -static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base) -{ - PCIVPBState *s = (PCIVPBState *)dev; - /* Selfconfig area. */ - memory_region_add_subregion(get_system_memory(), base + 0x01000000, - &s->mem_config); - /* Normal config area. */ - memory_region_add_subregion(get_system_memory(), base + 0x02000000, - &s->mem_config2); - - if (s->realview) { - /* IO memory area. */ - memory_region_add_subregion(get_system_memory(), base + 0x03000000, - &s->isa); - } -} - -static void pci_vpb_unmap(SysBusDevice *dev, target_phys_addr_t base) -{ - PCIVPBState *s = (PCIVPBState *)dev; - /* Selfconfig area. */ - memory_region_del_subregion(get_system_memory(), &s->mem_config); - /* Normal config area. */ - memory_region_del_subregion(get_system_memory(), &s->mem_config2); - - if (s->realview) { - /* IO memory area. */ - memory_region_del_subregion(get_system_memory(), &s->isa); - } -} - static int pci_vpb_init(SysBusDevice *dev) { PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev); @@ -106,16 +74,22 @@ static int pci_vpb_init(SysBusDevice *dev) /* ??? Register memory space. */ + /* Our memory regions are: + * 0 : PCI self config window + * 1 : PCI config window + * 2 : PCI IO window (realview_pci only) + */ memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus, "pci-vpb-selfconfig", 0x1000000); + sysbus_init_mmio_region(dev, &s->mem_config); memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus, "pci-vpb-config", 0x1000000); + sysbus_init_mmio_region(dev, &s->mem_config2); if (s->realview) { isa_mmio_setup(&s->isa, 0x0100000); + sysbus_init_mmio_region(dev, &s->isa); } - sysbus_init_mmio_cb2(dev, pci_vpb_map, pci_vpb_unmap); - pci_create_simple(bus, -1, "versatile_pci_host"); return 0; } diff --git a/hw/versatilepb.c b/hw/versatilepb.c index 49f8f5fc56..68402cc479 100644 --- a/hw/versatilepb.c +++ b/hw/versatilepb.c @@ -181,6 +181,7 @@ static void versatile_init(ram_addr_t ram_size, qemu_irq pic[32]; qemu_irq sic[32]; DeviceState *dev, *sysctl; + SysBusDevice *busdev; PCIBus *pci_bus; NICInfo *nd; int n; @@ -219,8 +220,15 @@ static void versatile_init(ram_addr_t ram_size, sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); - dev = sysbus_create_varargs("versatile_pci", 0x40000000, - sic[27], sic[28], sic[29], sic[30], NULL); + dev = qdev_create(NULL, "versatile_pci"); + busdev = sysbus_from_qdev(dev); + qdev_init_nofail(dev); + sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */ + sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */ + sysbus_connect_irq(busdev, 0, sic[27]); + sysbus_connect_irq(busdev, 1, sic[28]); + sysbus_connect_irq(busdev, 2, sic[29]); + sysbus_connect_irq(busdev, 3, sic[30]); pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); /* The Versatile PCI bridge does not provide access to PCI IO space, diff --git a/hw/vga-isa.c b/hw/vga-isa.c index 6b5c8ed970..4825313f67 100644 --- a/hw/vga-isa.c +++ b/hw/vga-isa.c @@ -47,24 +47,19 @@ static int vga_initfn(ISADevice *dev) ISAVGAState *d = DO_UPCAST(ISAVGAState, dev, dev); VGACommonState *s = &d->state; MemoryRegion *vga_io_memory; + const MemoryRegionPortio *vga_ports, *vbe_ports; vga_common_init(s, VGA_RAM_SIZE); s->legacy_address_space = isa_address_space(dev); - vga_io_memory = vga_init_io(s); + vga_io_memory = vga_init_io(s, &vga_ports, &vbe_ports); + isa_register_portio_list(dev, 0x3b0, vga_ports, s, "vga"); + if (vbe_ports) { + isa_register_portio_list(dev, 0x1ce, vbe_ports, s, "vbe"); + } memory_region_add_subregion_overlap(isa_address_space(dev), isa_mem_base + 0x000a0000, vga_io_memory, 1); memory_region_set_coalescing(vga_io_memory); - isa_init_ioport(dev, 0x3c0); - isa_init_ioport(dev, 0x3b4); - isa_init_ioport(dev, 0x3ba); - isa_init_ioport(dev, 0x3da); - isa_init_ioport(dev, 0x3c0); -#ifdef CONFIG_BOCHS_VBE - isa_init_ioport(dev, 0x1ce); - isa_init_ioport(dev, 0x1cf); - isa_init_ioport(dev, 0x1d0); -#endif /* CONFIG_BOCHS_VBE */ s->ds = graphic_console_init(s->update, s->invalidate, s->screen_dump, s->text_update, s); diff --git a/hw/vga-pci.c b/hw/vga-pci.c index 3c8bcb00b7..14bfadbfcf 100644 --- a/hw/vga-pci.c +++ b/hw/vga-pci.c @@ -54,7 +54,7 @@ static int pci_vga_initfn(PCIDevice *dev) // vga + console init vga_common_init(s, VGA_RAM_SIZE); - vga_init(s, pci_address_space(dev)); + vga_init(s, pci_address_space(dev), pci_address_space_io(dev), true); s->ds = graphic_console_init(s->update, s->invalidate, s->screen_dump, s->text_update, s); @@ -1838,6 +1838,8 @@ static void vga_update_display(void *opaque) VGACommonState *s = opaque; int full_update, graphic_mode; + qemu_flush_coalesced_mmio_buffer(); + if (ds_get_bits_per_pixel(s->ds) == 0) { /* nothing to do */ } else { @@ -1958,6 +1960,8 @@ static void vga_update_text(void *opaque, console_ch_t *chardata) char msg_buffer[80]; int full_update = 0; + qemu_flush_coalesced_mmio_buffer(); + if (!(s->ar_index & 0x20)) { graphic_mode = GMODE_BLANK; } else { @@ -2241,40 +2245,39 @@ void vga_common_init(VGACommonState *s, int vga_ram_size) vga_dirty_log_start(s); } -/* used by both ISA and PCI */ -MemoryRegion *vga_init_io(VGACommonState *s) -{ - MemoryRegion *vga_mem; - - register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s); - - register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s); - register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s); - register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s); - register_ioport_write(0x3da, 1, 1, vga_ioport_write, s); - - register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s); - - register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s); - register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s); - register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s); - register_ioport_read(0x3da, 1, 1, vga_ioport_read, s); +static const MemoryRegionPortio vga_portio_list[] = { + { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */ + { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */ + { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */ + { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */ + { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */ + PORTIO_END_OF_LIST(), +}; #ifdef CONFIG_BOCHS_VBE -#if defined (TARGET_I386) - register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s); - register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s); +static const MemoryRegionPortio vbe_portio_list[] = { + { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index }, +# ifdef TARGET_I386 + { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data }, +# else + { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data }, +# endif + PORTIO_END_OF_LIST(), +}; +#endif /* CONFIG_BOCHS_VBE */ - register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s); - register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s); -#else - register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s); - register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s); +/* Used by both ISA and PCI */ +MemoryRegion *vga_init_io(VGACommonState *s, + const MemoryRegionPortio **vga_ports, + const MemoryRegionPortio **vbe_ports) +{ + MemoryRegion *vga_mem; - register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s); - register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s); + *vga_ports = vga_portio_list; + *vbe_ports = NULL; +#ifdef CONFIG_BOCHS_VBE + *vbe_ports = vbe_portio_list; #endif -#endif /* CONFIG_BOCHS_VBE */ vga_mem = g_malloc(sizeof(*vga_mem)); memory_region_init_io(vga_mem, &vga_mem_ops, s, @@ -2283,9 +2286,13 @@ MemoryRegion *vga_init_io(VGACommonState *s) return vga_mem; } -void vga_init(VGACommonState *s, MemoryRegion *address_space) +void vga_init(VGACommonState *s, MemoryRegion *address_space, + MemoryRegion *address_space_io, bool init_vga_ports) { MemoryRegion *vga_io_memory; + const MemoryRegionPortio *vga_ports, *vbe_ports; + PortioList *vga_port_list = g_new(PortioList, 1); + PortioList *vbe_port_list = g_new(PortioList, 1); qemu_register_reset(vga_reset, s); @@ -2293,12 +2300,20 @@ void vga_init(VGACommonState *s, MemoryRegion *address_space) s->legacy_address_space = address_space; - vga_io_memory = vga_init_io(s); + vga_io_memory = vga_init_io(s, &vga_ports, &vbe_ports); memory_region_add_subregion_overlap(address_space, isa_mem_base + 0x000a0000, vga_io_memory, 1); memory_region_set_coalescing(vga_io_memory); + if (init_vga_ports) { + portio_list_init(vga_port_list, vga_ports, s, "vga"); + portio_list_add(vga_port_list, address_space_io, 0x3b0); + } + if (vbe_ports) { + portio_list_init(vbe_port_list, vbe_ports, s, "vbe"); + portio_list_add(vbe_port_list, address_space_io, 0x1ce); + } } void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory) diff --git a/hw/vga_int.h b/hw/vga_int.h index 99287dde9b..c1e700fa0b 100644 --- a/hw/vga_int.h +++ b/hw/vga_int.h @@ -187,8 +187,11 @@ static inline int c6_to_8(int v) } void vga_common_init(VGACommonState *s, int vga_ram_size); -void vga_init(VGACommonState *s, MemoryRegion *address_space); -MemoryRegion *vga_init_io(VGACommonState *s); +void vga_init(VGACommonState *s, MemoryRegion *address_space, + MemoryRegion *address_space_io, bool init_vga_ports); +MemoryRegion *vga_init_io(VGACommonState *s, + const MemoryRegionPortio **vga_ports, + const MemoryRegionPortio **vbe_ports); void vga_common_reset(VGACommonState *s); void vga_dirty_log_start(VGACommonState *s); diff --git a/hw/virtio-blk.c b/hw/virtio-blk.c index 03878bfc5e..2a5d1a92b3 100644 --- a/hw/virtio-blk.c +++ b/hw/virtio-blk.c @@ -78,6 +78,7 @@ static int virtio_blk_handle_rw_error(VirtIOBlockReq *req, int error, s->rq = req; bdrv_mon_event(s->bs, BDRV_ACTION_STOP, is_read); vm_stop(RUN_STATE_IO_ERROR); + bdrv_iostatus_set_err(s->bs, error); } else { virtio_blk_req_complete(req, VIRTIO_BLK_S_IOERR); bdrv_acct_done(s->bs, &req->acct); @@ -603,6 +604,7 @@ VirtIODevice *virtio_blk_init(DeviceState *dev, BlockConf *conf, bdrv_set_dev_ops(s->bs, &virtio_block_ops, s); bdrv_set_buffer_alignment(s->bs, conf->logical_block_size); + bdrv_iostatus_enable(s->bs); add_boot_device_path(conf->bootindex, dev, "/disk@0,0"); return &s->vdev; diff --git a/hw/vmport.c b/hw/vmport.c index c8aefaabb8..b5c6fa19cd 100644 --- a/hw/vmport.c +++ b/hw/vmport.c @@ -38,6 +38,7 @@ typedef struct _VMPortState { ISADevice dev; + MemoryRegion io; IOPortReadFunc *func[VMPORT_ENTRIES]; void *opaque[VMPORT_ENTRIES]; } VMPortState; @@ -120,13 +121,22 @@ void vmmouse_set_data(const uint32_t *data) env->regs[R_ESI] = data[4]; env->regs[R_EDI] = data[5]; } +static const MemoryRegionPortio vmport_portio[] = { + {0, 1, 4, .read = vmport_ioport_read, .write = vmport_ioport_write }, + PORTIO_END_OF_LIST(), +}; + +static const MemoryRegionOps vmport_ops = { + .old_portio = vmport_portio +}; + static int vmport_initfn(ISADevice *dev) { VMPortState *s = DO_UPCAST(VMPortState, dev, dev); - register_ioport_read(0x5658, 1, 4, vmport_ioport_read, s); - register_ioport_write(0x5658, 1, 4, vmport_ioport_write, s); - isa_init_ioport(dev, 0x5658); + memory_region_init_io(&s->io, &vmport_ops, s, "vmport", 1); + isa_register_ioport(dev, &s->io, 0x5658); + port_state = s; /* Register some generic port commands */ vmport_register(VMPORT_CMD_GETVERSION, vmport_cmd_get_version, NULL); diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c index aa682376ad..af70bdee09 100644 --- a/hw/vmware_vga.c +++ b/hw/vmware_vga.c @@ -1079,7 +1079,7 @@ static const VMStateDescription vmstate_vmware_vga = { }; static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size, - MemoryRegion *address_space) + MemoryRegion *address_space, MemoryRegion *io) { s->scratch_size = SVGA_SCRATCH_SIZE; s->scratch = g_malloc(s->scratch_size * 4); @@ -1095,7 +1095,7 @@ static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size, s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); vga_common_init(&s->vga, vga_ram_size); - vga_init(&s->vga, address_space); + vga_init(&s->vga, address_space, io, true); vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); s->depth = ds_get_bits_per_pixel(s->vga.ds); @@ -1183,7 +1183,8 @@ static int pci_vmsvga_initfn(PCIDevice *dev) "vmsvga-io", 0x10); pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); - vmsvga_init(&s->chip, VGA_RAM_SIZE, pci_address_space(dev)); + vmsvga_init(&s->chip, VGA_RAM_SIZE, pci_address_space(dev), + pci_address_space_io(dev)); pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem); pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c new file mode 100644 index 0000000000..3cebca1cfc --- /dev/null +++ b/hw/xtensa_lx60.c @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "sysemu.h" +#include "boards.h" +#include "loader.h" +#include "elf.h" +#include "memory.h" +#include "exec-memory.h" +#include "pc.h" +#include "sysbus.h" + +typedef struct Lx60FpgaState { + MemoryRegion iomem; + uint32_t leds; + uint32_t switches; +} Lx60FpgaState; + +static void lx60_fpga_reset(void *opaque) +{ + Lx60FpgaState *s = opaque; + + s->leds = 0; + s->switches = 0; +} + +static uint64_t lx60_fpga_read(void *opaque, target_phys_addr_t addr, + unsigned size) +{ + Lx60FpgaState *s = opaque; + + switch (addr) { + case 0x0: /*build date code*/ + return 0x27092011; + + case 0x4: /*processor clock frequency, Hz*/ + return 10000000; + + case 0x8: /*LEDs (off = 0, on = 1)*/ + return s->leds; + + case 0xc: /*DIP switches (off = 0, on = 1)*/ + return s->switches; + } + return 0; +} + +static void lx60_fpga_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size) +{ + Lx60FpgaState *s = opaque; + + switch (addr) { + case 0x8: /*LEDs (off = 0, on = 1)*/ + s->leds = val; + break; + + case 0x10: /*board reset*/ + if (val == 0xdead) { + qemu_system_reset_request(); + } + break; + } +} + +static const MemoryRegionOps lx60_fpga_ops = { + .read = lx60_fpga_read, + .write = lx60_fpga_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space, + target_phys_addr_t base) +{ + Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState)); + + memory_region_init_io(&s->iomem, &lx60_fpga_ops, s, + "lx60-fpga", 0x10000); + memory_region_add_subregion(address_space, base, &s->iomem); + lx60_fpga_reset(s); + qemu_register_reset(lx60_fpga_reset, s); + return s; +} + +static void lx60_net_init(MemoryRegion *address_space, + target_phys_addr_t base, + target_phys_addr_t descriptors, + target_phys_addr_t buffers, + qemu_irq irq, NICInfo *nd) +{ + DeviceState *dev; + SysBusDevice *s; + MemoryRegion *ram; + + dev = qdev_create(NULL, "open_eth"); + qdev_set_nic_properties(dev, nd); + qdev_init_nofail(dev); + + s = sysbus_from_qdev(dev); + sysbus_connect_irq(s, 0, irq); + memory_region_add_subregion(address_space, base, + sysbus_mmio_get_region(s, 0)); + memory_region_add_subregion(address_space, descriptors, + sysbus_mmio_get_region(s, 1)); + + ram = g_malloc(sizeof(*ram)); + memory_region_init_ram(ram, NULL, "open_eth.ram", 16384); + memory_region_add_subregion(address_space, buffers, ram); +} + +static uint64_t translate_phys_addr(void *env, uint64_t addr) +{ + return cpu_get_phys_page_debug(env, addr); +} + +static void lx60_reset(void *env) +{ + cpu_reset(env); +} + +static void lx60_init(ram_addr_t ram_size, + const char *boot_device, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ +#ifdef TARGET_WORDS_BIGENDIAN + int be = 1; +#else + int be = 0; +#endif + MemoryRegion *system_memory = get_system_memory(); + CPUState *env = NULL; + MemoryRegion *ram, *rom, *system_io; + int n; + + for (n = 0; n < smp_cpus; n++) { + env = cpu_init(cpu_model); + if (!env) { + fprintf(stderr, "Unable to find CPU definition\n"); + exit(1); + } + env->sregs[PRID] = n; + qemu_register_reset(lx60_reset, env); + /* Need MMU initialized prior to ELF loading, + * so that ELF gets loaded into virtual addresses + */ + cpu_reset(env); + } + + ram = g_malloc(sizeof(*ram)); + memory_region_init_ram(ram, NULL, "xtensa.sram", ram_size); + memory_region_add_subregion(system_memory, 0, ram); + + rom = g_malloc(sizeof(*rom)); + memory_region_init_ram(rom, NULL, "xtensa.rom", 0x1000); + memory_region_add_subregion(system_memory, 0xfe000000, rom); + + system_io = g_malloc(sizeof(*system_io)); + memory_region_init(system_io, "system.io", 224 * 1024 * 1024); + memory_region_add_subregion(system_memory, 0xf0000000, system_io); + lx60_fpga_init(system_io, 0x0d020000); + if (nd_table[0].vlan) { + lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, + xtensa_get_extint(env, 1), nd_table); + } + + if (!serial_hds[0]) { + serial_hds[0] = qemu_chr_new("serial0", "null", NULL); + } + + serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0), + 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); + + if (kernel_filename) { + uint64_t elf_entry; + uint64_t elf_lowaddr; + int success = load_elf(kernel_filename, translate_phys_addr, env, + &elf_entry, &elf_lowaddr, NULL, be, ELF_MACHINE, 0); + if (success > 0) { + env->pc = elf_entry; + } + } +} + +static void xtensa_lx60_init(ram_addr_t ram_size, + const char *boot_device, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + if (!cpu_model) { + cpu_model = "dc232b"; + } + lx60_init(ram_size, boot_device, kernel_filename, kernel_cmdline, + initrd_filename, cpu_model); +} + +static QEMUMachine xtensa_lx60_machine = { + .name = "lx60", + .desc = "lx60 EVB (dc232b)", + .init = xtensa_lx60_init, + .max_cpus = 4, +}; + +static void xtensa_lx60_machine_init(void) +{ + qemu_register_machine(&xtensa_lx60_machine); +} + +machine_init(xtensa_lx60_machine_init); diff --git a/hw/xtensa_pic.c b/hw/xtensa_pic.c index 3033ae214a..71d5fc89d4 100644 --- a/hw/xtensa_pic.c +++ b/hw/xtensa_pic.c @@ -26,19 +26,9 @@ */ #include "hw.h" -#include "pc.h" #include "qemu-log.h" #include "qemu-timer.h" -/* Stub functions for hardware that doesn't exist. */ -void pic_info(Monitor *mon) -{ -} - -void irq_info(Monitor *mon) -{ -} - void xtensa_advance_ccount(CPUState *env, uint32_t d) { uint32_t old_ccount = env->sregs[CCOUNT]; @@ -116,10 +106,35 @@ void xtensa_timer_irq(CPUState *env, uint32_t id, uint32_t active) qemu_set_irq(env->irq_inputs[env->config->timerint[id]], active); } +void xtensa_rearm_ccompare_timer(CPUState *env) +{ + int i; + uint32_t wake_ccount = env->sregs[CCOUNT] - 1; + + for (i = 0; i < env->config->nccompare; ++i) { + if (env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] < + wake_ccount - env->sregs[CCOUNT]) { + wake_ccount = env->sregs[CCOMPARE + i]; + } + } + env->wake_ccount = wake_ccount; + qemu_mod_timer(env->ccompare_timer, env->halt_clock + + muldiv64(wake_ccount - env->sregs[CCOUNT], + 1000000, env->config->clock_freq_khz)); +} + static void xtensa_ccompare_cb(void *opaque) { CPUState *env = opaque; - xtensa_advance_ccount(env, env->wake_ccount - env->sregs[CCOUNT]); + + if (env->halted) { + env->halt_clock = qemu_get_clock_ns(vm_clock); + xtensa_advance_ccount(env, env->wake_ccount - env->sregs[CCOUNT]); + if (!cpu_has_work(env)) { + env->sregs[CCOUNT] = env->wake_ccount + 1; + xtensa_rearm_ccompare_timer(env); + } + } } void xtensa_irq_init(CPUState *env) @@ -132,3 +147,15 @@ void xtensa_irq_init(CPUState *env) qemu_new_timer_ns(vm_clock, &xtensa_ccompare_cb, env); } } + +void *xtensa_get_extint(CPUState *env, unsigned extint) +{ + if (extint < env->config->nextint) { + unsigned irq = env->config->extint[extint]; + return env->irq_inputs[irq]; + } else { + qemu_log("%s: trying to acquire invalid external interrupt %d\n", + __func__, extint); + return NULL; + } +} diff --git a/hw/xtensa_sample.c b/hw/xtensa_sample.c deleted file mode 100644 index 31a6f70825..0000000000 --- a/hw/xtensa_sample.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the Open Source and Linux Lab nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "sysemu.h" -#include "boards.h" -#include "loader.h" -#include "elf.h" -#include "memory.h" -#include "exec-memory.h" - -static void xtensa_sample_reset(void *env) -{ - cpu_reset(env); -} - -static void xtensa_init(ram_addr_t ram_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - CPUState *env = NULL; - MemoryRegion *ram; - const size_t dram_size = 0x10000; - const size_t iram_size = 0x20000; - int n; - - for (n = 0; n < smp_cpus; n++) { - env = cpu_init(cpu_model); - if (!env) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } - qemu_register_reset(xtensa_sample_reset, env); - env->sregs[PRID] = n; - } - - ram = g_malloc(sizeof(*ram)); - memory_region_init_ram(ram, NULL, "xtensa.ram", - dram_size + iram_size + ram_size); - memory_region_add_subregion(get_system_memory(), - 0x60000000 - dram_size - iram_size, ram); - - if (kernel_filename) { - uint64_t elf_entry; - uint64_t elf_lowaddr; -#ifdef TARGET_WORDS_BIGENDIAN - int success = load_elf(kernel_filename, NULL, NULL, &elf_entry, - &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); -#else - int success = load_elf(kernel_filename, NULL, NULL, &elf_entry, - &elf_lowaddr, NULL, 0, ELF_MACHINE, 0); -#endif - if (success > 0) { - env->pc = elf_entry; - } - } -} - -static void xtensa_sample_init(ram_addr_t ram_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - if (!cpu_model) { - cpu_model = "sample-xtensa-core"; - } - xtensa_init(ram_size, boot_device, kernel_filename, kernel_cmdline, - initrd_filename, cpu_model); -} - -static QEMUMachine xtensa_sample_machine = { - .name = "sample-xtensa-machine", - .desc = "Sample Xtensa machine (sample Xtensa core)", - .init = xtensa_sample_init, - .max_cpus = 4, -}; - -static void xtensa_sample_machine_init(void) -{ - qemu_register_machine(&xtensa_sample_machine); -} - -machine_init(xtensa_sample_machine_init); diff --git a/hw/xtensa_dc232b.c b/hw/xtensa_sim.c index 015d6aaa6b..a94e4e561e 100644 --- a/hw/xtensa_dc232b.c +++ b/hw/xtensa_sim.c @@ -37,12 +37,12 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr) return cpu_get_phys_page_debug(env, addr); } -static void dc232b_reset(void *env) +static void sim_reset(void *env) { cpu_reset(env); } -static void dc232b_init(ram_addr_t ram_size, +static void sim_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -58,11 +58,11 @@ static void dc232b_init(ram_addr_t ram_size, exit(1); } env->sregs[PRID] = n; - qemu_register_reset(dc232b_reset, env); + qemu_register_reset(sim_reset, env); /* Need MMU initialized prior to ELF loading, * so that ELF gets loaded into virtual addresses */ - dc232b_reset(env); + sim_reset(env); } ram = g_malloc(sizeof(*ram)); @@ -89,7 +89,7 @@ static void dc232b_init(ram_addr_t ram_size, } } -static void xtensa_dc232b_init(ram_addr_t ram_size, +static void xtensa_sim_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -97,20 +97,20 @@ static void xtensa_dc232b_init(ram_addr_t ram_size, if (!cpu_model) { cpu_model = "dc232b"; } - dc232b_init(ram_size, boot_device, kernel_filename, kernel_cmdline, + sim_init(ram_size, boot_device, kernel_filename, kernel_cmdline, initrd_filename, cpu_model); } -static QEMUMachine xtensa_dc232b_machine = { - .name = "dc232b", - .desc = "Diamond 232L Standard Core Rev.B (LE) (dc232b)", - .init = xtensa_dc232b_init, +static QEMUMachine xtensa_sim_machine = { + .name = "sim", + .desc = "sim machine (dc232b)", + .init = xtensa_sim_init, .max_cpus = 4, }; -static void xtensa_dc232b_machine_init(void) +static void xtensa_sim_machine_init(void) { - qemu_register_machine(&xtensa_dc232b_machine); + qemu_register_machine(&xtensa_sim_machine); } -machine_init(xtensa_dc232b_machine_init); +machine_init(xtensa_sim_machine_init); @@ -27,6 +27,7 @@ #include "ioport.h" #include "trace.h" +#include "memory.h" /***********************************************************/ /* IO Port */ @@ -313,3 +314,110 @@ uint32_t cpu_inl(pio_addr_t addr) LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val); return val; } + +void portio_list_init(PortioList *piolist, + const MemoryRegionPortio *callbacks, + void *opaque, const char *name) +{ + unsigned n = 0; + + while (callbacks[n].size) { + ++n; + } + + piolist->ports = callbacks; + piolist->nr = 0; + piolist->regions = g_new0(MemoryRegion *, n); + piolist->address_space = NULL; + piolist->opaque = opaque; + piolist->name = name; +} + +void portio_list_destroy(PortioList *piolist) +{ + g_free(piolist->regions); +} + +static void portio_list_add_1(PortioList *piolist, + const MemoryRegionPortio *pio_init, + unsigned count, unsigned start, + unsigned off_low, unsigned off_high) +{ + MemoryRegionPortio *pio; + MemoryRegionOps *ops; + MemoryRegion *region; + unsigned i; + + /* Copy the sub-list and null-terminate it. */ + pio = g_new(MemoryRegionPortio, count + 1); + memcpy(pio, pio_init, sizeof(MemoryRegionPortio) * count); + memset(pio + count, 0, sizeof(MemoryRegionPortio)); + + /* Adjust the offsets to all be zero-based for the region. */ + for (i = 0; i < count; ++i) { + pio[i].offset -= off_low; + } + + ops = g_new0(MemoryRegionOps, 1); + ops->old_portio = pio; + + region = g_new(MemoryRegion, 1); + memory_region_init_io(region, ops, piolist->opaque, piolist->name, + off_high - off_low); + memory_region_set_offset(region, start + off_low); + memory_region_add_subregion(piolist->address_space, + start + off_low, region); + piolist->regions[piolist->nr++] = region; +} + +void portio_list_add(PortioList *piolist, + MemoryRegion *address_space, + uint32_t start) +{ + const MemoryRegionPortio *pio, *pio_start = piolist->ports; + unsigned int off_low, off_high, off_last, count; + + piolist->address_space = address_space; + + /* Handle the first entry specially. */ + off_last = off_low = pio_start->offset; + off_high = off_low + pio_start->len; + count = 1; + + for (pio = pio_start + 1; pio->size != 0; pio++, count++) { + /* All entries must be sorted by offset. */ + assert(pio->offset >= off_last); + off_last = pio->offset; + + /* If we see a hole, break the region. */ + if (off_last > off_high) { + portio_list_add_1(piolist, pio_start, count, start, off_low, + off_high); + /* ... and start collecting anew. */ + pio_start = pio; + off_low = off_last; + off_high = off_low + pio->len; + count = 0; + } else if (off_last + pio->len > off_high) { + off_high = off_last + pio->len; + } + } + + /* There will always be an open sub-list. */ + portio_list_add_1(piolist, pio_start, count, start, off_low, off_high); +} + +void portio_list_del(PortioList *piolist) +{ + MemoryRegion *mr; + unsigned i; + + for (i = 0; i < piolist->nr; ++i) { + mr = piolist->regions[i]; + memory_region_del_subregion(piolist->address_space, mr); + memory_region_destroy(mr); + g_free((MemoryRegionOps *)mr->ops); + g_free(mr); + piolist->regions[i] = NULL; + } +} @@ -52,4 +52,25 @@ uint8_t cpu_inb(pio_addr_t addr); uint16_t cpu_inw(pio_addr_t addr); uint32_t cpu_inl(pio_addr_t addr); +struct MemoryRegion; +struct MemoryRegionPortio; + +typedef struct PortioList { + const struct MemoryRegionPortio *ports; + struct MemoryRegion *address_space; + unsigned nr; + struct MemoryRegion **regions; + void *opaque; + const char *name; +} PortioList; + +void portio_list_init(PortioList *piolist, + const struct MemoryRegionPortio *callbacks, + void *opaque, const char *name); +void portio_list_destroy(PortioList *piolist); +void portio_list_add(PortioList *piolist, + struct MemoryRegion *address_space, + uint32_t addr); +void portio_list_del(PortioList *piolist); + #endif /* IOPORT_H */ diff --git a/linux-aio.c b/linux-aio.c index bffa6cd0e3..1c635ef12d 100644 --- a/linux-aio.c +++ b/linux-aio.c @@ -31,6 +31,8 @@ struct qemu_laiocb { struct iocb iocb; ssize_t ret; size_t nbytes; + QEMUIOVector *qiov; + bool is_read; QLIST_ENTRY(qemu_laiocb) node; }; @@ -57,10 +59,17 @@ static void qemu_laio_process_completion(struct qemu_laio_state *s, ret = laiocb->ret; if (ret != -ECANCELED) { - if (ret == laiocb->nbytes) + if (ret == laiocb->nbytes) { ret = 0; - else if (ret >= 0) - ret = -EINVAL; + } else if (ret >= 0) { + /* Short reads mean EOF, pad with zeros. */ + if (laiocb->is_read) { + qemu_iovec_memset_skip(laiocb->qiov, 0, + laiocb->qiov->size - ret, ret); + } else { + ret = -EINVAL; + } + } laiocb->common.cb(laiocb->common.opaque, ret); } @@ -162,6 +171,8 @@ BlockDriverAIOCB *laio_submit(BlockDriverState *bs, void *aio_ctx, int fd, laiocb->nbytes = nb_sectors * 512; laiocb->ctx = s; laiocb->ret = -EINPROGRESS; + laiocb->is_read = (type == QEMU_AIO_READ); + laiocb->qiov = qiov; iocbs = &laiocb->iocb; @@ -185,10 +196,10 @@ BlockDriverAIOCB *laio_submit(BlockDriverState *bs, void *aio_ctx, int fd, goto out_dec_count; return &laiocb->common; -out_free_aiocb: - qemu_aio_release(laiocb); out_dec_count: s->count--; +out_free_aiocb: + qemu_aio_release(laiocb); return NULL; } @@ -403,12 +403,17 @@ static void memory_region_iorange_read(IORange *iorange, *data = ((uint64_t)1 << (width * 8)) - 1; if (mrp) { - *data = mrp->read(mr->opaque, offset); + *data = mrp->read(mr->opaque, offset + mr->offset); + } else if (width == 2) { + mrp = find_portio(mr, offset, 1, false); + assert(mrp); + *data = mrp->read(mr->opaque, offset + mr->offset) | + (mrp->read(mr->opaque, offset + mr->offset + 1) << 8); } return; } *data = 0; - access_with_adjusted_size(offset, data, width, + access_with_adjusted_size(offset + mr->offset, data, width, mr->ops->impl.min_access_size, mr->ops->impl.max_access_size, memory_region_read_accessor, mr); @@ -425,11 +430,16 @@ static void memory_region_iorange_write(IORange *iorange, const MemoryRegionPortio *mrp = find_portio(mr, offset, width, true); if (mrp) { - mrp->write(mr->opaque, offset, data); + mrp->write(mr->opaque, offset + mr->offset, data); + } else if (width == 2) { + mrp = find_portio(mr, offset, 1, false); + assert(mrp); + mrp->write(mr->opaque, offset + mr->offset, data & 0xff); + mrp->write(mr->opaque, offset + mr->offset + 1, data >> 8); } return; } - access_with_adjusted_size(offset, &data, width, + access_with_adjusted_size(offset + mr->offset, &data, width, mr->ops->impl.min_access_size, mr->ops->impl.max_access_size, memory_region_write_accessor, mr); diff --git a/migration.c b/migration.c index 77a51adc5b..62b74a6e26 100644 --- a/migration.c +++ b/migration.c @@ -375,7 +375,7 @@ void migrate_fd_put_ready(void *opaque) int old_vm_running = runstate_is_running(); DPRINTF("done iterating\n"); - vm_stop(RUN_STATE_FINISH_MIGRATE); + vm_stop_force_state(RUN_STATE_FINISH_MIGRATE); if ((qemu_savevm_state_complete(s->mon, s->file)) < 0) { if (old_vm_running) { @@ -67,6 +67,12 @@ #include "qmp-commands.h" #include "hmp.h" +/* for pic/irq_info */ +#if defined(TARGET_SPARC) +#include "hw/sun4m.h" +#endif +#include "hw/lm32_pic.h" + //#define DEBUG //#define DEBUG_COMPLETION @@ -1221,6 +1227,11 @@ struct bdrv_iterate_context { int err; }; +static void iostatus_bdrv_it(void *opaque, BlockDriverState *bs) +{ + bdrv_iostatus_reset(bs); +} + /** * do_cont(): Resume emulation. */ @@ -1237,6 +1248,7 @@ static int do_cont(Monitor *mon, const QDict *qdict, QObject **ret_data) return -1; } + bdrv_iterate(iostatus_bdrv_it, NULL); bdrv_iterate(encrypted_bdrv_it, &context); /* only resume the vm if all keys are set and valid */ if (!context.err) { @@ -2792,20 +2804,35 @@ static const mon_cmd_t info_cmds[] = { .help = "show the command line history", .mhandler.info = do_info_history, }, +#if defined(TARGET_I386) || defined(TARGET_PPC) || defined(TARGET_MIPS) || \ + defined(TARGET_LM32) || (defined(TARGET_SPARC) && !defined(TARGET_SPARC64)) { .name = "irq", .args_type = "", .params = "", .help = "show the interrupts statistics (if available)", +#ifdef TARGET_SPARC + .mhandler.info = sun4m_irq_info, +#elif defined(TARGET_LM32) + .mhandler.info = lm32_irq_info, +#else .mhandler.info = irq_info, +#endif }, { .name = "pic", .args_type = "", .params = "", .help = "show i8259 (PIC) state", +#ifdef TARGET_SPARC + .mhandler.info = sun4m_pic_info, +#elif defined(TARGET_LM32) + .mhandler.info = lm32_do_pic_info, +#else .mhandler.info = pic_info, +#endif }, +#endif { .name = "pci", .args_type = "", diff --git a/qemu-char.c b/qemu-char.c index 8bdbcfdad2..fb9e058961 100644 --- a/qemu-char.c +++ b/qemu-char.c @@ -1664,8 +1664,8 @@ static int qemu_chr_open_win(QemuOpts *opts, CharDriverState **_chr) chr->chr_close = win_chr_close; if (win_chr_init(chr, filename) < 0) { - free(s); - free(chr); + g_free(s); + g_free(chr); return -EIO; } qemu_chr_generic_open(chr); @@ -1766,8 +1766,8 @@ static int qemu_chr_open_win_pipe(QemuOpts *opts, CharDriverState **_chr) chr->chr_close = win_chr_close; if (win_chr_pipe_init(chr, filename) < 0) { - free(s); - free(chr); + g_free(s); + g_free(chr); return -EIO; } qemu_chr_generic_open(chr); diff --git a/qemu-doc.texi b/qemu-doc.texi index 31199f6004..ad19b73f15 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -110,6 +110,7 @@ For system emulation, the following hardware targets are supported: @item Syborg SVP base model (ARM Cortex-A8). @item AXIS-Devboard88 (CRISv32 ETRAX-FS). @item Petalogix Spartan 3aDSP1800 MMU ref design (MicroBlaze). +@item Avnet LX60/LX110/LX200 boards (Xtensa) @end itemize @cindex supported user mode targets @@ -1446,6 +1447,7 @@ differences are mentioned in the following sections. * Cris System emulator:: * Microblaze System emulator:: * SH4 System emulator:: +* Xtensa System emulator:: @end menu @node PowerPC System emulator @@ -2124,6 +2126,59 @@ TODO TODO +@node Xtensa System emulator +@section Xtensa System emulator +@cindex system emulation (Xtensa) + +Two executables cover simulation of both Xtensa endian options, +@file{qemu-system-xtensa} and @file{qemu-system-xtensaeb}. +Two different machine types are emulated: + +@itemize @minus +@item +Xtensa emulator pseudo board "sim" +@item +Avnet LX60/LX110/LX200 board +@end itemize + +The sim pseudo board emulation provides an environment similiar +to one provided by the proprietary Tensilica ISS. +It supports: + +@itemize @minus +@item +A range of Xtensa CPUs, default is the DC232B +@item +Console and filesystem access via semihosting calls +@end itemize + +The Avnet LX60/LX110/LX200 emulation supports: + +@itemize @minus +@item +A range of Xtensa CPUs, default is the DC232B +@item +16550 UART +@item +OpenCores 10/100 Mbps Ethernet MAC +@end itemize + +@c man begin OPTIONS + +The following options are specific to the Xtensa emulation: + +@table @option + +@item -semihosting +Enable semihosting syscall emulation. + +Xtensa semihosting provides basic file IO calls, such as open/read/write/seek/select. +Tensilica baremetal libc for ISS and linux platform "sim" use this interface. + +Note that this allows guest direct access to the host filesystem, +so should only be used with trusted guest OS. + +@end table @node QEMU User space emulator @chapter QEMU User space emulator diff --git a/qemu-options.hx b/qemu-options.hx index f05be307ba..5d2a7765e8 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1703,15 +1703,15 @@ Connect to a local parallel port. @option{path} specifies the path to the parallel port device. @option{path} is required. -#if defined(CONFIG_SPICE) @item -chardev spicevmc ,id=@var{id} ,debug=@var{debug}, name=@var{name} +@option{spicevmc} is only available when spice support is built in. + @option{debug} debug level for spicevmc @option{name} name of spice channel to connect to Connect to a spice virtual machine channel, such as vdiport. -#endif @end table ETEXI diff --git a/qemu-tech.texi b/qemu-tech.texi index 138e3ce9ad..397b070842 100644 --- a/qemu-tech.texi +++ b/qemu-tech.texi @@ -42,13 +42,14 @@ @chapter Introduction @menu -* intro_features:: Features -* intro_x86_emulation:: x86 and x86-64 emulation -* intro_arm_emulation:: ARM emulation -* intro_mips_emulation:: MIPS emulation -* intro_ppc_emulation:: PowerPC emulation -* intro_sparc_emulation:: Sparc32 and Sparc64 emulation -* intro_other_emulation:: Other CPU emulation +* intro_features:: Features +* intro_x86_emulation:: x86 and x86-64 emulation +* intro_arm_emulation:: ARM emulation +* intro_mips_emulation:: MIPS emulation +* intro_ppc_emulation:: PowerPC emulation +* intro_sparc_emulation:: Sparc32 and Sparc64 emulation +* intro_xtensa_emulation:: Xtensa emulation +* intro_other_emulation:: Other CPU emulation @end menu @node intro_features @@ -259,6 +260,31 @@ Current QEMU limitations: @end itemize +@node intro_xtensa_emulation +@section Xtensa emulation + +@itemize + +@item Core Xtensa ISA emulation, including most options: code density, +loop, extended L32R, 16- and 32-bit multiplication, 32-bit division, +MAC16, miscellaneous operations, boolean, multiprocessor synchronization, +conditional store, exceptions, relocatable vectors, unaligned exception, +interrupts (including high priority and timer), hardware alignment, +region protection, region translation, MMU, windowed registers, thread +pointer, processor ID. + +@item Not implemented options: FP coprocessor, coprocessor context, +data/instruction cache (including cache prefetch and locking), XLMI, +processor interface, debug. Also options not covered by the core ISA +(e.g. FLIX, wide branches) are not implemented. + +@item Can run most Xtensa Linux binaries. + +@item New core configuration that requires no additional instructions +may be created from overlay with minimal amount of hand-written code. + +@end itemize + @node intro_other_emulation @section Other CPU emulation diff --git a/qmp-commands.hx b/qmp-commands.hx index ea96191c12..4328e8b86c 100644 --- a/qmp-commands.hx +++ b/qmp-commands.hx @@ -710,10 +710,10 @@ Arguments: Example: --> { "execute": "blockdev-snapshot", "arguments": { "device": "ide-hd0", - "snapshot-file": - "/some/place/my-image", - "format": "qcow2" } } +-> { "execute": "blockdev-snapshot-sync", "arguments": { "device": "ide-hd0", + "snapshot-file": + "/some/place/my-image", + "format": "qcow2" } } <- { "return": {} } EQMP @@ -1154,6 +1154,10 @@ Each json-object contain the following: "tftp", "vdi", "vmdk", "vpc", "vvfat" - "backing_file": backing file name (json-string, optional) - "encrypted": true if encrypted, false otherwise (json-bool) +- "io-status": I/O operation status, only present if the device supports it + and the VM is configured to stop on errors. It's always reset + to "ok" when the "cont" command is issued (json_string, optional) + - Possible values: "ok", "failed", "nospace" Example: @@ -1161,6 +1165,7 @@ Example: <- { "return":[ { + "io-status": "ok", "device":"ide0-hd0", "locked":false, "removable":false, @@ -1173,6 +1178,7 @@ Example: "type":"unknown" }, { + "io-status": "ok", "device":"ide1-cd0", "locked":false, "removable":true, @@ -1599,12 +1599,8 @@ void qemu_savevm_state_cancel(Monitor *mon, QEMUFile *f) static int qemu_savevm_state(Monitor *mon, QEMUFile *f) { - int saved_vm_running; int ret; - saved_vm_running = runstate_is_running(); - vm_stop(RUN_STATE_SAVE_VM); - if (qemu_savevm_state_blocked(mon)) { ret = -EINVAL; goto out; @@ -1626,9 +1622,6 @@ out: if (qemu_file_has_error(f)) ret = -EIO; - if (!ret && saved_vm_running) - vm_start(); - return ret; } @@ -35,6 +35,7 @@ void vm_state_notify(int running, RunState state); void vm_start(void); void vm_stop(RunState state); +void vm_stop_force_state(RunState state); void qemu_system_reset_request(void); void qemu_system_shutdown_request(void); diff --git a/target-xtensa/core-dc232b.c b/target-xtensa/core-dc232b.c new file mode 100644 index 0000000000..4d9bd559d4 --- /dev/null +++ b/target-xtensa/core-dc232b.c @@ -0,0 +1,28 @@ +#include "cpu.h" +#include "exec-all.h" +#include "gdbstub.h" +#include "qemu-common.h" +#include "host-utils.h" + +#include "core-dc232b/core-isa.h" +#include "overlay_tool.h" + +static const XtensaConfig dc232b = { + .name = "dc232b", + .options = XTENSA_OPTIONS, + .gdb_regmap = { + .num_regs = 120, + .num_core_regs = 52, + .reg = { +#include "core-dc232b/gdb-config.c" + } + }, + .nareg = XCHAL_NUM_AREGS, + .ndepc = 1, + EXCEPTIONS_SECTION, + INTERRUPTS_SECTION, + TLB_SECTION, + .clock_freq_khz = 10000, +}; + +REGISTER_CORE(dc232b) diff --git a/target-xtensa/core-dc232b/core-isa.h b/target-xtensa/core-dc232b/core-isa.h new file mode 100644 index 0000000000..69f1065574 --- /dev/null +++ b/target-xtensa/core-dc232b/core-isa.h @@ -0,0 +1,423 @@ +/* + * Xtensa processor core configuration information. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 1999-2007 Tensilica Inc. + */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU insns */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 1 /* MAC16 package */ +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_FP 0 /* floating point pkg */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ + +#define XCHAL_SW_VERSION 701001 /* sw version of this header */ + +#define XCHAL_CORE_ID "dc232b" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_CORE_DESCRIPTION "Diamond 232L Standard Core Rev.B (LE)" +#define XCHAL_BUILD_UNIQUE_ID 0x0000BEEF /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC56307FE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x0D40BEEF /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX2.1.1" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2210 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 221001 /* major*100+minor */ +#define XCHAL_HW_REL_LX2 1 +#define XCHAL_HW_REL_LX2_1 1 +#define XCHAL_HW_REL_LX2_1_1 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2210 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 221001 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2210 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 221001 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 7 +#define XCHAL_DCACHE_SETWIDTH 7 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS 4 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ +#define XCHAL_CA_BITS 4 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x001F80FF +#define XCHAL_INTLEVEL2_MASK 0x00000100 +#define XCHAL_INTLEVEL3_MASK 0x00200E00 +#define XCHAL_INTLEVEL4_MASK 0x00001000 +#define XCHAL_INTLEVEL5_MASK 0x00002000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00004000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 3 +#define XCHAL_INT10_LEVEL 3 +#define XCHAL_INT11_LEVEL 3 +#define XCHAL_INT12_LEVEL 4 +#define XCHAL_INT13_LEVEL 5 +#define XCHAL_INT14_LEVEL 7 +#define XCHAL_INT15_LEVEL 1 +#define XCHAL_INT16_LEVEL 1 +#define XCHAL_INT17_LEVEL 1 +#define XCHAL_INT18_LEVEL 1 +#define XCHAL_INT19_LEVEL 1 +#define XCHAL_INT20_LEVEL 1 +#define XCHAL_INT21_LEVEL 3 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F +#define XCHAL_INTTYPE_MASK_TIMER 0x00002440 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL2_NUM 8 +#define XCHAL_INTLEVEL4_NUM 12 +#define XCHAL_INTLEVEL5_NUM 13 +#define XCHAL_INTLEVEL7_NUM 14 +/* (There are many interrupts each at level(s) 1, 3.) */ + + +/* + * External interrupt vectors/levels. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt<n> pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ +#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ +#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ +#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x00000000 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 +#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 +#define XCHAL_RESET_VECTOR1_VADDR 0xD8000500 +#define XCHAL_RESET_VECTOR1_PADDR 0x00000500 +#define XCHAL_RESET_VECTOR_VADDR 0xFE000000 +#define XCHAL_RESET_VECTOR_PADDR 0xFE000000 +#define XCHAL_USER_VECOFS 0x00000340 +#define XCHAL_USER_VECTOR_VADDR 0xD0000340 +#define XCHAL_USER_VECTOR_PADDR 0x00000340 +#define XCHAL_KERNEL_VECOFS 0x00000300 +#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000300 +#define XCHAL_KERNEL_VECTOR_PADDR 0x00000300 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD00003C0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000003C0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000 +#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000180 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000180 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD00001C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000001C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xD0000200 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00000200 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xD0000240 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00000240 +#define XCHAL_INTLEVEL6_VECOFS 0x00000280 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xD0000280 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00000280 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000002C0 +#define XCHAL_NMI_VECTOR_VADDR 0xD00002C0 +#define XCHAL_NMI_VECTOR_PADDR 0x000002C0 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */ +#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ +#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ +#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ + +#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ diff --git a/target-xtensa/gdb-config-dc232b.c b/target-xtensa/core-dc232b/gdb-config.c index 13aba5edec..13aba5edec 100644 --- a/target-xtensa/gdb-config-dc232b.c +++ b/target-xtensa/core-dc232b/gdb-config.c diff --git a/target-xtensa/core-fsf.c b/target-xtensa/core-fsf.c new file mode 100644 index 0000000000..7650462f2f --- /dev/null +++ b/target-xtensa/core-fsf.c @@ -0,0 +1,22 @@ +#include "cpu.h" +#include "exec-all.h" +#include "gdbstub.h" +#include "qemu-common.h" +#include "host-utils.h" + +#include "core-fsf/core-isa.h" +#include "overlay_tool.h" + +static const XtensaConfig fsf = { + .name = "fsf", + .options = XTENSA_OPTIONS, + /* GDB for this core is not supported currently */ + .nareg = XCHAL_NUM_AREGS, + .ndepc = 1, + EXCEPTIONS_SECTION, + INTERRUPTS_SECTION, + TLB_SECTION, + .clock_freq_khz = 10000, +}; + +REGISTER_CORE(fsf) diff --git a/target-xtensa/core-fsf/core-isa.h b/target-xtensa/core-fsf/core-isa.h new file mode 100644 index 0000000000..b519d6c741 --- /dev/null +++ b/target-xtensa/core-fsf/core-isa.h @@ -0,0 +1,361 @@ +/* + * Xtensa processor core configuration information. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999-2006 Tensilica Inc. + */ + +#ifndef _XTENSA_CORE_H +#define _XTENSA_CORE_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 1 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 0 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 0 /* SEXT instruction */ +#define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 0 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 0 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 0 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ +#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_FP 0 /* floating point pkg */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ + +#define XCHAL_SW_VERSION 800002 /* sw version of this header */ + +#define XCHAL_CORE_ID "fsf" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_CORE_DESCRIPTION "fsf standard core" +#define XCHAL_BUILD_UNIQUE_ID 0x00006700 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC103C3FF /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x0C006700 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX2.0.0" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2200 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 0 /* minor ver# of targeted hw */ +#define XTHAL_HW_REL_LX2 1 +#define XTHAL_HW_REL_LX2_0 1 +#define XTHAL_HW_REL_LX2_0_0 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2200 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 0 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2200 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 0 /* minor v of latest tgt hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 8192 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 8 +#define XCHAL_DCACHE_SETWIDTH 8 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 2 +#define XCHAL_DCACHE_WAYS 2 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 0 +#define XCHAL_DCACHE_LINE_LOCKABLE 0 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ +#define XCHAL_CA_BITS 4 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 17 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 10 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x000064F9 +#define XCHAL_INTLEVEL2_MASK 0x00008902 +#define XCHAL_INTLEVEL3_MASK 0x00011204 +#define XCHAL_INTLEVEL4_MASK 0x00000000 +#define XCHAL_INTLEVEL5_MASK 0x00000000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00000000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000064F9 +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x0000EDFB +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x0001FFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x0001FFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x0001FFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x0001FFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x0001FFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 2 +#define XCHAL_INT2_LEVEL 3 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 3 +#define XCHAL_INT10_LEVEL 1 +#define XCHAL_INT11_LEVEL 2 +#define XCHAL_INT12_LEVEL 3 +#define XCHAL_INT13_LEVEL 1 +#define XCHAL_INT14_LEVEL 1 +#define XCHAL_INT15_LEVEL 2 +#define XCHAL_INT16_LEVEL 3 +#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 0 /* OCD external db interrupt */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_SOFTWARE + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFE0000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0001E000 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000380 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000007F +#define XCHAL_INTTYPE_MASK_TIMER 0x00001C00 +#define XCHAL_INTTYPE_MASK_NMI 0x00000000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 10 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 11 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 12 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +/* (There are many interrupts each at level(s) 1, 2, 3.) */ + + +/* + * External interrupt vectors/levels. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt<n> pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 2) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 3) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT9_NUM 9 /* (intlevel 3) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ + +#define XCHAL_RESET_VECTOR_VADDR 0xFE000020 +#define XCHAL_RESET_VECTOR_PADDR 0xFE000020 +#define XCHAL_USER_VECTOR_VADDR 0xD0000220 +#define XCHAL_USER_VECTOR_PADDR 0x00000220 +#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000200 +#define XCHAL_KERNEL_VECTOR_PADDR 0x00000200 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD0000290 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x00000290 +#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000 +#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000240 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000240 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD0000250 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x00000250 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xFE000520 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xFE000520 +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See <xtensa/config/core-matmap.h> header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */ +#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ +#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ +#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ + +#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 339075dda1..0db83a6fd7 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -52,9 +52,13 @@ enum { XTENSA_OPTION_EXTENDED_L32R, XTENSA_OPTION_16_BIT_IMUL, XTENSA_OPTION_32_BIT_IMUL, + XTENSA_OPTION_32_BIT_IMUL_HIGH, XTENSA_OPTION_32_BIT_IDIV, XTENSA_OPTION_MAC16, - XTENSA_OPTION_MISC_OP, + XTENSA_OPTION_MISC_OP_NSA, + XTENSA_OPTION_MISC_OP_MINMAX, + XTENSA_OPTION_MISC_OP_SEXT, + XTENSA_OPTION_MISC_OP_CLAMPS, XTENSA_OPTION_COPROCESSOR, XTENSA_OPTION_BOOLEAN, XTENSA_OPTION_FP_COPROCESSOR, @@ -113,6 +117,9 @@ enum { BR = 4, LITBASE = 5, SCOMPARE1 = 12, + ACCLO = 16, + ACCHI = 17, + MR = 32, WINDOW_BASE = 72, WINDOW_START = 73, PTEVADDR = 83, @@ -270,12 +277,19 @@ typedef struct XtensaConfig { } interrupt[MAX_NINTERRUPT]; unsigned nccompare; uint32_t timerint[MAX_NCCOMPARE]; + unsigned nextint; + unsigned extint[MAX_NINTERRUPT]; uint32_t clock_freq_khz; xtensa_tlb itlb; xtensa_tlb dtlb; } XtensaConfig; +typedef struct XtensaConfigList { + const XtensaConfig *config; + struct XtensaConfigList *next; +} XtensaConfigList; + typedef struct CPUXtensaState { const XtensaConfig *config; uint32_t regs[16]; @@ -308,11 +322,14 @@ typedef struct CPUXtensaState { CPUXtensaState *cpu_xtensa_init(const char *cpu_model); void xtensa_translate_init(void); int cpu_xtensa_exec(CPUXtensaState *s); +void xtensa_register_core(XtensaConfigList *node); void do_interrupt(CPUXtensaState *s); void check_interrupts(CPUXtensaState *s); void xtensa_irq_init(CPUState *env); +void *xtensa_get_extint(CPUState *env, unsigned extint); void xtensa_advance_ccount(CPUState *env, uint32_t d); void xtensa_timer_irq(CPUState *env, uint32_t id, uint32_t active); +void xtensa_rearm_ccompare_timer(CPUState *env); int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf); void xtensa_sync_window_from_phys(CPUState *env); diff --git a/target-xtensa/gdb-config-sample-xtensa-core.c b/target-xtensa/gdb-config-sample-xtensa-core.c deleted file mode 100644 index bfbd7be30a..0000000000 --- a/target-xtensa/gdb-config-sample-xtensa-core.c +++ /dev/null @@ -1,375 +0,0 @@ -/* Configuration for the Xtensa architecture for GDB, the GNU debugger. - - Copyright (c) 2003-2010 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - - XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc, - 0, 0, 0, 0, 0, 0) - XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0, - 0, 0, 0, 0, 0, 0) - XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1, - 0, 0, 0, 0, 0, 0) - XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2, - 0, 0, 0, 0, 0, 0) - XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3, - 0, 0, 0, 0, 0, 0) - XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4, - 0, 0, 0, 0, 0, 0) - XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5, - 0, 0, 0, 0, 0, 0) - XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6, - 0, 0, 0, 0, 0, 0) - XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7, - 0, 0, 0, 0, 0, 0) - XTREG(9, 36, 32, 4, 4, 0x0108, 0x0006, -2, 1, 0x0002, ar8, - 0, 0, 0, 0, 0, 0) - XTREG(10, 40, 32, 4, 4, 0x0109, 0x0006, -2, 1, 0x0002, ar9, - 0, 0, 0, 0, 0, 0) - XTREG(11, 44, 32, 4, 4, 0x010a, 0x0006, -2, 1, 0x0002, ar10, - 0, 0, 0, 0, 0, 0) - XTREG(12, 48, 32, 4, 4, 0x010b, 0x0006, -2, 1, 0x0002, ar11, - 0, 0, 0, 0, 0, 0) - XTREG(13, 52, 32, 4, 4, 0x010c, 0x0006, -2, 1, 0x0002, ar12, - 0, 0, 0, 0, 0, 0) - XTREG(14, 56, 32, 4, 4, 0x010d, 0x0006, -2, 1, 0x0002, ar13, - 0, 0, 0, 0, 0, 0) - XTREG(15, 60, 32, 4, 4, 0x010e, 0x0006, -2, 1, 0x0002, ar14, - 0, 0, 0, 0, 0, 0) - XTREG(16, 64, 32, 4, 4, 0x010f, 0x0006, -2, 1, 0x0002, ar15, - 0, 0, 0, 0, 0, 0) - XTREG(17, 68, 32, 4, 4, 0x0110, 0x0006, -2, 1, 0x0002, ar16, - 0, 0, 0, 0, 0, 0) - XTREG(18, 72, 32, 4, 4, 0x0111, 0x0006, -2, 1, 0x0002, ar17, - 0, 0, 0, 0, 0, 0) - XTREG(19, 76, 32, 4, 4, 0x0112, 0x0006, -2, 1, 0x0002, ar18, - 0, 0, 0, 0, 0, 0) - XTREG(20, 80, 32, 4, 4, 0x0113, 0x0006, -2, 1, 0x0002, ar19, - 0, 0, 0, 0, 0, 0) - XTREG(21, 84, 32, 4, 4, 0x0114, 0x0006, -2, 1, 0x0002, ar20, - 0, 0, 0, 0, 0, 0) - XTREG(22, 88, 32, 4, 4, 0x0115, 0x0006, -2, 1, 0x0002, ar21, - 0, 0, 0, 0, 0, 0) - XTREG(23, 92, 32, 4, 4, 0x0116, 0x0006, -2, 1, 0x0002, ar22, - 0, 0, 0, 0, 0, 0) - XTREG(24, 96, 32, 4, 4, 0x0117, 0x0006, -2, 1, 0x0002, ar23, - 0, 0, 0, 0, 0, 0) - XTREG(25, 100, 32, 4, 4, 0x0118, 0x0006, -2, 1, 0x0002, ar24, - 0, 0, 0, 0, 0, 0) - XTREG(26, 104, 32, 4, 4, 0x0119, 0x0006, -2, 1, 0x0002, ar25, - 0, 0, 0, 0, 0, 0) - XTREG(27, 108, 32, 4, 4, 0x011a, 0x0006, -2, 1, 0x0002, ar26, - 0, 0, 0, 0, 0, 0) - XTREG(28, 112, 32, 4, 4, 0x011b, 0x0006, -2, 1, 0x0002, ar27, - 0, 0, 0, 0, 0, 0) - XTREG(29, 116, 32, 4, 4, 0x011c, 0x0006, -2, 1, 0x0002, ar28, - 0, 0, 0, 0, 0, 0) - XTREG(30, 120, 32, 4, 4, 0x011d, 0x0006, -2, 1, 0x0002, ar29, - 0, 0, 0, 0, 0, 0) - XTREG(31, 124, 32, 4, 4, 0x011e, 0x0006, -2, 1, 0x0002, ar30, - 0, 0, 0, 0, 0, 0) - XTREG(32, 128, 32, 4, 4, 0x011f, 0x0006, -2, 1, 0x0002, ar31, - 0, 0, 0, 0, 0, 0) - XTREG(33, 132, 32, 4, 4, 0x0120, 0x0006, -2, 1, 0x0002, ar32, - 0, 0, 0, 0, 0, 0) - XTREG(34, 136, 32, 4, 4, 0x0121, 0x0006, -2, 1, 0x0002, ar33, - 0, 0, 0, 0, 0, 0) - XTREG(35, 140, 32, 4, 4, 0x0122, 0x0006, -2, 1, 0x0002, ar34, - 0, 0, 0, 0, 0, 0) - XTREG(36, 144, 32, 4, 4, 0x0123, 0x0006, -2, 1, 0x0002, ar35, - 0, 0, 0, 0, 0, 0) - XTREG(37, 148, 32, 4, 4, 0x0124, 0x0006, -2, 1, 0x0002, ar36, - 0, 0, 0, 0, 0, 0) - XTREG(38, 152, 32, 4, 4, 0x0125, 0x0006, -2, 1, 0x0002, ar37, - 0, 0, 0, 0, 0, 0) - XTREG(39, 156, 32, 4, 4, 0x0126, 0x0006, -2, 1, 0x0002, ar38, - 0, 0, 0, 0, 0, 0) - XTREG(40, 160, 32, 4, 4, 0x0127, 0x0006, -2, 1, 0x0002, ar39, - 0, 0, 0, 0, 0, 0) - XTREG(41, 164, 32, 4, 4, 0x0128, 0x0006, -2, 1, 0x0002, ar40, - 0, 0, 0, 0, 0, 0) - XTREG(42, 168, 32, 4, 4, 0x0129, 0x0006, -2, 1, 0x0002, ar41, - 0, 0, 0, 0, 0, 0) - XTREG(43, 172, 32, 4, 4, 0x012a, 0x0006, -2, 1, 0x0002, ar42, - 0, 0, 0, 0, 0, 0) - XTREG(44, 176, 32, 4, 4, 0x012b, 0x0006, -2, 1, 0x0002, ar43, - 0, 0, 0, 0, 0, 0) - XTREG(45, 180, 32, 4, 4, 0x012c, 0x0006, -2, 1, 0x0002, ar44, - 0, 0, 0, 0, 0, 0) - XTREG(46, 184, 32, 4, 4, 0x012d, 0x0006, -2, 1, 0x0002, ar45, - 0, 0, 0, 0, 0, 0) - XTREG(47, 188, 32, 4, 4, 0x012e, 0x0006, -2, 1, 0x0002, ar46, - 0, 0, 0, 0, 0, 0) - XTREG(48, 192, 32, 4, 4, 0x012f, 0x0006, -2, 1, 0x0002, ar47, - 0, 0, 0, 0, 0, 0) - XTREG(49, 196, 32, 4, 4, 0x0130, 0x0006, -2, 1, 0x0002, ar48, - 0, 0, 0, 0, 0, 0) - XTREG(50, 200, 32, 4, 4, 0x0131, 0x0006, -2, 1, 0x0002, ar49, - 0, 0, 0, 0, 0, 0) - XTREG(51, 204, 32, 4, 4, 0x0132, 0x0006, -2, 1, 0x0002, ar50, - 0, 0, 0, 0, 0, 0) - XTREG(52, 208, 32, 4, 4, 0x0133, 0x0006, -2, 1, 0x0002, ar51, - 0, 0, 0, 0, 0, 0) - XTREG(53, 212, 32, 4, 4, 0x0134, 0x0006, -2, 1, 0x0002, ar52, - 0, 0, 0, 0, 0, 0) - XTREG(54, 216, 32, 4, 4, 0x0135, 0x0006, -2, 1, 0x0002, ar53, - 0, 0, 0, 0, 0, 0) - XTREG(55, 220, 32, 4, 4, 0x0136, 0x0006, -2, 1, 0x0002, ar54, - 0, 0, 0, 0, 0, 0) - XTREG(56, 224, 32, 4, 4, 0x0137, 0x0006, -2, 1, 0x0002, ar55, - 0, 0, 0, 0, 0, 0) - XTREG(57, 228, 32, 4, 4, 0x0138, 0x0006, -2, 1, 0x0002, ar56, - 0, 0, 0, 0, 0, 0) - XTREG(58, 232, 32, 4, 4, 0x0139, 0x0006, -2, 1, 0x0002, ar57, - 0, 0, 0, 0, 0, 0) - XTREG(59, 236, 32, 4, 4, 0x013a, 0x0006, -2, 1, 0x0002, ar58, - 0, 0, 0, 0, 0, 0) - XTREG(60, 240, 32, 4, 4, 0x013b, 0x0006, -2, 1, 0x0002, ar59, - 0, 0, 0, 0, 0, 0) - XTREG(61, 244, 32, 4, 4, 0x013c, 0x0006, -2, 1, 0x0002, ar60, - 0, 0, 0, 0, 0, 0) - XTREG(62, 248, 32, 4, 4, 0x013d, 0x0006, -2, 1, 0x0002, ar61, - 0, 0, 0, 0, 0, 0) - XTREG(63, 252, 32, 4, 4, 0x013e, 0x0006, -2, 1, 0x0002, ar62, - 0, 0, 0, 0, 0, 0) - XTREG(64, 256, 32, 4, 4, 0x013f, 0x0006, -2, 1, 0x0002, ar63, - 0, 0, 0, 0, 0, 0) - XTREG(65, 260, 32, 4, 4, 0x0200, 0x0006, -2, 2, 0x1100, lbeg, - 0, 0, 0, 0, 0, 0) - XTREG(66, 264, 32, 4, 4, 0x0201, 0x0006, -2, 2, 0x1100, lend, - 0, 0, 0, 0, 0, 0) - XTREG(67, 268, 32, 4, 4, 0x0202, 0x0006, -2, 2, 0x1100, lcount, - 0, 0, 0, 0, 0, 0) - XTREG(68, 272, 6, 4, 4, 0x0203, 0x0006, -2, 2, 0x1100, sar, - 0, 0, 0, 0, 0, 0) - XTREG(69, 276, 32, 4, 4, 0x0205, 0x0006, -2, 2, 0x1100, litbase, - 0, 0, 0, 0, 0, 0) - XTREG(70, 280, 4, 4, 4, 0x0248, 0x0006, -2, 2, 0x1002, windowbase, - 0, 0, 0, 0, 0, 0) - XTREG(71, 284, 16, 4, 4, 0x0249, 0x0006, -2, 2, 0x1002, windowstart, - 0, 0, 0, 0, 0, 0) - XTREG(72, 288, 32, 4, 4, 0x02b0, 0x0002, -2, 2, 0x1000, sr176, - 0, 0, 0, 0, 0, 0) - XTREG(73, 292, 32, 4, 4, 0x02d0, 0x0002, -2, 2, 0x1000, sr208, - 0, 0, 0, 0, 0, 0) - XTREG(74, 296, 19, 4, 4, 0x02e6, 0x0006, -2, 2, 0x1100, ps, - 0, 0, 0, 0, 0, 0) - XTREG(75, 300, 32, 4, 4, 0x03e7, 0x0006, -2, 3, 0x0110, threadptr, - 0, 0, 0, 0, 0, 0) - XTREG(76, 304, 32, 4, 4, 0x020c, 0x0006, -1, 2, 0x1100, scompare1, - 0, 0, 0, 0, 0, 0) - XTREG(77, 308, 32, 4, 4, 0x0327, 0x000e, -1, 3, 0x0210, expstate, - 0, 0, 0, 0, 0, 0) - XTREG(78, 312, 32, 4, 4, 0x0300, 0x0006, 2, 3, 0x0210, stage1, - 0, 0, 0, 0, 0, 0) - XTREG(79, 316, 32, 4, 4, 0x0301, 0x0006, 2, 3, 0x0210, stage2, - 0, 0, 0, 0, 0, 0) - XTREG(80, 320, 32, 4, 4, 0x0302, 0x0006, 2, 3, 0x0210, input_align_reg, - 0, 0, 0, 0, 0, 0) - XTREG(81, 324, 6, 4, 4, 0x0303, 0x0006, 2, 3, 0x0210, input_align_reg_pos, - 0, 0, 0, 0, 0, 0) - XTREG(82, 328, 32, 4, 4, 0x0304, 0x0006, 2, 3, 0x0210, data_reg, - 0, 0, 0, 0, 0, 0) - XTREG(83, 332, 7, 4, 4, 0x0305, 0x0006, 2, 3, 0x0210, data_reg_pos, - 0, 0, 0, 0, 0, 0) - XTREG(84, 336, 32, 4, 4, 0x0306, 0x0006, 2, 3, 0x0210, crc_reg, - 0, 0, 0, 0, 0, 0) - XTREG(85, 340, 32, 4, 4, 0x0307, 0x0006, 2, 3, 0x0210, pol_reg00, - 0, 0, 0, 0, 0, 0) - XTREG(86, 344, 32, 4, 4, 0x0308, 0x0006, 2, 3, 0x0210, pol_reg01, - 0, 0, 0, 0, 0, 0) - XTREG(87, 348, 32, 4, 4, 0x0309, 0x0006, 2, 3, 0x0210, pol_reg02, - 0, 0, 0, 0, 0, 0) - XTREG(88, 352, 32, 4, 4, 0x030a, 0x0006, 2, 3, 0x0210, pol_reg03, - 0, 0, 0, 0, 0, 0) - XTREG(89, 356, 32, 4, 4, 0x030b, 0x0006, 2, 3, 0x0210, pol_reg04, - 0, 0, 0, 0, 0, 0) - XTREG(90, 360, 32, 4, 4, 0x030c, 0x0006, 2, 3, 0x0210, pol_reg05, - 0, 0, 0, 0, 0, 0) - XTREG(91, 364, 32, 4, 4, 0x030d, 0x0006, 2, 3, 0x0210, pol_reg06, - 0, 0, 0, 0, 0, 0) - XTREG(92, 368, 32, 4, 4, 0x030e, 0x0006, 2, 3, 0x0210, pol_reg07, - 0, 0, 0, 0, 0, 0) - XTREG(93, 372, 32, 4, 4, 0x030f, 0x0006, 2, 3, 0x0210, pol_reg08, - 0, 0, 0, 0, 0, 0) - XTREG(94, 376, 32, 4, 4, 0x0310, 0x0006, 2, 3, 0x0210, pol_reg09, - 0, 0, 0, 0, 0, 0) - XTREG(95, 380, 32, 4, 4, 0x0311, 0x0006, 2, 3, 0x0210, pol_reg10, - 0, 0, 0, 0, 0, 0) - XTREG(96, 384, 32, 4, 4, 0x0312, 0x0006, 2, 3, 0x0210, pol_reg11, - 0, 0, 0, 0, 0, 0) - XTREG(97, 388, 32, 4, 4, 0x0313, 0x0006, 2, 3, 0x0210, pol_reg12, - 0, 0, 0, 0, 0, 0) - XTREG(98, 392, 32, 4, 4, 0x0314, 0x0006, 2, 3, 0x0210, pol_reg13, - 0, 0, 0, 0, 0, 0) - XTREG(99, 396, 32, 4, 4, 0x0315, 0x0006, 2, 3, 0x0210, pol_reg14, - 0, 0, 0, 0, 0, 0) - XTREG(100, 400, 32, 4, 4, 0x0316, 0x0006, 2, 3, 0x0210, pol_reg15, - 0, 0, 0, 0, 0, 0) - XTREG(101, 404, 32, 4, 4, 0x0317, 0x0006, 2, 3, 0x0210, pol_reg16, - 0, 0, 0, 0, 0, 0) - XTREG(102, 408, 32, 4, 4, 0x0318, 0x0006, 2, 3, 0x0210, pol_reg17, - 0, 0, 0, 0, 0, 0) - XTREG(103, 412, 32, 4, 4, 0x0319, 0x0006, 2, 3, 0x0210, pol_reg18, - 0, 0, 0, 0, 0, 0) - XTREG(104, 416, 32, 4, 4, 0x031a, 0x0006, 2, 3, 0x0210, pol_reg19, - 0, 0, 0, 0, 0, 0) - XTREG(105, 420, 32, 4, 4, 0x031b, 0x0006, 2, 3, 0x0210, pol_reg20, - 0, 0, 0, 0, 0, 0) - XTREG(106, 424, 32, 4, 4, 0x031c, 0x0006, 2, 3, 0x0210, pol_reg21, - 0, 0, 0, 0, 0, 0) - XTREG(107, 428, 32, 4, 4, 0x031d, 0x0006, 2, 3, 0x0210, pol_reg22, - 0, 0, 0, 0, 0, 0) - XTREG(108, 432, 32, 4, 4, 0x031e, 0x0006, 2, 3, 0x0210, pol_reg23, - 0, 0, 0, 0, 0, 0) - XTREG(109, 436, 32, 4, 4, 0x031f, 0x0006, 2, 3, 0x0210, pol_reg24, - 0, 0, 0, 0, 0, 0) - XTREG(110, 440, 32, 4, 4, 0x0320, 0x0006, 2, 3, 0x0210, pol_reg25, - 0, 0, 0, 0, 0, 0) - XTREG(111, 444, 32, 4, 4, 0x0321, 0x0006, 2, 3, 0x0210, pol_reg26, - 0, 0, 0, 0, 0, 0) - XTREG(112, 448, 32, 4, 4, 0x0322, 0x0006, 2, 3, 0x0210, pol_reg27, - 0, 0, 0, 0, 0, 0) - XTREG(113, 452, 32, 4, 4, 0x0323, 0x0006, 2, 3, 0x0210, pol_reg28, - 0, 0, 0, 0, 0, 0) - XTREG(114, 456, 32, 4, 4, 0x0324, 0x0006, 2, 3, 0x0210, pol_reg29, - 0, 0, 0, 0, 0, 0) - XTREG(115, 460, 32, 4, 4, 0x0325, 0x0006, 2, 3, 0x0210, pol_reg30, - 0, 0, 0, 0, 0, 0) - XTREG(116, 464, 32, 4, 4, 0x0326, 0x0006, 2, 3, 0x0210, pol_reg31, - 0, 0, 0, 0, 0, 0) - XTREG(117, 468, 32, 4, 4, 0x0259, 0x000d, -2, 2, 0x1000, mmid, - 0, 0, 0, 0, 0, 0) - XTREG(118, 472, 2, 4, 4, 0x0260, 0x0007, -2, 2, 0x1000, ibreakenable, - 0, 0, 0, 0, 0, 0) - XTREG(119, 476, 6, 4, 4, 0x0263, 0x0007, -2, 2, 0x1000, atomctl, - 0, 0, 0, 0, 0, 0) - XTREG(120, 480, 32, 4, 4, 0x0268, 0x0007, -2, 2, 0x1000, ddr, - 0, 0, 0, 0, 0, 0) - XTREG(121, 484, 32, 4, 4, 0x0280, 0x0007, -2, 2, 0x1000, ibreaka0, - 0, 0, 0, 0, 0, 0) - XTREG(122, 488, 32, 4, 4, 0x0281, 0x0007, -2, 2, 0x1000, ibreaka1, - 0, 0, 0, 0, 0, 0) - XTREG(123, 492, 32, 4, 4, 0x0290, 0x0007, -2, 2, 0x1000, dbreaka0, - 0, 0, 0, 0, 0, 0) - XTREG(124, 496, 32, 4, 4, 0x0291, 0x0007, -2, 2, 0x1000, dbreaka1, - 0, 0, 0, 0, 0, 0) - XTREG(125, 500, 32, 4, 4, 0x02a0, 0x0007, -2, 2, 0x1000, dbreakc0, - 0, 0, 0, 0, 0, 0) - XTREG(126, 504, 32, 4, 4, 0x02a1, 0x0007, -2, 2, 0x1000, dbreakc1, - 0, 0, 0, 0, 0, 0) - XTREG(127, 508, 32, 4, 4, 0x02b1, 0x0007, -2, 2, 0x1000, epc1, - 0, 0, 0, 0, 0, 0) - XTREG(128, 512, 32, 4, 4, 0x02b2, 0x0007, -2, 2, 0x1000, epc2, - 0, 0, 0, 0, 0, 0) - XTREG(129, 516, 32, 4, 4, 0x02b3, 0x0007, -2, 2, 0x1000, epc3, - 0, 0, 0, 0, 0, 0) - XTREG(130, 520, 32, 4, 4, 0x02b4, 0x0007, -2, 2, 0x1000, epc4, - 0, 0, 0, 0, 0, 0) - XTREG(131, 524, 32, 4, 4, 0x02b5, 0x0007, -2, 2, 0x1000, epc5, - 0, 0, 0, 0, 0, 0) - XTREG(132, 528, 32, 4, 4, 0x02b6, 0x0007, -2, 2, 0x1000, epc6, - 0, 0, 0, 0, 0, 0) - XTREG(133, 532, 32, 4, 4, 0x02c0, 0x0007, -2, 2, 0x1000, depc, - 0, 0, 0, 0, 0, 0) - XTREG(134, 536, 19, 4, 4, 0x02c2, 0x0007, -2, 2, 0x1000, eps2, - 0, 0, 0, 0, 0, 0) - XTREG(135, 540, 19, 4, 4, 0x02c3, 0x0007, -2, 2, 0x1000, eps3, - 0, 0, 0, 0, 0, 0) - XTREG(136, 544, 19, 4, 4, 0x02c4, 0x0007, -2, 2, 0x1000, eps4, - 0, 0, 0, 0, 0, 0) - XTREG(137, 548, 19, 4, 4, 0x02c5, 0x0007, -2, 2, 0x1000, eps5, - 0, 0, 0, 0, 0, 0) - XTREG(138, 552, 19, 4, 4, 0x02c6, 0x0007, -2, 2, 0x1000, eps6, - 0, 0, 0, 0, 0, 0) - XTREG(139, 556, 32, 4, 4, 0x02d1, 0x0007, -2, 2, 0x1000, excsave1, - 0, 0, 0, 0, 0, 0) - XTREG(140, 560, 32, 4, 4, 0x02d2, 0x0007, -2, 2, 0x1000, excsave2, - 0, 0, 0, 0, 0, 0) - XTREG(141, 564, 32, 4, 4, 0x02d3, 0x0007, -2, 2, 0x1000, excsave3, - 0, 0, 0, 0, 0, 0) - XTREG(142, 568, 32, 4, 4, 0x02d4, 0x0007, -2, 2, 0x1000, excsave4, - 0, 0, 0, 0, 0, 0) - XTREG(143, 572, 32, 4, 4, 0x02d5, 0x0007, -2, 2, 0x1000, excsave5, - 0, 0, 0, 0, 0, 0) - XTREG(144, 576, 32, 4, 4, 0x02d6, 0x0007, -2, 2, 0x1000, excsave6, - 0, 0, 0, 0, 0, 0) - XTREG(145, 580, 4, 4, 4, 0x02e0, 0x0007, -2, 2, 0x1000, cpenable, - 0, 0, 0, 0, 0, 0) - XTREG(146, 584, 13, 4, 4, 0x02e2, 0x000b, -2, 2, 0x1000, interrupt, - 0, 0, 0, 0, 0, 0) - XTREG(147, 588, 13, 4, 4, 0x02e2, 0x000d, -2, 2, 0x1000, intset, - 0, 0, 0, 0, 0, 0) - XTREG(148, 592, 13, 4, 4, 0x02e3, 0x000d, -2, 2, 0x1000, intclear, - 0, 0, 0, 0, 0, 0) - XTREG(149, 596, 13, 4, 4, 0x02e4, 0x0007, -2, 2, 0x1000, intenable, - 0, 0, 0, 0, 0, 0) - XTREG(150, 600, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase, - 0, 0, 0, 0, 0, 0) - XTREG(151, 604, 6, 4, 4, 0x02e8, 0x0007, -2, 2, 0x1000, exccause, - 0, 0, 0, 0, 0, 0) - XTREG(152, 608, 12, 4, 4, 0x02e9, 0x0003, -2, 2, 0x1000, debugcause, - 0, 0, 0, 0, 0, 0) - XTREG(153, 612, 32, 4, 4, 0x02ea, 0x000f, -2, 2, 0x1000, ccount, - 0, 0, 0, 0, 0, 0) - XTREG(154, 616, 32, 4, 4, 0x02eb, 0x0003, -2, 2, 0x1000, prid, - 0, 0, 0, 0, 0, 0) - XTREG(155, 620, 32, 4, 4, 0x02ec, 0x000f, -2, 2, 0x1000, icount, - 0, 0, 0, 0, 0, 0) - XTREG(156, 624, 4, 4, 4, 0x02ed, 0x0007, -2, 2, 0x1000, icountlevel, - 0, 0, 0, 0, 0, 0) - XTREG(157, 628, 32, 4, 4, 0x02ee, 0x0007, -2, 2, 0x1000, excvaddr, - 0, 0, 0, 0, 0, 0) - XTREG(158, 632, 32, 4, 4, 0x02f0, 0x000f, -2, 2, 0x1000, ccompare0, - 0, 0, 0, 0, 0, 0) - XTREG(159, 636, 32, 4, 4, 0x02f1, 0x000f, -2, 2, 0x1000, ccompare1, - 0, 0, 0, 0, 0, 0) - XTREG(160, 640, 32, 4, 4, 0x0000, 0x0006, -2, 8, 0x0100, a0, - 0, 0, 0, 0, 0, 0) - XTREG(161, 644, 32, 4, 4, 0x0001, 0x0006, -2, 8, 0x0100, a1, - 0, 0, 0, 0, 0, 0) - XTREG(162, 648, 32, 4, 4, 0x0002, 0x0006, -2, 8, 0x0100, a2, - 0, 0, 0, 0, 0, 0) - XTREG(163, 652, 32, 4, 4, 0x0003, 0x0006, -2, 8, 0x0100, a3, - 0, 0, 0, 0, 0, 0) - XTREG(164, 656, 32, 4, 4, 0x0004, 0x0006, -2, 8, 0x0100, a4, - 0, 0, 0, 0, 0, 0) - XTREG(165, 660, 32, 4, 4, 0x0005, 0x0006, -2, 8, 0x0100, a5, - 0, 0, 0, 0, 0, 0) - XTREG(166, 664, 32, 4, 4, 0x0006, 0x0006, -2, 8, 0x0100, a6, - 0, 0, 0, 0, 0, 0) - XTREG(167, 668, 32, 4, 4, 0x0007, 0x0006, -2, 8, 0x0100, a7, - 0, 0, 0, 0, 0, 0) - XTREG(168, 672, 32, 4, 4, 0x0008, 0x0006, -2, 8, 0x0100, a8, - 0, 0, 0, 0, 0, 0) - XTREG(169, 676, 32, 4, 4, 0x0009, 0x0006, -2, 8, 0x0100, a9, - 0, 0, 0, 0, 0, 0) - XTREG(170, 680, 32, 4, 4, 0x000a, 0x0006, -2, 8, 0x0100, a10, - 0, 0, 0, 0, 0, 0) - XTREG(171, 684, 32, 4, 4, 0x000b, 0x0006, -2, 8, 0x0100, a11, - 0, 0, 0, 0, 0, 0) - XTREG(172, 688, 32, 4, 4, 0x000c, 0x0006, -2, 8, 0x0100, a12, - 0, 0, 0, 0, 0, 0) - XTREG(173, 692, 32, 4, 4, 0x000d, 0x0006, -2, 8, 0x0100, a13, - 0, 0, 0, 0, 0, 0) - XTREG(174, 696, 32, 4, 4, 0x000e, 0x0006, -2, 8, 0x0100, a14, - 0, 0, 0, 0, 0, 0) - XTREG(175, 700, 32, 4, 4, 0x000f, 0x0006, -2, 8, 0x0100, a15, - 0, 0, 0, 0, 0, 0) diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index c8ba74e145..fc85815a63 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -34,10 +34,6 @@ #include "hw/loader.h" #endif -#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \ - a1, a2, a3, a4, a5, a6) \ - { .targno = (no), .type = (typ), .group = (grp) }, - static void reset_mmu(CPUState *env); void cpu_reset(CPUXtensaState *env) @@ -53,241 +49,24 @@ void cpu_reset(CPUXtensaState *env) reset_mmu(env); } -static const XtensaConfig core_config[] = { - { - .name = "sample-xtensa-core", - .options = -1 ^ - (XTENSA_OPTION_BIT(XTENSA_OPTION_HW_ALIGNMENT) | - XTENSA_OPTION_BIT(XTENSA_OPTION_MMU)), - .gdb_regmap = { - .num_regs = 176, - .num_core_regs = 117, - .reg = { -#include "gdb-config-sample-xtensa-core.c" - } - }, - .nareg = 64, - .ndepc = 1, - .excm_level = 16, - .vecbase = 0x5fff8400, - .exception_vector = { - [EXC_RESET] = 0x5fff8000, - [EXC_WINDOW_OVERFLOW4] = 0x5fff8400, - [EXC_WINDOW_UNDERFLOW4] = 0x5fff8440, - [EXC_WINDOW_OVERFLOW8] = 0x5fff8480, - [EXC_WINDOW_UNDERFLOW8] = 0x5fff84c0, - [EXC_WINDOW_OVERFLOW12] = 0x5fff8500, - [EXC_WINDOW_UNDERFLOW12] = 0x5fff8540, - [EXC_KERNEL] = 0x5fff861c, - [EXC_USER] = 0x5fff863c, - [EXC_DOUBLE] = 0x5fff865c, - }, - .ninterrupt = 13, - .nlevel = 6, - .interrupt_vector = { - 0, - 0, - 0x5fff857c, - 0x5fff859c, - 0x5fff85bc, - 0x5fff85dc, - 0x5fff85fc, - }, - .level_mask = { - [4] = 1, - }, - .interrupt = { - [0] = { - .level = 4, - .inttype = INTTYPE_TIMER, - }, - }, - .nccompare = 1, - .timerint = { - [0] = 0, - }, - .clock_freq_khz = 912000, - }, { - .name = "dc232b", - .options = -1 ^ - (XTENSA_OPTION_BIT(XTENSA_OPTION_HW_ALIGNMENT) | - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION)), - .gdb_regmap = { - .num_regs = 120, - .num_core_regs = 52, - .reg = { -#include "gdb-config-dc232b.c" - } - }, - .nareg = 32, - .ndepc = 1, - .excm_level = 3, - .vecbase = 0xd0000000, - .exception_vector = { - [EXC_RESET] = 0xfe000000, - [EXC_WINDOW_OVERFLOW4] = 0xd0000000, - [EXC_WINDOW_UNDERFLOW4] = 0xd0000040, - [EXC_WINDOW_OVERFLOW8] = 0xd0000080, - [EXC_WINDOW_UNDERFLOW8] = 0xd00000c0, - [EXC_WINDOW_OVERFLOW12] = 0xd0000100, - [EXC_WINDOW_UNDERFLOW12] = 0xd0000140, - [EXC_KERNEL] = 0xd0000300, - [EXC_USER] = 0xd0000340, - [EXC_DOUBLE] = 0xd00003c0, - }, - .ninterrupt = 22, - .nlevel = 6, - .interrupt_vector = { - 0, - 0, - 0xd0000180, - 0xd00001c0, - 0xd0000200, - 0xd0000240, - 0xd0000280, - 0xd00002c0, - }, - .level_mask = { - [1] = 0x1f80ff, - [2] = 0x000100, - [3] = 0x200e00, - [4] = 0x001000, - [5] = 0x002000, - [6] = 0x000000, - [7] = 0x004000, - }, - .inttype_mask = { - [INTTYPE_EDGE] = 0x3f8000, - [INTTYPE_NMI] = 0x4000, - [INTTYPE_SOFTWARE] = 0x880, - }, - .interrupt = { - [0] = { - .level = 1, - .inttype = INTTYPE_LEVEL, - }, - [1] = { - .level = 1, - .inttype = INTTYPE_LEVEL, - }, - [2] = { - .level = 1, - .inttype = INTTYPE_LEVEL, - }, - [3] = { - .level = 1, - .inttype = INTTYPE_LEVEL, - }, - [4] = { - .level = 1, - .inttype = INTTYPE_LEVEL, - }, - [5] = { - .level = 1, - .inttype = INTTYPE_LEVEL, - }, - [6] = { - .level = 1, - .inttype = INTTYPE_TIMER, - }, - [7] = { - .level = 1, - .inttype = INTTYPE_SOFTWARE, - }, - [8] = { - .level = 2, - .inttype = INTTYPE_LEVEL, - }, - [9] = { - .level = 3, - .inttype = INTTYPE_LEVEL, - }, - [10] = { - .level = 3, - .inttype = INTTYPE_TIMER, - }, - [11] = { - .level = 3, - .inttype = INTTYPE_SOFTWARE, - }, - [12] = { - .level = 4, - .inttype = INTTYPE_LEVEL, - }, - [13] = { - .level = 5, - .inttype = INTTYPE_TIMER, - }, - [14] = { - .level = 7, - .inttype = INTTYPE_NMI, - }, - [15] = { - .level = 1, - .inttype = INTTYPE_EDGE, - }, - [16] = { - .level = 1, - .inttype = INTTYPE_EDGE, - }, - [17] = { - .level = 1, - .inttype = INTTYPE_EDGE, - }, - [18] = { - .level = 1, - .inttype = INTTYPE_EDGE, - }, - [19] = { - .level = 1, - .inttype = INTTYPE_EDGE, - }, - [20] = { - .level = 1, - .inttype = INTTYPE_EDGE, - }, - [21] = { - .level = 3, - .inttype = INTTYPE_EDGE, - }, - }, - .nccompare = 3, - .timerint = { - [0] = 6, - [1] = 10, - [2] = 13, - }, - .clock_freq_khz = 912000, - .itlb = { - .nways = 7, - .way_size = { - 4, 4, 4, 4, 4, 2, 2, - }, - .varway56 = false, - .nrefillentries = 16, - }, - .dtlb = { - .nways = 10, - .way_size = { - 4, 4, 4, 4, 4, 2, 2, 1, 1, 1, - }, - .varway56 = false, - .nrefillentries = 16, - }, - }, -}; +static struct XtensaConfigList *xtensa_cores; + +void xtensa_register_core(XtensaConfigList *node) +{ + node->next = xtensa_cores; + xtensa_cores = node; +} CPUXtensaState *cpu_xtensa_init(const char *cpu_model) { static int tcg_inited; CPUXtensaState *env; const XtensaConfig *config = NULL; - int i; + XtensaConfigList *core = xtensa_cores; - for (i = 0; i < ARRAY_SIZE(core_config); ++i) - if (strcmp(core_config[i].name, cpu_model) == 0) { - config = core_config + i; + for (; core; core = core->next) + if (strcmp(core->config->name, cpu_model) == 0) { + config = core->config; break; } @@ -312,10 +91,10 @@ CPUXtensaState *cpu_xtensa_init(const char *cpu_model) void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf) { - int i; + XtensaConfigList *core = xtensa_cores; cpu_fprintf(f, "Available CPUs:\n"); - for (i = 0; i < ARRAY_SIZE(core_config); ++i) { - cpu_fprintf(f, " %s\n", core_config[i].name); + for (; core; core = core->next) { + cpu_fprintf(f, " %s\n", core->config->name); } } diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 64847fc8e6..0605611031 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -370,23 +370,11 @@ void HELPER(waiti)(uint32_t pc, uint32_t intlevel) return; } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) { - int i; - uint32_t wake_ccount = env->sregs[CCOUNT] - 1; - - for (i = 0; i < env->config->nccompare; ++i) { - if (env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] < - wake_ccount - env->sregs[CCOUNT]) { - wake_ccount = env->sregs[CCOMPARE + i]; - } - } - env->wake_ccount = wake_ccount; - qemu_mod_timer(env->ccompare_timer, qemu_get_clock_ns(vm_clock) + - muldiv64(wake_ccount - env->sregs[CCOUNT], - 1000000, env->config->clock_freq_khz)); - } env->halt_clock = qemu_get_clock_ns(vm_clock); env->halted = 1; + if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) { + xtensa_rearm_ccompare_timer(env); + } HELPER(exception)(EXCP_HLT); } diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h new file mode 100644 index 0000000000..060e8e54d1 --- /dev/null +++ b/target-xtensa/overlay_tool.h @@ -0,0 +1,534 @@ +/* + * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \ + a1, a2, a3, a4, a5, a6) \ + { .targno = (no), .type = (typ), .group = (grp) }, + +#ifndef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 0 +#endif + +#ifndef XCHAL_UNALIGNED_LOAD_HW +#define XCHAL_UNALIGNED_LOAD_HW 0 +#endif + +#ifndef XCHAL_HAVE_VECBASE +#define XCHAL_HAVE_VECBASE 0 +#define XCHAL_VECBASE_RESET_VADDR 0 +#endif + +#define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0) + +#define XTENSA_OPTIONS ( \ + XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \ + XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \ + XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \ + XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \ + XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \ + XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \ + XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \ + XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \ + XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \ + XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \ + XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \ + XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \ + XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \ + XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \ + XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \ + XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \ + /* Interrupts and exceptions */ \ + XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \ + XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \ + XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \ + XTENSA_OPTION_UNALIGNED_EXCEPTION) | \ + XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \ + XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \ + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \ + XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \ + /* Local memory, TODO */ \ + XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \ + /* Memory protection and translation */ \ + XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \ + XTENSA_OPTION_REGION_PROTECTION) | \ + XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \ + XTENSA_OPTION_REGION_TRANSLATION) | \ + XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \ + /* Other, TODO */ \ + XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \ + XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG)) + +#ifndef XCHAL_WINDOW_OF4_VECOFS +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#endif + +#define EXCEPTION_VECTORS { \ + [EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \ + [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \ + XCHAL_WINDOW_VECTORS_VADDR, \ + [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \ + XCHAL_WINDOW_VECTORS_VADDR, \ + [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \ + XCHAL_WINDOW_VECTORS_VADDR, \ + [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \ + XCHAL_WINDOW_VECTORS_VADDR, \ + [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \ + XCHAL_WINDOW_VECTORS_VADDR, \ + [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \ + XCHAL_WINDOW_VECTORS_VADDR, \ + [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \ + [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \ + [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \ + } + +#define INTERRUPT_VECTORS { \ + 0, \ + 0, \ + XCHAL_INTLEVEL2_VECTOR_VADDR, \ + XCHAL_INTLEVEL3_VECTOR_VADDR, \ + XCHAL_INTLEVEL4_VECTOR_VADDR, \ + XCHAL_INTLEVEL5_VECTOR_VADDR, \ + XCHAL_INTLEVEL6_VECTOR_VADDR, \ + XCHAL_INTLEVEL7_VECTOR_VADDR, \ + } + +#define LEVEL_MASKS { \ + [1] = XCHAL_INTLEVEL1_MASK, \ + [2] = XCHAL_INTLEVEL2_MASK, \ + [3] = XCHAL_INTLEVEL3_MASK, \ + [4] = XCHAL_INTLEVEL4_MASK, \ + [5] = XCHAL_INTLEVEL5_MASK, \ + [6] = XCHAL_INTLEVEL6_MASK, \ + [7] = XCHAL_INTLEVEL7_MASK, \ + } + +#define INTTYPE_MASKS { \ + [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \ + [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \ + [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \ + } + +#define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL +#define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE +#define XTHAL_INTTYPE_NMI INTTYPE_NMI +#define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE +#define XTHAL_INTTYPE_TIMER INTTYPE_TIMER +#define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG +#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR +#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR + + +#define INTERRUPT(i) { \ + .level = XCHAL_INT ## i ## _LEVEL, \ + .inttype = XCHAL_INT ## i ## _TYPE, \ + } + +#define INTERRUPTS { \ + [0] = INTERRUPT(0), \ + [1] = INTERRUPT(1), \ + [2] = INTERRUPT(2), \ + [3] = INTERRUPT(3), \ + [4] = INTERRUPT(4), \ + [5] = INTERRUPT(5), \ + [6] = INTERRUPT(6), \ + [7] = INTERRUPT(7), \ + [8] = INTERRUPT(8), \ + [9] = INTERRUPT(9), \ + [10] = INTERRUPT(10), \ + [11] = INTERRUPT(11), \ + [12] = INTERRUPT(12), \ + [13] = INTERRUPT(13), \ + [14] = INTERRUPT(14), \ + [15] = INTERRUPT(15), \ + [16] = INTERRUPT(16), \ + [17] = INTERRUPT(17), \ + [18] = INTERRUPT(18), \ + [19] = INTERRUPT(19), \ + [20] = INTERRUPT(20), \ + [21] = INTERRUPT(21), \ + [22] = INTERRUPT(22), \ + [23] = INTERRUPT(23), \ + [24] = INTERRUPT(24), \ + [25] = INTERRUPT(25), \ + [26] = INTERRUPT(26), \ + [27] = INTERRUPT(27), \ + [28] = INTERRUPT(28), \ + [29] = INTERRUPT(29), \ + [30] = INTERRUPT(30), \ + [31] = INTERRUPT(31), \ + } + +#define TIMERINTS { \ + [0] = XCHAL_TIMER0_INTERRUPT, \ + [1] = XCHAL_TIMER1_INTERRUPT, \ + [2] = XCHAL_TIMER2_INTERRUPT, \ + } + +#define EXTINTS { \ + [0] = XCHAL_EXTINT0_NUM, \ + [1] = XCHAL_EXTINT1_NUM, \ + [2] = XCHAL_EXTINT2_NUM, \ + [3] = XCHAL_EXTINT3_NUM, \ + [4] = XCHAL_EXTINT4_NUM, \ + [5] = XCHAL_EXTINT5_NUM, \ + [6] = XCHAL_EXTINT6_NUM, \ + [7] = XCHAL_EXTINT7_NUM, \ + [8] = XCHAL_EXTINT8_NUM, \ + [9] = XCHAL_EXTINT9_NUM, \ + [10] = XCHAL_EXTINT10_NUM, \ + [11] = XCHAL_EXTINT11_NUM, \ + [12] = XCHAL_EXTINT12_NUM, \ + [13] = XCHAL_EXTINT13_NUM, \ + [14] = XCHAL_EXTINT14_NUM, \ + [15] = XCHAL_EXTINT15_NUM, \ + [16] = XCHAL_EXTINT16_NUM, \ + [17] = XCHAL_EXTINT17_NUM, \ + [18] = XCHAL_EXTINT18_NUM, \ + [19] = XCHAL_EXTINT19_NUM, \ + [20] = XCHAL_EXTINT20_NUM, \ + [21] = XCHAL_EXTINT21_NUM, \ + [22] = XCHAL_EXTINT22_NUM, \ + [23] = XCHAL_EXTINT23_NUM, \ + [24] = XCHAL_EXTINT24_NUM, \ + [25] = XCHAL_EXTINT25_NUM, \ + [26] = XCHAL_EXTINT26_NUM, \ + [27] = XCHAL_EXTINT27_NUM, \ + [28] = XCHAL_EXTINT28_NUM, \ + [29] = XCHAL_EXTINT29_NUM, \ + [30] = XCHAL_EXTINT30_NUM, \ + [31] = XCHAL_EXTINT31_NUM, \ + } + +#define EXCEPTIONS_SECTION \ + .excm_level = XCHAL_EXCM_LEVEL, \ + .vecbase = XCHAL_VECBASE_RESET_VADDR, \ + .exception_vector = EXCEPTION_VECTORS + +#define INTERRUPTS_SECTION \ + .ninterrupt = XCHAL_NUM_INTERRUPTS, \ + .nlevel = XCHAL_NUM_INTLEVELS, \ + .interrupt_vector = INTERRUPT_VECTORS, \ + .level_mask = LEVEL_MASKS, \ + .inttype_mask = INTTYPE_MASKS, \ + .interrupt = INTERRUPTS, \ + .nccompare = XCHAL_NUM_TIMERS, \ + .timerint = TIMERINTS, \ + .nextint = XCHAL_NUM_EXTINTERRUPTS, \ + .extint = EXTINTS + +#define TLB_TEMPLATE(ways, refill_way_size, way56) { \ + .nways = ways, \ + .way_size = { \ + (refill_way_size), (refill_way_size), \ + (refill_way_size), (refill_way_size), \ + 4, 2, 2, 1, 1, 1, \ + }, \ + .varway56 = (way56), \ + .nrefillentries = (refill_way_size) * 4, \ + } + +#define ITLB(varway56) \ + TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56) + +#define DTLB(varway56) \ + TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56) + +#if XCHAL_HAVE_PTP_MMU +#define TLB_SECTION \ + .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \ + .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY) +#else +#endif + +#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0) +#define REGISTER_CORE(core) \ + static void __attribute__((constructor)) register_core(void) \ + { \ + static XtensaConfigList node = { \ + .config = &core, \ + }; \ + xtensa_register_core(&node); \ + } +#else +#define REGISTER_CORE(core) +#endif + + +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7 +#define XCHAL_INTLEVEL7_VECTOR_VADDR 0 +#endif + + +#if XCHAL_NUM_INTERRUPTS <= 0 +#define XCHAL_INT0_LEVEL 0 +#define XCHAL_INT0_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 1 +#define XCHAL_INT1_LEVEL 0 +#define XCHAL_INT1_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 2 +#define XCHAL_INT2_LEVEL 0 +#define XCHAL_INT2_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 3 +#define XCHAL_INT3_LEVEL 0 +#define XCHAL_INT3_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 4 +#define XCHAL_INT4_LEVEL 0 +#define XCHAL_INT4_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 5 +#define XCHAL_INT5_LEVEL 0 +#define XCHAL_INT5_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 6 +#define XCHAL_INT6_LEVEL 0 +#define XCHAL_INT6_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 7 +#define XCHAL_INT7_LEVEL 0 +#define XCHAL_INT7_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 8 +#define XCHAL_INT8_LEVEL 0 +#define XCHAL_INT8_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 9 +#define XCHAL_INT9_LEVEL 0 +#define XCHAL_INT9_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 10 +#define XCHAL_INT10_LEVEL 0 +#define XCHAL_INT10_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 11 +#define XCHAL_INT11_LEVEL 0 +#define XCHAL_INT11_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 12 +#define XCHAL_INT12_LEVEL 0 +#define XCHAL_INT12_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 13 +#define XCHAL_INT13_LEVEL 0 +#define XCHAL_INT13_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 14 +#define XCHAL_INT14_LEVEL 0 +#define XCHAL_INT14_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 15 +#define XCHAL_INT15_LEVEL 0 +#define XCHAL_INT15_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 16 +#define XCHAL_INT16_LEVEL 0 +#define XCHAL_INT16_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 17 +#define XCHAL_INT17_LEVEL 0 +#define XCHAL_INT17_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 18 +#define XCHAL_INT18_LEVEL 0 +#define XCHAL_INT18_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 19 +#define XCHAL_INT19_LEVEL 0 +#define XCHAL_INT19_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 20 +#define XCHAL_INT20_LEVEL 0 +#define XCHAL_INT20_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 21 +#define XCHAL_INT21_LEVEL 0 +#define XCHAL_INT21_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 22 +#define XCHAL_INT22_LEVEL 0 +#define XCHAL_INT22_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 23 +#define XCHAL_INT23_LEVEL 0 +#define XCHAL_INT23_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 24 +#define XCHAL_INT24_LEVEL 0 +#define XCHAL_INT24_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 25 +#define XCHAL_INT25_LEVEL 0 +#define XCHAL_INT25_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 26 +#define XCHAL_INT26_LEVEL 0 +#define XCHAL_INT26_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 27 +#define XCHAL_INT27_LEVEL 0 +#define XCHAL_INT27_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 28 +#define XCHAL_INT28_LEVEL 0 +#define XCHAL_INT28_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 29 +#define XCHAL_INT29_LEVEL 0 +#define XCHAL_INT29_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 30 +#define XCHAL_INT30_LEVEL 0 +#define XCHAL_INT30_TYPE 0 +#endif +#if XCHAL_NUM_INTERRUPTS <= 31 +#define XCHAL_INT31_LEVEL 0 +#define XCHAL_INT31_TYPE 0 +#endif + + +#if XCHAL_NUM_EXTINTERRUPTS <= 0 +#define XCHAL_EXTINT0_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 1 +#define XCHAL_EXTINT1_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 2 +#define XCHAL_EXTINT2_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 3 +#define XCHAL_EXTINT3_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 4 +#define XCHAL_EXTINT4_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 5 +#define XCHAL_EXTINT5_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 6 +#define XCHAL_EXTINT6_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 7 +#define XCHAL_EXTINT7_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 8 +#define XCHAL_EXTINT8_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 9 +#define XCHAL_EXTINT9_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 10 +#define XCHAL_EXTINT10_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 11 +#define XCHAL_EXTINT11_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 12 +#define XCHAL_EXTINT12_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 13 +#define XCHAL_EXTINT13_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 14 +#define XCHAL_EXTINT14_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 15 +#define XCHAL_EXTINT15_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 16 +#define XCHAL_EXTINT16_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 17 +#define XCHAL_EXTINT17_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 18 +#define XCHAL_EXTINT18_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 19 +#define XCHAL_EXTINT19_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 20 +#define XCHAL_EXTINT20_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 21 +#define XCHAL_EXTINT21_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 22 +#define XCHAL_EXTINT22_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 23 +#define XCHAL_EXTINT23_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 24 +#define XCHAL_EXTINT24_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 25 +#define XCHAL_EXTINT25_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 26 +#define XCHAL_EXTINT26_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 27 +#define XCHAL_EXTINT27_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 28 +#define XCHAL_EXTINT28_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 29 +#define XCHAL_EXTINT29_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 30 +#define XCHAL_EXTINT30_NUM 0 +#endif +#if XCHAL_NUM_EXTINTERRUPTS <= 31 +#define XCHAL_EXTINT31_NUM 0 +#endif + + +#define XTHAL_TIMER_UNCONFIGURED 0 diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 93a807e8c0..1688bb2462 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -79,6 +79,12 @@ static const char * const sregnames[256] = { [BR] = "BR", [LITBASE] = "LITBASE", [SCOMPARE1] = "SCOMPARE1", + [ACCLO] = "ACCLO", + [ACCHI] = "ACCHI", + [MR] = "MR0", + [MR + 1] = "MR1", + [MR + 2] = "MR2", + [MR + 3] = "MR3", [WINDOW_BASE] = "WINDOW_BASE", [WINDOW_START] = "WINDOW_START", [PTEVADDR] = "PTEVADDR", @@ -447,6 +453,11 @@ static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s) gen_jumpi_check_loop_end(dc, -1); } +static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s) +{ + tcg_gen_ext8s_i32(cpu_SR[sr], s); +} + static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) { gen_helper_wsr_windowbase(v); @@ -544,6 +555,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) [SAR] = gen_wsr_sar, [BR] = gen_wsr_br, [LITBASE] = gen_wsr_litbase, + [ACCHI] = gen_wsr_acchi, [WINDOW_BASE] = gen_wsr_windowbase, [WINDOW_START] = gen_wsr_windowstart, [PTEVADDR] = gen_wsr_ptevaddr, @@ -628,6 +640,18 @@ static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2, gen_window_check2(dc, r1, r2 > r3 ? r2 : r3); } +static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) +{ + TCGv_i32 m = tcg_temp_new_i32(); + + if (hi) { + (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16); + } else { + (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v); + } + return m; +} + static void disas_xtensa_insn(DisasContext *dc) { #define HAS_OPTION_BITS(opt) do { \ @@ -663,6 +687,9 @@ static void disas_xtensa_insn(DisasContext *dc) #define RRR_S (((b1) & 0xf)) #define RRR_T (((b0) & 0xf0) >> 4) #endif +#define RRR_X ((RRR_R & 0x4) >> 2) +#define RRR_Y ((RRR_T & 0x4) >> 2) +#define RRR_W (RRR_R & 0x3) #define RRRN_R RRR_R #define RRRN_S RRR_S @@ -1089,13 +1116,13 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 14: /*NSAu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP); + HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); gen_window_check2(dc, RRR_S, RRR_T); gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]); break; case 15: /*NSAUu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP); + HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); gen_window_check2(dc, RRR_S, RRR_T); gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]); break; @@ -1407,7 +1434,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 10: /*MULUHi*/ case 11: /*MULSHi*/ - HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL); + HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH); { TCGv_i64 r = tcg_temp_new_i64(); TCGv_i64 s = tcg_temp_new_i64(); @@ -1494,7 +1521,7 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 2: /*SEXTu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP); + HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT); gen_window_check2(dc, RRR_R, RRR_S); { int shift = 24 - RRR_T; @@ -1513,7 +1540,7 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 3: /*CLAMPSu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP); + HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS); gen_window_check2(dc, RRR_R, RRR_S); { TCGv_i32 tmp1 = tcg_temp_new_i32(); @@ -1541,7 +1568,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 5: /*MAXu*/ case 6: /*MINUu*/ case 7: /*MAXUu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP); + HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX); gen_window_check3(dc, RRR_R, RRR_S, RRR_T); { static const TCGCond cond[] = { @@ -1894,7 +1921,7 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 14: /*S32C1Iy*/ - HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); + HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE); gen_window_check2(dc, RRI8_S, RRI8_T); { int label = gen_new_label(); @@ -1935,7 +1962,113 @@ static void disas_xtensa_insn(DisasContext *dc) case 4: /*MAC16d*/ HAS_OPTION(XTENSA_OPTION_MAC16); - TBD(); + { + enum { + MAC16_UMUL = 0x0, + MAC16_MUL = 0x4, + MAC16_MULA = 0x8, + MAC16_MULS = 0xc, + MAC16_NONE = 0xf, + } op = OP1 & 0xc; + bool is_m1_sr = (OP2 & 0x3) == 2; + bool is_m2_sr = (OP2 & 0xc) == 0; + uint32_t ld_offset = 0; + + if (OP2 > 9) { + RESERVED(); + } + + switch (OP2 & 2) { + case 0: /*MACI?/MACC?*/ + is_m1_sr = true; + ld_offset = (OP2 & 1) ? -4 : 4; + + if (OP2 >= 8) { /*MACI/MACC*/ + if (OP1 == 0) { /*LDINC/LDDEC*/ + op = MAC16_NONE; + } else { + RESERVED(); + } + } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/ + RESERVED(); + } + break; + + case 2: /*MACD?/MACA?*/ + if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/ + RESERVED(); + } + break; + } + + if (op != MAC16_NONE) { + if (!is_m1_sr) { + gen_window_check1(dc, RRR_S); + } + if (!is_m2_sr) { + gen_window_check1(dc, RRR_T); + } + } + + { + TCGv_i32 vaddr = tcg_temp_new_i32(); + TCGv_i32 mem32 = tcg_temp_new_i32(); + + if (ld_offset) { + gen_window_check1(dc, RRR_S); + tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset); + gen_load_store_alignment(dc, 2, vaddr, false); + tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); + } + if (op != MAC16_NONE) { + TCGv_i32 m1 = gen_mac16_m( + is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S], + OP1 & 1, op == MAC16_UMUL); + TCGv_i32 m2 = gen_mac16_m( + is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T], + OP1 & 2, op == MAC16_UMUL); + + if (op == MAC16_MUL || op == MAC16_UMUL) { + tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); + if (op == MAC16_UMUL) { + tcg_gen_movi_i32(cpu_SR[ACCHI], 0); + } else { + tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31); + } + } else { + TCGv_i32 res = tcg_temp_new_i32(); + TCGv_i64 res64 = tcg_temp_new_i64(); + TCGv_i64 tmp = tcg_temp_new_i64(); + + tcg_gen_mul_i32(res, m1, m2); + tcg_gen_ext_i32_i64(res64, res); + tcg_gen_concat_i32_i64(tmp, + cpu_SR[ACCLO], cpu_SR[ACCHI]); + if (op == MAC16_MULA) { + tcg_gen_add_i64(tmp, tmp, res64); + } else { + tcg_gen_sub_i64(tmp, tmp, res64); + } + tcg_gen_trunc_i64_i32(cpu_SR[ACCLO], tmp); + tcg_gen_shri_i64(tmp, tmp, 32); + tcg_gen_trunc_i64_i32(cpu_SR[ACCHI], tmp); + tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); + + tcg_temp_free(res); + tcg_temp_free_i64(res64); + tcg_temp_free_i64(tmp); + } + tcg_temp_free(m1); + tcg_temp_free(m2); + } + if (ld_offset) { + tcg_gen_mov_i32(cpu_R[RRR_S], vaddr); + tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32); + } + tcg_temp_free(vaddr); + tcg_temp_free(mem32); + } + } break; case 5: /*CALLN*/ @@ -175,7 +175,7 @@ typedef enum TCGType { typedef tcg_target_ulong TCGArg; -/* Define a type and accessor macros for varables. Using a struct is +/* Define a type and accessor macros for variables. Using a struct is nice because it gives some level of type safely. Ideally the compiler be able to see through all this. However in practice this is not true, expecially on targets with braindamaged ABIs (e.g. i386). diff --git a/tests/xtensa/Makefile b/tests/xtensa/Makefile index 70bd097ec4..8713af16eb 100644 --- a/tests/xtensa/Makefile +++ b/tests/xtensa/Makefile @@ -4,7 +4,7 @@ CROSS=xtensa-dc232b-elf- ifndef XT SIM = qemu-system-xtensa -SIMFLAGS = -M dc232b -nographic -semihosting $(EXTFLAGS) -kernel +SIMFLAGS = -M sim -cpu dc232b -nographic -semihosting $(EXTFLAGS) -kernel SIMDEBUG = -s -S else SIM = xt-run @@ -28,6 +28,7 @@ TESTCASES += test_clamps.tst TESTCASES += test_fail.tst TESTCASES += test_interrupt.tst TESTCASES += test_loop.tst +TESTCASES += test_mac16.tst TESTCASES += test_max.tst TESTCASES += test_min.tst TESTCASES += test_mmu.tst diff --git a/tests/xtensa/test_mac16.S b/tests/xtensa/test_mac16.S new file mode 100644 index 0000000000..5ddd160ffc --- /dev/null +++ b/tests/xtensa/test_mac16.S @@ -0,0 +1,243 @@ +.include "macros.inc" + +test_suite mac16 + +#define ext16(v) (((v) & 0xffff) | (((v) & 0x8000) * 0x1ffffffe)) +#define mul16(a, b) ((ext16(a) * ext16(b))) + +.macro assert_acc_value v + rsr a4, ACCLO + movi a5, (\v) & 0xffffffff + assert eq, a4, a5 + rsr a4, ACCHI + movi a5, (\v) >> 32 + sext a5, a5, 7 + assert eq, a4, a5 +.endm + +.macro init_reg sr, reg, val + .if (\sr) + movi a4, \val + wsr a4, \reg + .else + movi \reg, \val + .endif +.endm + +.macro test_mulxx mulop, comb, s, t, a, b + init_reg \comb & 2, \s, \a + init_reg \comb & 1, \t, \b + + \mulop\().ll \s, \t + assert_acc_value mul16(\a, \b) + + \mulop\().lh \s, \t + assert_acc_value mul16(\a, (\b >> 16)) + + \mulop\().hl \s, \t + assert_acc_value mul16((\a >> 16), \b) + + \mulop\().hh \s, \t + assert_acc_value mul16((\a >> 16), (\b >> 16)) +.endm + +test mul_aa + test_mulxx mul.aa, 0, a2, a3, 0xf7315a5a, 0xa5a5137f +test_end + +test mul_ad + test_mulxx mul.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f +test_end + +test mul_da + test_mulxx mul.da, 2, m1, a3, 0xf7315a5a, 0xa5a5137f +test_end + +test mul_dd + test_mulxx mul.dd, 3, m0, m3, 0xf7315a5a, 0xa5a5137f +test_end + + +.macro init_acc iv + movi a4, (\iv) & 0xffffffff + wsr a4, ACCLO + movi a4, (\iv) >> 32 + wsr a4, ACCHI +.endm + +.macro test_mulxxx mulop, comb, s, t, a, b, iv, op + init_reg \comb & 2, \s, \a + init_reg \comb & 1, \t, \b + + init_acc \iv + \mulop\().ll \s, \t + assert_acc_value (\iv \op mul16(\a, \b)) + + init_acc \iv + \mulop\().lh \s, \t + assert_acc_value (\iv \op mul16(\a, (\b >> 16))) + + init_acc \iv + \mulop\().hl \s, \t + assert_acc_value (\iv \op mul16((\a >> 16), \b)) + + init_acc \iv + \mulop\().hh \s, \t + assert_acc_value (\iv \op mul16((\a >> 16), (\b >> 16))) +.endm + + +test mula_aa + test_mulxxx mula.aa, 0, a2, a3, 0xf7315a5a, 0xa5a5137f, 0xfff73155aa, + +test_end + +test mula_ad + test_mulxxx mula.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f, 0xfff73155aa, + +test_end + +test mula_da + test_mulxxx mula.da, 2, m1, a3, 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, + +test_end + +test mula_dd + test_mulxxx mula.dd, 3, m0, m3, 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, + +test_end + + +test muls_aa + test_mulxxx muls.aa, 0, a2, a3, 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, - +test_end + +test muls_ad + test_mulxxx muls.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, - +test_end + +test muls_da + test_mulxxx muls.da, 2, m1, a3, 0xf7315a5a, 0xa5a5137f, 0xfff73155aa, - +test_end + +test muls_dd + test_mulxxx muls.dd, 3, m0, m3, 0xf7315a5a, 0xa5a5137f, 0xfff73155aa, - +test_end + +test ldinc + movi a2, 1f - 4 + ldinc m0, a2 + movi a3, 1f + assert eq, a2, a3 + rsr a3, m0 + movi a4, 0x55aa137f + assert eq, a3, a4 + ldinc m1, a2 + movi a3, 1f + 4 + assert eq, a2, a3 + rsr a3, m1 + movi a4, 0x12345678 + assert eq, a3, a4 + +.data +1: .word 0x55aa137f, 0x12345678, 0x137fa5a5 +.text +test_end + +test lddec + movi a2, 1f + lddec m2, a2 + movi a3, 1f - 4 + assert eq, a2, a3 + rsr a3, m2 + movi a4, 0x12345678 + assert eq, a3, a4 + lddec m3, a2 + movi a3, 1f - 8 + assert eq, a2, a3 + rsr a3, m3 + movi a4, 0x55aa137f + assert eq, a3, a4 +.data + .word 0x55aa137f, 0x12345678 +1: +.text +test_end + + +.macro test_mulxxx_ld mulop, ldop, comb, w, x, s, t, a, b, iv, op + init_reg \comb & 2, \s, \a + init_reg \comb & 1, \t, \b + + init_acc \iv + \mulop\().ll.\ldop \w, \x, \s, \t + assert_acc_value (\iv \op mul16(\a, \b)) + + init_acc \iv + \mulop\().lh.\ldop \w, \x, \s, \t + assert_acc_value (\iv \op mul16(\a, (\b >> 16))) + + init_acc \iv + \mulop\().hl.\ldop \w, \x, \s, \t + assert_acc_value (\iv \op mul16((\a >> 16), \b)) + + init_acc \iv + \mulop\().hh.\ldop \w, \x, \s, \t + assert_acc_value (\iv \op mul16((\a >> 16), (\b >> 16))) +.endm + +test mula_da_ldinc + movi a2, 1f - 4 + test_mulxxx_ld mula.da, ldinc, 2, m1, a2, m1, a3, \ + 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, + + movi a3, 1f + 12 + assert eq, a2, a3 + rsr a2, m1 + movi a3, 0x12345678 + assert eq, a2, a3 +.data +1: .word 0xf7315a5a, 0xf7315a5a, 0xf7315a5a, 0x12345678 +.text +test_end + +test mula_dd_ldinc + movi a2, 1f - 4 + test_mulxxx_ld mula.dd, ldinc, 3, m2, a2, m1, m2, \ + 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, + + movi a3, 1f + 12 + assert eq, a2, a3 + rsr a2, m2 + movi a3, 0x12345678 + assert eq, a2, a3 +.data +1: .word 0xa5a5137f, 0xa5a5137f, 0xa5a5137f, 0x12345678 +.text +test_end + +test mula_da_lddec + movi a2, 1f + test_mulxxx_ld mula.da, lddec, 2, m1, a2, m1, a3, \ + 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, + + movi a3, 1f - 16 + assert eq, a2, a3 + rsr a2, m1 + movi a3, 0x12345678 + assert eq, a2, a3 +.data + .word 0x12345678, 0xf7315a5a, 0xf7315a5a, 0xf7315a5a +1: +.text +test_end + +test mula_dd_lddec + movi a2, 1f + test_mulxxx_ld mula.dd, lddec, 3, m2, a2, m1, m2, \ + 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, + + movi a3, 1f - 16 + assert eq, a2, a3 + rsr a2, m2 + movi a3, 0x12345678 + assert eq, a2, a3 +.data + .word 0x12345678, 0xa5a5137f, 0xa5a5137f, 0xa5a5137f +1: +.text +test_end + +test_suite_end diff --git a/tests/xtensa/test_timer.S b/tests/xtensa/test_timer.S index ede63955cc..1041cc6658 100644 --- a/tests/xtensa/test_timer.S +++ b/tests/xtensa/test_timer.S @@ -14,6 +14,7 @@ test ccompare wsr a2, intenable rsr a2, interrupt wsr a2, intclear + movi a2, 0 wsr a2, ccompare1 wsr a2, ccompare2 @@ -37,6 +38,7 @@ test ccompare0_interrupt wsr a2, intenable rsr a2, interrupt wsr a2, intclear + movi a2, 0 wsr a2, ccompare1 wsr a2, ccompare2 @@ -66,6 +68,7 @@ test ccompare1_interrupt wsr a2, intenable rsr a2, interrupt wsr a2, intclear + movi a2, 0 wsr a2, ccompare0 wsr a2, ccompare2 @@ -92,6 +95,7 @@ test ccompare2_interrupt wsr a2, intenable rsr a2, interrupt wsr a2, intclear + movi a2, 0 wsr a2, ccompare0 wsr a2, ccompare1 @@ -112,4 +116,63 @@ test ccompare2_interrupt 2: test_end +test ccompare_interrupt_masked + set_vector kernel, 2f + movi a2, 0 + wsr a2, intenable + rsr a2, interrupt + wsr a2, intclear + movi a2, 0 + wsr a2, ccompare2 + + movi a3, 40 + rsr a2, ccount + addi a2, a2, 20 + wsr a2, ccompare1 + addi a2, a2, 20 + wsr a2, ccompare0 + rsync + rsr a2, interrupt + assert eqi, a2, 0 + + movi a2, 0x40 + wsr a2, intenable + rsil a2, 0 + loop a3, 1f + nop +1: + test_fail +2: + rsr a2, exccause + assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ +test_end + +test ccompare_interrupt_masked_waiti + set_vector kernel, 2f + movi a2, 0 + wsr a2, intenable + rsr a2, interrupt + wsr a2, intclear + movi a2, 0 + wsr a2, ccompare2 + + movi a3, 40 + rsr a2, ccount + addi a2, a2, 20 + wsr a2, ccompare1 + addi a2, a2, 20 + wsr a2, ccompare0 + rsync + rsr a2, interrupt + assert eqi, a2, 0 + + movi a2, 0x40 + wsr a2, intenable + waiti 0 + test_fail +2: + rsr a2, exccause + assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ +test_end + test_suite_end diff --git a/trace-events b/trace-events index cbbc4aa192..fc13733250 100644 --- a/trace-events +++ b/trace-events @@ -539,6 +539,20 @@ esp_mem_writeb_cmd_ensel(uint32_t val) "Enable selection (%2.2x)" handle_qmp_command(void *mon, const char *cmd_name) "mon %p cmd_name \"%s\"" monitor_protocol_emitter(void *mon) "mon %p" +# hw/opencores_eth.c +open_eth_mii_write(unsigned idx, uint16_t v) "MII[%02x] <- %04x" +open_eth_mii_read(unsigned idx, uint16_t v) "MII[%02x] -> %04x" +open_eth_update_irq(uint32_t v) "IRQ <- %x" +open_eth_receive(unsigned len) "RX: len: %u" +open_eth_receive_mcast(unsigned idx, uint32_t h0, uint32_t h1) "MCAST: idx = %u, hash: %08x:%08x" +open_eth_receive_reject(void) "RX: rejected" +open_eth_receive_desc(uint32_t addr, uint32_t len_flags) "RX: %08x, len_flags: %08x" +open_eth_start_xmit(uint32_t addr, unsigned len, unsigned tx_len) "TX: %08x, len: %u, tx_len: %u" +open_eth_reg_read(uint32_t addr, uint32_t v) "MAC[%02x] -> %08x" +open_eth_reg_write(uint32_t addr, uint32_t v) "MAC[%02x] <- %08x" +open_eth_desc_read(uint32_t addr, uint32_t v) "DESC[%04x] -> %08x" +open_eth_desc_write(uint32_t addr, uint32_t v) "DESC[%04x] <- %08x" + # hw/9pfs/virtio-9p.c complete_pdu(uint16_t tag, uint8_t id, int err) "tag %d id %d err %d" v9fs_version(uint16_t tag, uint8_t id, int32_t msize, char* version) "tag %d id %d msize %d version %s" diff --git a/usb-linux.c b/usb-linux.c index 2075c4c67a..7d4d1d7bcf 100644 --- a/usb-linux.c +++ b/usb-linux.c @@ -411,6 +411,100 @@ static void usb_host_async_cancel(USBDevice *dev, USBPacket *p) } } +static int usb_host_claim_port(USBHostDevice *s) +{ +#ifdef USBDEVFS_CLAIM_PORT + char *h, hub_name[64], line[1024]; + int hub_addr, portnr, ret; + + snprintf(hub_name, sizeof(hub_name), "%d-%s", + s->match.bus_num, s->match.port); + + /* try strip off last ".$portnr" to get hub */ + h = strrchr(hub_name, '.'); + if (h != NULL) { + portnr = atoi(h+1); + *h = '\0'; + } else { + /* no dot in there -> it is the root hub */ + snprintf(hub_name, sizeof(hub_name), "usb%d", + s->match.bus_num); + portnr = atoi(s->match.port); + } + + if (!usb_host_read_file(line, sizeof(line), "devnum", + hub_name)) { + return -1; + } + if (sscanf(line, "%d", &hub_addr) != 1) { + return -1; + } + + if (!usb_host_device_path) { + return -1; + } + snprintf(line, sizeof(line), "%s/%03d/%03d", + usb_host_device_path, s->match.bus_num, hub_addr); + s->hub_fd = open(line, O_RDWR | O_NONBLOCK); + if (s->hub_fd < 0) { + return -1; + } + + ret = ioctl(s->hub_fd, USBDEVFS_CLAIM_PORT, &portnr); + if (ret < 0) { + close(s->hub_fd); + s->hub_fd = -1; + return -1; + } + + trace_usb_host_claim_port(s->match.bus_num, hub_addr, portnr); + return 0; +#else + return -1; +#endif +} + +static int usb_host_disconnect_ifaces(USBHostDevice *dev, int nb_interfaces) +{ + /* earlier Linux 2.4 do not support that */ +#ifdef USBDEVFS_DISCONNECT + struct usbdevfs_ioctl ctrl; + int ret, interface; + + for (interface = 0; interface < nb_interfaces; interface++) { + ctrl.ioctl_code = USBDEVFS_DISCONNECT; + ctrl.ifno = interface; + ctrl.data = 0; + ret = ioctl(dev->fd, USBDEVFS_IOCTL, &ctrl); + if (ret < 0 && errno != ENODATA) { + perror("USBDEVFS_DISCONNECT"); + return -1; + } + } +#endif + return 0; +} + +static int usb_linux_get_num_interfaces(USBHostDevice *s) +{ + char device_name[64], line[1024]; + int num_interfaces = 0; + + if (usb_fs_type != USB_FS_SYS) { + return -1; + } + + sprintf(device_name, "%d-%s", s->bus_num, s->port); + if (!usb_host_read_file(line, sizeof(line), "bNumInterfaces", + device_name)) { + return -1; + } + if (sscanf(line, "%d", &num_interfaces) != 1) { + return -1; + } + return num_interfaces; +} + static int usb_host_claim_interfaces(USBHostDevice *dev, int configuration) { const char *op = NULL; @@ -462,22 +556,9 @@ static int usb_host_claim_interfaces(USBHostDevice *dev, int configuration) } nb_interfaces = dev->descr[i + 4]; -#ifdef USBDEVFS_DISCONNECT - /* earlier Linux 2.4 do not support that */ - { - struct usbdevfs_ioctl ctrl; - for (interface = 0; interface < nb_interfaces; interface++) { - ctrl.ioctl_code = USBDEVFS_DISCONNECT; - ctrl.ifno = interface; - ctrl.data = 0; - op = "USBDEVFS_DISCONNECT"; - ret = ioctl(dev->fd, USBDEVFS_IOCTL, &ctrl); - if (ret < 0 && errno != ENODATA) { - goto fail; - } - } + if (usb_host_disconnect_ifaces(dev, nb_interfaces) < 0) { + goto fail; } -#endif /* XXX: only grab if all interfaces are free */ for (interface = 0; interface < nb_interfaces; interface++) { @@ -840,14 +921,28 @@ static int usb_host_set_address(USBHostDevice *s, int addr) static int usb_host_set_config(USBHostDevice *s, int config) { + int ret, first = 1; + trace_usb_host_set_config(s->bus_num, s->addr, config); usb_host_release_interfaces(s); - int ret = ioctl(s->fd, USBDEVFS_SETCONFIGURATION, &config); +again: + ret = ioctl(s->fd, USBDEVFS_SETCONFIGURATION, &config); DPRINTF("husb: ctrl set config %d ret %d errno %d\n", config, ret, errno); + if (ret < 0 && errno == EBUSY && first) { + /* happens if usb device is in use by host drivers */ + int count = usb_linux_get_num_interfaces(s); + if (count > 0) { + DPRINTF("husb: busy -> disconnecting %d interfaces\n", count); + usb_host_disconnect_ifaces(s, count); + first = 0; + goto again; + } + } + if (ret < 0) { return ctrl_error(); } @@ -1301,56 +1396,9 @@ static int usb_host_initfn(USBDevice *dev) qemu_add_exit_notifier(&s->exit); usb_host_auto_check(NULL); -#ifdef USBDEVFS_CLAIM_PORT if (s->match.bus_num != 0 && s->match.port != NULL) { - char *h, hub_name[64], line[1024]; - int hub_addr, portnr, ret; - - snprintf(hub_name, sizeof(hub_name), "%d-%s", - s->match.bus_num, s->match.port); - - /* try strip off last ".$portnr" to get hub */ - h = strrchr(hub_name, '.'); - if (h != NULL) { - portnr = atoi(h+1); - *h = '\0'; - } else { - /* no dot in there -> it is the root hub */ - snprintf(hub_name, sizeof(hub_name), "usb%d", - s->match.bus_num); - portnr = atoi(s->match.port); - } - - if (!usb_host_read_file(line, sizeof(line), "devnum", - hub_name)) { - goto out; - } - if (sscanf(line, "%d", &hub_addr) != 1) { - goto out; - } - - if (!usb_host_device_path) { - goto out; - } - snprintf(line, sizeof(line), "%s/%03d/%03d", - usb_host_device_path, s->match.bus_num, hub_addr); - s->hub_fd = open(line, O_RDWR | O_NONBLOCK); - if (s->hub_fd < 0) { - goto out; - } - - ret = ioctl(s->hub_fd, USBDEVFS_CLAIM_PORT, &portnr); - if (ret < 0) { - close(s->hub_fd); - s->hub_fd = -1; - goto out; - } - - trace_usb_host_claim_port(s->match.bus_num, hub_addr, portnr); + usb_host_claim_port(s); } -out: -#endif - return 0; } @@ -248,8 +248,6 @@ int nb_numa_nodes; uint64_t node_mem[MAX_NODES]; uint64_t node_cpumask[MAX_NODES]; -static QEMUTimer *nographic_timer; - uint8_t qemu_uuid[16]; static QEMUBootSetHandler *boot_set_handler; @@ -339,16 +337,20 @@ static const RunStateTransition runstate_transitions_def[] = { { RUN_STATE_INMIGRATE, RUN_STATE_PRELAUNCH }, { RUN_STATE_INTERNAL_ERROR, RUN_STATE_PAUSED }, + { RUN_STATE_INTERNAL_ERROR, RUN_STATE_FINISH_MIGRATE }, { RUN_STATE_IO_ERROR, RUN_STATE_RUNNING }, + { RUN_STATE_IO_ERROR, RUN_STATE_FINISH_MIGRATE }, { RUN_STATE_PAUSED, RUN_STATE_RUNNING }, + { RUN_STATE_PAUSED, RUN_STATE_FINISH_MIGRATE }, { RUN_STATE_POSTMIGRATE, RUN_STATE_RUNNING }, + { RUN_STATE_POSTMIGRATE, RUN_STATE_FINISH_MIGRATE }, { RUN_STATE_PRELAUNCH, RUN_STATE_RUNNING }, + { RUN_STATE_PRELAUNCH, RUN_STATE_FINISH_MIGRATE }, { RUN_STATE_PRELAUNCH, RUN_STATE_INMIGRATE }, - { RUN_STATE_PRELAUNCH, RUN_STATE_POSTMIGRATE }, { RUN_STATE_FINISH_MIGRATE, RUN_STATE_RUNNING }, { RUN_STATE_FINISH_MIGRATE, RUN_STATE_POSTMIGRATE }, @@ -368,8 +370,10 @@ static const RunStateTransition runstate_transitions_def[] = { { RUN_STATE_SAVE_VM, RUN_STATE_RUNNING }, { RUN_STATE_SHUTDOWN, RUN_STATE_PAUSED }, + { RUN_STATE_SHUTDOWN, RUN_STATE_FINISH_MIGRATE }, { RUN_STATE_WATCHDOG, RUN_STATE_RUNNING }, + { RUN_STATE_WATCHDOG, RUN_STATE_FINISH_MIGRATE }, { RUN_STATE_MAX, RUN_STATE_MAX }, }; @@ -395,9 +399,12 @@ void runstate_init(void) /* This function will abort() on invalid state transitions */ void runstate_set(RunState new_state) { - if (new_state >= RUN_STATE_MAX || - !runstate_valid_transitions[current_run_state][new_state]) { - fprintf(stderr, "invalid runstate transition\n"); + assert(new_state < RUN_STATE_MAX); + + if (!runstate_valid_transitions[current_run_state][new_state]) { + fprintf(stderr, "ERROR: invalid runstate transition: '%s' -> '%s'\n", + RunState_lookup[current_run_state], + RunState_lookup[new_state]); abort(); } @@ -1196,7 +1203,6 @@ static void gui_update(void *opaque) DisplayState *ds = opaque; DisplayChangeListener *dcl = ds->listeners; - qemu_flush_coalesced_mmio_buffer(); dpy_refresh(ds); while (dcl != NULL) { @@ -1208,14 +1214,6 @@ static void gui_update(void *opaque) qemu_mod_timer(ds->gui_timer, interval + qemu_get_clock_ms(rt_clock)); } -static void nographic_update(void *opaque) -{ - uint64_t interval = GUI_REFRESH_INTERVAL; - - qemu_flush_coalesced_mmio_buffer(); - qemu_mod_timer(nographic_timer, interval + qemu_get_clock_ms(rt_clock)); -} - struct vm_change_state_entry { VMChangeStateHandler *cb; void *opaque; @@ -3525,10 +3523,6 @@ int main(int argc, char **argv, char **envp) } dcl = dcl->next; } - if (ds->gui_timer == NULL) { - nographic_timer = qemu_new_timer_ms(rt_clock, nographic_update, NULL); - qemu_mod_timer(nographic_timer, qemu_get_clock_ms(rt_clock)); - } text_consoles_set_display(ds); if (gdbstub_dev && gdbserver_start(gdbstub_dev) < 0) { |