diff options
| -rw-r--r-- | Makefile.target | 4 | ||||
| -rw-r--r-- | hw/i8259.c | 145 | ||||
| -rw-r--r-- | hw/ide.c | 6 | ||||
| -rw-r--r-- | hw/pc.c | 29 | ||||
| -rw-r--r-- | hw/ppc_chrp.c | 9 | ||||
| -rw-r--r-- | hw/ppc_prep.c | 15 | ||||
| -rw-r--r-- | vl.c | 1 | ||||
| -rw-r--r-- | vl.h | 9 |
8 files changed, 141 insertions, 77 deletions
diff --git a/Makefile.target b/Makefile.target index 9bc08731b4..c2fed5342d 100644 --- a/Makefile.target +++ b/Makefile.target @@ -360,8 +360,8 @@ VL_OBJS+= mc146818rtc.o serial.o i8259.o i8254.o fdc.o m48t59.o VL_OBJS+= ppc_prep.o ppc_chrp.o cuda.o adb.o openpic.o heathrow_pic.o mixeng.o endif ifeq ($(TARGET_ARCH), mips) -VL_OBJS+= mips.o mips_r4k.o dma.o vga.o serial.o ne2000.o #ide.o pckbd.o -VL_OBJS+= #i8259.o i8254.o fdc.o m48t59.o +VL_OBJS+= mips_r4k.o dma.o vga.o serial.o ne2000.o i8259.o +#VL_OBJS+= #ide.o pckbd.o i8254.o fdc.o m48t59.o endif ifeq ($(TARGET_BASE_ARCH), sparc) ifeq ($(TARGET_ARCH), sparc64) diff --git a/hw/i8259.c b/hw/i8259.c index 9bfaaed1bc..1be40c909c 100644 --- a/hw/i8259.c +++ b/hw/i8259.c @@ -46,10 +46,16 @@ typedef struct PicState { uint8_t init4; /* true if 4 byte init */ uint8_t elcr; /* PIIX edge/trigger selection*/ uint8_t elcr_mask; + PicState2 *pics_state; } PicState; -/* 0 is master pic, 1 is slave pic */ -static PicState pics[2]; +struct PicState2 { + /* 0 is master pic, 1 is slave pic */ + /* XXX: better separation between the two pics */ + PicState pics[2]; + IRQRequestFunc *irq_request; + void *irq_request_opaque; +}; #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT) static int irq_level[16]; @@ -110,7 +116,7 @@ static int pic_get_irq(PicState *s) master, the IRQ coming from the slave is not taken into account for the priority computation. */ mask = s->isr; - if (s->special_fully_nested_mode && s == &pics[0]) + if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) mask &= ~(1 << 2); cur_priority = get_priority(s, mask); if (priority < cur_priority) { @@ -123,32 +129,34 @@ static int pic_get_irq(PicState *s) /* raise irq to CPU if necessary. must be called every time the active irq may change */ -static void pic_update_irq(void) +/* XXX: should not export it, but it is needed for an APIC kludge */ +void pic_update_irq(PicState2 *s) { int irq2, irq; /* first look at slave pic */ - irq2 = pic_get_irq(&pics[1]); + irq2 = pic_get_irq(&s->pics[1]); if (irq2 >= 0) { /* if irq request by slave pic, signal master PIC */ - pic_set_irq1(&pics[0], 2, 1); - pic_set_irq1(&pics[0], 2, 0); + pic_set_irq1(&s->pics[0], 2, 1); + pic_set_irq1(&s->pics[0], 2, 0); } /* look at requested irq */ - irq = pic_get_irq(&pics[0]); + irq = pic_get_irq(&s->pics[0]); if (irq >= 0) { #if defined(DEBUG_PIC) { int i; for(i = 0; i < 2; i++) { printf("pic%d: imr=%x irr=%x padd=%d\n", - i, pics[i].imr, pics[i].irr, pics[i].priority_add); + i, s->pics[i].imr, s->pics[i].irr, + s->pics[i].priority_add); } } printf("pic: cpu_interrupt\n"); #endif - cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); + s->irq_request(s->irq_request_opaque, 1); } } @@ -156,8 +164,10 @@ static void pic_update_irq(void) int64_t irq_time[16]; #endif -void pic_set_irq(int irq, int level) +void pic_set_irq_new(void *opaque, int irq, int level) { + PicState2 *s = opaque; + #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) if (level != irq_level[irq]) { #if defined(DEBUG_PIC) @@ -175,14 +185,14 @@ void pic_set_irq(int irq, int level) irq_time[irq] = qemu_get_clock(vm_clock); } #endif - pic_set_irq1(&pics[irq >> 3], irq & 7, level); - pic_update_irq(); + pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); + pic_update_irq(s); } -/* this function should be used to have the controller context */ -void pic_set_irq_new(void *opaque, int irq, int level) +/* obsolete function */ +void pic_set_irq(int irq, int level) { - pic_set_irq(irq, level); + pic_set_irq_new(isa_pic, irq, level); } /* acknowledge interrupt 'irq' */ @@ -199,43 +209,32 @@ static inline void pic_intack(PicState *s, int irq) s->irr &= ~(1 << irq); } -int cpu_get_pic_interrupt(CPUState *env) +int pic_read_irq(PicState2 *s) { int irq, irq2, intno; -#ifdef TARGET_X86_64 - intno = apic_get_interrupt(env); - if (intno >= 0) { - /* set irq request if a PIC irq is still pending */ - /* XXX: improve that */ - pic_update_irq(); - return intno; - } -#endif - /* read the irq from the PIC */ - - irq = pic_get_irq(&pics[0]); + irq = pic_get_irq(&s->pics[0]); if (irq >= 0) { - pic_intack(&pics[0], irq); + pic_intack(&s->pics[0], irq); if (irq == 2) { - irq2 = pic_get_irq(&pics[1]); + irq2 = pic_get_irq(&s->pics[1]); if (irq2 >= 0) { - pic_intack(&pics[1], irq2); + pic_intack(&s->pics[1], irq2); } else { /* spurious IRQ on slave controller */ irq2 = 7; } - intno = pics[1].irq_base + irq2; + intno = s->pics[1].irq_base + irq2; irq = irq2 + 8; } else { - intno = pics[0].irq_base + irq; + intno = s->pics[0].irq_base + irq; } } else { /* spurious IRQ on host controller */ irq = 7; - intno = pics[0].irq_base + irq; + intno = s->pics[0].irq_base + irq; } - pic_update_irq(); + pic_update_irq(s); #ifdef DEBUG_IRQ_LATENCY printf("IRQ%d latency=%0.3fus\n", @@ -251,11 +250,22 @@ int cpu_get_pic_interrupt(CPUState *env) static void pic_reset(void *opaque) { PicState *s = opaque; - int tmp; - tmp = s->elcr_mask; - memset(s, 0, sizeof(PicState)); - s->elcr_mask = tmp; + s->last_irr = 0; + s->irr = 0; + s->imr = 0; + s->isr = 0; + s->priority_add = 0; + s->irq_base = 0; + s->read_reg_select = 0; + s->poll = 0; + s->special_mask = 0; + s->init_state = 0; + s->auto_eoi = 0; + s->rotate_on_auto_eoi = 0; + s->special_fully_nested_mode = 0; + s->init4 = 0; + s->elcr = 0; } static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val) @@ -272,8 +282,7 @@ static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val) /* init */ pic_reset(s); /* deassert a pending interrupt */ - cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); - + s->pics_state->irq_request(s->pics_state->irq_request_opaque, 0); s->init_state = 1; s->init4 = val & 1; if (val & 0x02) @@ -302,23 +311,23 @@ static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val) s->isr &= ~(1 << irq); if (cmd == 5) s->priority_add = (irq + 1) & 7; - pic_update_irq(); + pic_update_irq(s->pics_state); } break; case 3: irq = val & 7; s->isr &= ~(1 << irq); - pic_update_irq(); + pic_update_irq(s->pics_state); break; case 6: s->priority_add = (val + 1) & 7; - pic_update_irq(); + pic_update_irq(s->pics_state); break; case 7: irq = val & 7; s->isr &= ~(1 << irq); s->priority_add = (irq + 1) & 7; - pic_update_irq(); + pic_update_irq(s->pics_state); break; default: /* no operation */ @@ -330,7 +339,7 @@ static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val) case 0: /* normal mode */ s->imr = val; - pic_update_irq(); + pic_update_irq(s->pics_state); break; case 1: s->irq_base = val & 0xf8; @@ -359,16 +368,16 @@ static uint32_t pic_poll_read (PicState *s, uint32_t addr1) ret = pic_get_irq(s); if (ret >= 0) { if (addr1 >> 7) { - pics[0].isr &= ~(1 << 2); - pics[0].irr &= ~(1 << 2); + s->pics_state->pics[0].isr &= ~(1 << 2); + s->pics_state->pics[0].irr &= ~(1 << 2); } s->irr &= ~(1 << ret); s->isr &= ~(1 << ret); if (addr1 >> 7 || ret != 2) - pic_update_irq(); + pic_update_irq(s->pics_state); } else { ret = 0x07; - pic_update_irq(); + pic_update_irq(s->pics_state); } return ret; @@ -402,15 +411,16 @@ static uint32_t pic_ioport_read(void *opaque, uint32_t addr1) } /* memory mapped interrupt status */ -uint32_t pic_intack_read(CPUState *env) +/* XXX: may be the same than pic_read_irq() */ +uint32_t pic_intack_read(PicState2 *s) { int ret; - ret = pic_poll_read(&pics[0], 0x00); + ret = pic_poll_read(&s->pics[0], 0x00); if (ret == 2) - ret = pic_poll_read(&pics[1], 0x80) + 8; + ret = pic_poll_read(&s->pics[1], 0x80) + 8; /* Prepare for ISR read */ - pics[0].read_reg_select = 1; + s->pics[0].read_reg_select = 1; return ret; } @@ -490,9 +500,12 @@ void pic_info(void) { int i; PicState *s; + + if (!isa_pic) + return; for(i=0;i<2;i++) { - s = &pics[i]; + s = &isa_pic->pics[i]; term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", i, s->irr, s->imr, s->isr, s->priority_add, s->irq_base, s->read_reg_select, s->elcr, @@ -517,11 +530,19 @@ void irq_info(void) #endif } -void pic_init(void) +PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque) { - pic_init1(0x20, 0x4d0, &pics[0]); - pic_init1(0xa0, 0x4d1, &pics[1]); - pics[0].elcr_mask = 0xf8; - pics[1].elcr_mask = 0xde; + PicState2 *s; + s = qemu_mallocz(sizeof(PicState2)); + if (!s) + return NULL; + pic_init1(0x20, 0x4d0, &s->pics[0]); + pic_init1(0xa0, 0x4d1, &s->pics[1]); + s->pics[0].elcr_mask = 0xf8; + s->pics[1].elcr_mask = 0xde; + s->irq_request = irq_request; + s->irq_request_opaque = irq_request_opaque; + s->pics[0].pics_state = s; + s->pics[1].pics_state = s; + return s; } - @@ -2008,7 +2008,7 @@ void isa_ide_init(int iobase, int iobase2, int irq, if (!ide_state) return; - ide_init2(ide_state, hd0, hd1, pic_set_irq_new, NULL, irq); + ide_init2(ide_state, hd0, hd1, pic_set_irq_new, isa_pic, irq); ide_init_ioport(ide_state, iobase, iobase2); } @@ -2337,9 +2337,9 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table) PCI_ADDRESS_SPACE_IO, bmdma_map); ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], - pic_set_irq_new, NULL, 14); + pic_set_irq_new, isa_pic, 14); ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], - pic_set_irq_new, NULL, 15); + pic_set_irq_new, isa_pic, 15); ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6); ide_init_ioport(&d->ide_if[2], 0x170, 0x376); } @@ -65,6 +65,33 @@ uint64_t cpu_get_tsc(CPUX86State *env) return qemu_get_clock(vm_clock); } +/* IRQ handling */ +int cpu_get_pic_interrupt(CPUState *env) +{ + int intno; + +#ifdef TARGET_X86_64 + intno = apic_get_interrupt(env); + if (intno >= 0) { + /* set irq request if a PIC irq is still pending */ + /* XXX: improve that */ + pic_update_irq(isa_pic); + return intno; + } +#endif + /* read the irq from the PIC */ + intno = pic_read_irq(isa_pic); + return intno; +} + +static void pic_irq_request(void *opaque, int level) +{ + if (level) + cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); + else + cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); +} + /* PC cmos mappings */ #define REG_EQUIPMENT_BYTE 0x14 @@ -532,7 +559,7 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device, if (pci_enabled) apic_init(cpu_single_env); - pic_init(); + isa_pic = pic_init(pic_irq_request, cpu_single_env); pit = pit_init(0x40, 0); for(i = 0; i < MAX_SERIAL_PORTS; i++) { diff --git a/hw/ppc_chrp.c b/hw/ppc_chrp.c index af57995071..cd0283c5b6 100644 --- a/hw/ppc_chrp.c +++ b/hw/ppc_chrp.c @@ -213,6 +213,11 @@ static int vga_osi_call(CPUState *env) return 1; /* osi_call handled */ } +/* XXX: suppress that */ +static void pic_irq_request(void *opaque, int level) +{ +} + /* PowerPC CHRP hardware initialisation */ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device, DisplayState *ds, const char **fd_filename, @@ -303,7 +308,7 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device, pci_set_pic(pci_bus, set_irq, pic); /* XXX: suppress that */ - pic_init(); + pic_init(pic_irq_request, NULL); /* XXX: use Mac Serial port */ serial_init(0x3f8, 4, serial_hds[0]); @@ -345,7 +350,7 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device, pci_set_pic(pci_bus, set_irq, pic); /* XXX: suppress that */ - pic_init(); + pic_init(pic_irq_request, NULL); /* XXX: use Mac Serial port */ serial_init(0x3f8, 4, serial_hds[0]); diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index 849635f6ca..b287c6f918 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -96,6 +96,14 @@ static uint32_t speaker_ioport_read(void *opaque, uint32_t addr) return 0; } +static void pic_irq_request(void *opaque, int level) +{ + if (level) + cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); + else + cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); +} + /* PCI intack register */ /* Read-only register (?) */ static void _PPC_intack_write (void *opaque, target_phys_addr_t addr, uint32_t value) @@ -108,7 +116,7 @@ static inline uint32_t _PPC_intack_read (target_phys_addr_t addr) uint32_t retval = 0; if (addr == 0xBFFFFFF0) - retval = pic_intack_read(NULL); + retval = pic_intack_read(isa_pic); // printf("%s: 0x%08x <= %d\n", __func__, addr, retval); return retval; @@ -505,8 +513,6 @@ CPUReadMemoryFunc *PPC_prep_io_read[] = { &PPC_prep_io_readl, }; -extern CPUPPCState *global_env; - #define NVRAM_SIZE 0x2000 /* PowerPC PREP hardware initialisation */ @@ -593,8 +599,7 @@ static void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, vga_ram_size); rtc_init(0x70, 8); // openpic = openpic_init(0x00000000, 0xF0000000, 1); - // pic_init(openpic); - pic_init(); + isa_pic = pic_init(pic_irq_request, cpu_single_env); // pit = pit_init(0x40, 0); serial_init(0x3f8, 4, serial_hds[0]); @@ -155,6 +155,7 @@ int win2k_install_hack = 0; /* x86 ISA bus support */ target_phys_addr_t isa_mem_base = 0; +PicState2 *isa_pic; uint32_t default_ioport_readb(void *opaque, uint32_t address) { @@ -469,6 +469,7 @@ typedef struct QEMUMachine { int qemu_register_machine(QEMUMachine *m); typedef void SetIRQFunc(void *opaque, int irq_num, int level); +typedef void IRQRequestFunc(void *opaque, int level); /* ISA bus */ @@ -687,10 +688,14 @@ ParallelState *parallel_init(int base, int irq, CharDriverState *chr); /* i8259.c */ +typedef struct PicState2 PicState2; +extern PicState2 *isa_pic; void pic_set_irq(int irq, int level); void pic_set_irq_new(void *opaque, int irq, int level); -void pic_init(void); -uint32_t pic_intack_read(CPUState *env); +PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque); +int pic_read_irq(PicState2 *s); +void pic_update_irq(PicState2 *s); +uint32_t pic_intack_read(PicState2 *s); void pic_info(void); void irq_info(void); |