diff options
| -rw-r--r-- | target-tricore/csfr.def | 2 | ||||
| -rw-r--r-- | target-tricore/translate.c | 2 | ||||
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/target-tricore/csfr.def b/target-tricore/csfr.def index 5b219b4bf1..05c45dd628 100644 --- a/target-tricore/csfr.def +++ b/target-tricore/csfr.def @@ -90,7 +90,7 @@ A(0xE200, CPM0, TRICORE_FEATURE_13) A(0xE280, CPM1, TRICORE_FEATURE_13) A(0xE300, CPM2, TRICORE_FEATURE_13) A(0xE380, CPM3, TRICORE_FEATURE_13) -/* memory Managment Registers */ +/* memory management registers */ A(0x8000, MMU_CON, TRICORE_FEATURE_13) A(0x8004, MMU_ASI, TRICORE_FEATURE_13) A(0x800C, MMU_TVA, TRICORE_FEATURE_13) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 3b83782be2..def7f4ad45 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -5022,7 +5022,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) case OPCM_32_RR_LOGICAL_SHIFT: decode_rr_logical_shift(env, ctx); break; - case OPCM_32_RR_ADRESS: + case OPCM_32_RR_ADDRESS: decode_rr_address(env, ctx); break; case OPCM_32_RR_IDIRECT: diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 919063e422..82bd161645 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -503,7 +503,7 @@ enum { /* RR Format */ OPCM_32_RR_LOGICAL_SHIFT = 0x0f, OPCM_32_RR_ACCUMULATOR = 0x0b, - OPCM_32_RR_ADRESS = 0x01, + OPCM_32_RR_ADDRESS = 0x01, OPCM_32_RR_DIVIDE = 0x4b, OPCM_32_RR_IDIRECT = 0x2d, /* RR1 Format */ @@ -1082,7 +1082,7 @@ enum { OPC2_32_RR_XOR_LT_U = 0x32, OPC2_32_RR_XOR_NE = 0x30, }; -/* OPCM_32_RR_ADRESS */ +/* OPCM_32_RR_ADDRESS */ enum { OPC2_32_RR_ADD_A = 0x01, OPC2_32_RR_ADDSC_A = 0x60, |