diff options
320 files changed, 5361 insertions, 2203 deletions
@@ -437,6 +437,61 @@ qemu-doc.dvi qemu-doc.html qemu-doc.info qemu-doc.pdf: \ qemu-img.texi qemu-nbd.texi qemu-options.texi \ qemu-monitor.texi qemu-img-cmds.texi +ifdef CONFIG_WIN32 + +INSTALLER = qemu-setup-$(VERSION)$(EXESUF) + +nsisflags = -V2 -NOCD + +ifneq ($(wildcard $(SRC_PATH)/dll),) +ifeq ($(ARCH),x86_64) +# 64 bit executables +DLL_PATH = $(SRC_PATH)/dll/w64 +nsisflags += -DW64 +else +# 32 bit executables +DLL_PATH = $(SRC_PATH)/dll/w32 +endif +endif + +.PHONY: installer +installer: $(INSTALLER) + +INSTDIR=/tmp/qemu-nsis + +$(INSTALLER): $(SRC_PATH)/qemu.nsi + make install prefix=${INSTDIR} +ifdef SIGNCODE + (cd ${INSTDIR}; \ + for i in *.exe; do \ + $(SIGNCODE) $${i}; \ + done \ + ) +endif # SIGNCODE + (cd ${INSTDIR}; \ + for i in qemu-system-*.exe; do \ + arch=$${i%.exe}; \ + arch=$${arch#qemu-system-}; \ + echo Section \"$$arch\" Section_$$arch; \ + echo SetOutPath \"\$$INSTDIR\"; \ + echo File \"\$${BINDIR}\\$$i\"; \ + echo SectionEnd; \ + done \ + ) >${INSTDIR}/system-emulations.nsh + makensis $(nsisflags) \ + $(if $(BUILD_DOCS),-DCONFIG_DOCUMENTATION="y") \ + $(if $(CONFIG_GTK),-DCONFIG_GTK="y") \ + -DBINDIR="${INSTDIR}" \ + $(if $(DLL_PATH),-DDLLDIR="$(DLL_PATH)") \ + -DSRCDIR="$(SRC_PATH)" \ + -DOUTFILE="$(INSTALLER)" \ + $(SRC_PATH)/qemu.nsi + rm -r ${INSTDIR} +ifdef SIGNCODE + $(SIGNCODE) $(INSTALLER) +endif # SIGNCODE +endif # CONFIG_WIN + # Add a dependency on the generated files, so that they are always # rebuilt before other object files ifneq ($(filter-out %clean,$(MAKECMDGOALS)),$(if $(MAKECMDGOALS),,fail)) diff --git a/block/vhdx.h b/block/vhdx.h index c3b64c6ff6..fb687ed2d6 100644 --- a/block/vhdx.h +++ b/block/vhdx.h @@ -168,7 +168,7 @@ typedef struct QEMU_PACKED VHDXLogEntryHeader { vhdx_header. If not found in vhdx_header, it is invalid */ uint64_t flushed_file_offset; /* see spec for full details - this - sould be vhdx file size in bytes */ + should be vhdx file size in bytes */ uint64_t last_file_offset; /* size in bytes that all allocated file structures fit into */ } VHDXLogEntryHeader; diff --git a/blockdev.c b/blockdev.c index 4534864802..7879e8593d 100644 --- a/blockdev.c +++ b/blockdev.c @@ -1029,7 +1029,7 @@ static void abort_prepare(BlkTransactionState *common, Error **errp) static void abort_commit(BlkTransactionState *common) { - assert(false); /* this action never succeeds */ + g_assert_not_reached(); /* this action never succeeds */ } static const BdrvActionOps actions[] = { @@ -1469,7 +1469,7 @@ libs_softmmu="$libs_softmmu -lz" # libseccomp check if test "$seccomp" != "no" ; then - if $pkg_config --atleast-version=1.0.0 libseccomp --modversion >/dev/null 2>&1; then + if $pkg_config --atleast-version=2.1.0 libseccomp --modversion >/dev/null 2>&1; then libs_softmmu="$libs_softmmu `$pkg_config --libs libseccomp`" QEMU_CFLAGS="$QEMU_CFLAGS `$pkg_config --cflags libseccomp`" seccomp="yes" @@ -3645,7 +3645,7 @@ echo "libs_softmmu=$libs_softmmu" >> $config_host_mak echo "ARCH=$ARCH" >> $config_host_mak case "$cpu" in - arm|i386|x86_64|ppc) + arm|i386|x86_64|ppc|aarch64) # The TCG interpreter currently does not support ld/st optimization. if test "$tcg_interpreter" = "no" ; then echo "CONFIG_QEMU_LDST_OPTIMIZATION=y" >> $config_host_mak @@ -4502,7 +4502,7 @@ if [ "$dtc_internal" = "yes" ]; then fi # build tree in object directory in case the source is not in the current directory -DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32 tests/libqos" +DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32 tests/libqos tests/qapi-schema" DIRS="$DIRS pc-bios/optionrom pc-bios/spapr-rtas pc-bios/s390-ccw" DIRS="$DIRS roms/seabios roms/vgabios" DIRS="$DIRS qapi-generated" @@ -112,7 +112,7 @@ typedef struct TimersState { int64_t dummy; } TimersState; -TimersState timers_state; +static TimersState timers_state; /* Return the virtual CPU time, based on the instruction counter. */ int64_t cpu_get_icount(void) diff --git a/docs/rdma.txt b/docs/rdma.txt index 45d1c8aab8..8d1e003f92 100644 --- a/docs/rdma.txt +++ b/docs/rdma.txt @@ -199,7 +199,7 @@ Version #1 requires that all server implementations of the protocol must check this field and register all requests found in the array of commands located in the data portion and return an equal number of results in the response. The maximum number of repeats is hard-coded to 4096. This is a conservative -limit based on the maximum size of a SEND message along with emperical +limit based on the maximum size of a SEND message along with empirical observations on the maximum future benefit of simultaneous page registrations. The 'type' field has 12 different command values: @@ -590,15 +590,14 @@ void cpu_breakpoint_remove_all(CPUArchState *env, int mask) void cpu_single_step(CPUState *cpu, int enabled) { #if defined(TARGET_HAS_ICE) - CPUArchState *env = cpu->env_ptr; - if (cpu->singlestep_enabled != enabled) { cpu->singlestep_enabled = enabled; if (kvm_enabled()) { - kvm_update_guest_debug(env, 0); + kvm_update_guest_debug(cpu, 0); } else { /* must flush all the translated code to avoid inconsistencies */ /* XXX: only flush what is necessary */ + CPUArchState *env = cpu->env_ptr; tb_flush(env); } } @@ -40,7 +40,6 @@ #include "cpu.h" #include "qemu/sockets.h" #include "sysemu/kvm.h" -#include "qemu/bitops.h" static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr, uint8_t *buf, int len, bool is_write) @@ -316,10 +315,7 @@ static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER; static GDBState *gdbserver_state; -/* This is an ugly hack to cope with both new and old gdb. - If gdb sends qXfer:features:read then assume we're talking to a newish - gdb that understands target descriptions. */ -static int gdb_has_xml; +bool gdb_has_xml; #ifdef CONFIG_USER_ONLY /* XXX: This is not thread safe. Do we care? */ @@ -489,1319 +485,6 @@ static int put_packet(GDBState *s, const char *buf) return put_packet_binary(s, buf, strlen(buf)); } -/* The GDB remote protocol transfers values in target byte order. This means - we can use the raw memory access routines to access the value buffer. - Conveniently, these also handle the case where the buffer is mis-aligned. - */ -#define GET_REG8(val) do { \ - stb_p(mem_buf, val); \ - return 1; \ - } while(0) -#define GET_REG16(val) do { \ - stw_p(mem_buf, val); \ - return 2; \ - } while(0) -#define GET_REG32(val) do { \ - stl_p(mem_buf, val); \ - return 4; \ - } while(0) -#define GET_REG64(val) do { \ - stq_p(mem_buf, val); \ - return 8; \ - } while(0) - -#if TARGET_LONG_BITS == 64 -#define GET_REGL(val) GET_REG64(val) -#define ldtul_p(addr) ldq_p(addr) -#else -#define GET_REGL(val) GET_REG32(val) -#define ldtul_p(addr) ldl_p(addr) -#endif - -#if defined(TARGET_I386) - -#ifdef TARGET_X86_64 -static const int gpr_map[16] = { - R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP, - 8, 9, 10, 11, 12, 13, 14, 15 -}; -#else -#define gpr_map gpr_map32 -#endif -static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; - -#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25) - -#define IDX_IP_REG CPU_NB_REGS -#define IDX_FLAGS_REG (IDX_IP_REG + 1) -#define IDX_SEG_REGS (IDX_FLAGS_REG + 1) -#define IDX_FP_REGS (IDX_SEG_REGS + 6) -#define IDX_XMM_REGS (IDX_FP_REGS + 16) -#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS) - -static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n) -{ - if (n < CPU_NB_REGS) { - if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { - GET_REG64(env->regs[gpr_map[n]]); - } else if (n < CPU_NB_REGS32) { - GET_REG32(env->regs[gpr_map32[n]]); - } - } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) { -#ifdef USE_X86LDOUBLE - /* FIXME: byteswap float values - after fixing fpregs layout. */ - memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10); -#else - memset(mem_buf, 0, 10); -#endif - return 10; - } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { - n -= IDX_XMM_REGS; - if (n < CPU_NB_REGS32 || - (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) { - stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0)); - stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1)); - return 16; - } - } else { - switch (n) { - case IDX_IP_REG: - if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { - GET_REG64(env->eip); - } else { - GET_REG32(env->eip); - } - case IDX_FLAGS_REG: GET_REG32(env->eflags); - - case IDX_SEG_REGS: GET_REG32(env->segs[R_CS].selector); - case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector); - case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector); - case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector); - case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector); - case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector); - - case IDX_FP_REGS + 8: GET_REG32(env->fpuc); - case IDX_FP_REGS + 9: GET_REG32((env->fpus & ~0x3800) | - (env->fpstt & 0x7) << 11); - case IDX_FP_REGS + 10: GET_REG32(0); /* ftag */ - case IDX_FP_REGS + 11: GET_REG32(0); /* fiseg */ - case IDX_FP_REGS + 12: GET_REG32(0); /* fioff */ - case IDX_FP_REGS + 13: GET_REG32(0); /* foseg */ - case IDX_FP_REGS + 14: GET_REG32(0); /* fooff */ - case IDX_FP_REGS + 15: GET_REG32(0); /* fop */ - - case IDX_MXCSR_REG: GET_REG32(env->mxcsr); - } - } - return 0; -} - -static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf) -{ - uint16_t selector = ldl_p(mem_buf); - - if (selector != env->segs[sreg].selector) { -#if defined(CONFIG_USER_ONLY) - cpu_x86_load_seg(env, sreg, selector); -#else - unsigned int limit, flags; - target_ulong base; - - if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { - base = selector << 4; - limit = 0xffff; - flags = 0; - } else { - if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags)) - return 4; - } - cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags); -#endif - } - return 4; -} - -static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n) -{ - uint32_t tmp; - - if (n < CPU_NB_REGS) { - if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { - env->regs[gpr_map[n]] = ldtul_p(mem_buf); - return sizeof(target_ulong); - } else if (n < CPU_NB_REGS32) { - n = gpr_map32[n]; - env->regs[n] &= ~0xffffffffUL; - env->regs[n] |= (uint32_t)ldl_p(mem_buf); - return 4; - } - } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) { -#ifdef USE_X86LDOUBLE - /* FIXME: byteswap float values - after fixing fpregs layout. */ - memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10); -#endif - return 10; - } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { - n -= IDX_XMM_REGS; - if (n < CPU_NB_REGS32 || - (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) { - env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf); - env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8); - return 16; - } - } else { - switch (n) { - case IDX_IP_REG: - if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { - env->eip = ldq_p(mem_buf); - return 8; - } else { - env->eip &= ~0xffffffffUL; - env->eip |= (uint32_t)ldl_p(mem_buf); - return 4; - } - case IDX_FLAGS_REG: - env->eflags = ldl_p(mem_buf); - return 4; - - case IDX_SEG_REGS: return cpu_x86_gdb_load_seg(env, R_CS, mem_buf); - case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf); - case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf); - case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf); - case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf); - case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf); - - case IDX_FP_REGS + 8: - env->fpuc = ldl_p(mem_buf); - return 4; - case IDX_FP_REGS + 9: - tmp = ldl_p(mem_buf); - env->fpstt = (tmp >> 11) & 7; - env->fpus = tmp & ~0x3800; - return 4; - case IDX_FP_REGS + 10: /* ftag */ return 4; - case IDX_FP_REGS + 11: /* fiseg */ return 4; - case IDX_FP_REGS + 12: /* fioff */ return 4; - case IDX_FP_REGS + 13: /* foseg */ return 4; - case IDX_FP_REGS + 14: /* fooff */ return 4; - case IDX_FP_REGS + 15: /* fop */ return 4; - - case IDX_MXCSR_REG: - env->mxcsr = ldl_p(mem_buf); - return 4; - } - } - /* Unrecognised register. */ - return 0; -} - -#elif defined (TARGET_PPC) - -/* Old gdb always expects FP registers. Newer (xml-aware) gdb only - expects whatever the target description contains. Due to a - historical mishap the FP registers appear in between core integer - regs and PC, MSR, CR, and so forth. We hack round this by giving the - FP regs zero size when talking to a newer gdb. */ -#define NUM_CORE_REGS 71 -#if defined (TARGET_PPC64) -#define GDB_CORE_XML "power64-core.xml" -#else -#define GDB_CORE_XML "power-core.xml" -#endif - -static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n) -{ - if (n < 32) { - /* gprs */ - GET_REGL(env->gpr[n]); - } else if (n < 64) { - /* fprs */ - if (gdb_has_xml) - return 0; - stfq_p(mem_buf, env->fpr[n-32]); - return 8; - } else { - switch (n) { - case 64: GET_REGL(env->nip); - case 65: GET_REGL(env->msr); - case 66: - { - uint32_t cr = 0; - int i; - for (i = 0; i < 8; i++) - cr |= env->crf[i] << (32 - ((i + 1) * 4)); - GET_REG32(cr); - } - case 67: GET_REGL(env->lr); - case 68: GET_REGL(env->ctr); - case 69: GET_REGL(env->xer); - case 70: - { - if (gdb_has_xml) - return 0; - GET_REG32(env->fpscr); - } - } - } - return 0; -} - -static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n) -{ - if (n < 32) { - /* gprs */ - env->gpr[n] = ldtul_p(mem_buf); - return sizeof(target_ulong); - } else if (n < 64) { - /* fprs */ - if (gdb_has_xml) - return 0; - env->fpr[n-32] = ldfq_p(mem_buf); - return 8; - } else { - switch (n) { - case 64: - env->nip = ldtul_p(mem_buf); - return sizeof(target_ulong); - case 65: - ppc_store_msr(env, ldtul_p(mem_buf)); - return sizeof(target_ulong); - case 66: - { - uint32_t cr = ldl_p(mem_buf); - int i; - for (i = 0; i < 8; i++) - env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF; - return 4; - } - case 67: - env->lr = ldtul_p(mem_buf); - return sizeof(target_ulong); - case 68: - env->ctr = ldtul_p(mem_buf); - return sizeof(target_ulong); - case 69: - env->xer = ldtul_p(mem_buf); - return sizeof(target_ulong); - case 70: - /* fpscr */ - if (gdb_has_xml) - return 0; - store_fpscr(env, ldtul_p(mem_buf), 0xffffffff); - return sizeof(target_ulong); - } - } - return 0; -} - -#elif defined (TARGET_SPARC) - -#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) -#define NUM_CORE_REGS 86 -#else -#define NUM_CORE_REGS 72 -#endif - -#ifdef TARGET_ABI32 -#define GET_REGA(val) GET_REG32(val) -#else -#define GET_REGA(val) GET_REGL(val) -#endif - -static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n) -{ - if (n < 8) { - /* g0..g7 */ - GET_REGA(env->gregs[n]); - } - if (n < 32) { - /* register window */ - GET_REGA(env->regwptr[n - 8]); - } -#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) - if (n < 64) { - /* fprs */ - if (n & 1) { - GET_REG32(env->fpr[(n - 32) / 2].l.lower); - } else { - GET_REG32(env->fpr[(n - 32) / 2].l.upper); - } - } - /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */ - switch (n) { - case 64: GET_REGA(env->y); - case 65: GET_REGA(cpu_get_psr(env)); - case 66: GET_REGA(env->wim); - case 67: GET_REGA(env->tbr); - case 68: GET_REGA(env->pc); - case 69: GET_REGA(env->npc); - case 70: GET_REGA(env->fsr); - case 71: GET_REGA(0); /* csr */ - default: GET_REGA(0); - } -#else - if (n < 64) { - /* f0-f31 */ - if (n & 1) { - GET_REG32(env->fpr[(n - 32) / 2].l.lower); - } else { - GET_REG32(env->fpr[(n - 32) / 2].l.upper); - } - } - if (n < 80) { - /* f32-f62 (double width, even numbers only) */ - GET_REG64(env->fpr[(n - 32) / 2].ll); - } - switch (n) { - case 80: GET_REGL(env->pc); - case 81: GET_REGL(env->npc); - case 82: GET_REGL((cpu_get_ccr(env) << 32) | - ((env->asi & 0xff) << 24) | - ((env->pstate & 0xfff) << 8) | - cpu_get_cwp64(env)); - case 83: GET_REGL(env->fsr); - case 84: GET_REGL(env->fprs); - case 85: GET_REGL(env->y); - } -#endif - return 0; -} - -static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n) -{ -#if defined(TARGET_ABI32) - abi_ulong tmp; - - tmp = ldl_p(mem_buf); -#else - target_ulong tmp; - - tmp = ldtul_p(mem_buf); -#endif - - if (n < 8) { - /* g0..g7 */ - env->gregs[n] = tmp; - } else if (n < 32) { - /* register window */ - env->regwptr[n - 8] = tmp; - } -#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) - else if (n < 64) { - /* fprs */ - /* f0-f31 */ - if (n & 1) { - env->fpr[(n - 32) / 2].l.lower = tmp; - } else { - env->fpr[(n - 32) / 2].l.upper = tmp; - } - } else { - /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */ - switch (n) { - case 64: env->y = tmp; break; - case 65: cpu_put_psr(env, tmp); break; - case 66: env->wim = tmp; break; - case 67: env->tbr = tmp; break; - case 68: env->pc = tmp; break; - case 69: env->npc = tmp; break; - case 70: env->fsr = tmp; break; - default: return 0; - } - } - return 4; -#else - else if (n < 64) { - /* f0-f31 */ - tmp = ldl_p(mem_buf); - if (n & 1) { - env->fpr[(n - 32) / 2].l.lower = tmp; - } else { - env->fpr[(n - 32) / 2].l.upper = tmp; - } - return 4; - } else if (n < 80) { - /* f32-f62 (double width, even numbers only) */ - env->fpr[(n - 32) / 2].ll = tmp; - } else { - switch (n) { - case 80: env->pc = tmp; break; - case 81: env->npc = tmp; break; - case 82: - cpu_put_ccr(env, tmp >> 32); - env->asi = (tmp >> 24) & 0xff; - env->pstate = (tmp >> 8) & 0xfff; - cpu_put_cwp64(env, tmp & 0xff); - break; - case 83: env->fsr = tmp; break; - case 84: env->fprs = tmp; break; - case 85: env->y = tmp; break; - default: return 0; - } - } - return 8; -#endif -} -#elif defined (TARGET_ARM) - -/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect - whatever the target description contains. Due to a historical mishap - the FPA registers appear in between core integer regs and the CPSR. - We hack round this by giving the FPA regs zero size when talking to a - newer gdb. */ -#define NUM_CORE_REGS 26 -#define GDB_CORE_XML "arm-core.xml" - -static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n) -{ - if (n < 16) { - /* Core integer register. */ - GET_REG32(env->regs[n]); - } - if (n < 24) { - /* FPA registers. */ - if (gdb_has_xml) - return 0; - memset(mem_buf, 0, 12); - return 12; - } - switch (n) { - case 24: - /* FPA status register. */ - if (gdb_has_xml) - return 0; - GET_REG32(0); - case 25: - /* CPSR */ - GET_REG32(cpsr_read(env)); - } - /* Unknown register. */ - return 0; -} - -static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n) -{ - uint32_t tmp; - - tmp = ldl_p(mem_buf); - - /* Mask out low bit of PC to workaround gdb bugs. This will probably - cause problems if we ever implement the Jazelle DBX extensions. */ - if (n == 15) - tmp &= ~1; - - if (n < 16) { - /* Core integer register. */ - env->regs[n] = tmp; - return 4; - } - if (n < 24) { /* 16-23 */ - /* FPA registers (ignored). */ - if (gdb_has_xml) - return 0; - return 12; - } - switch (n) { - case 24: - /* FPA status register (ignored). */ - if (gdb_has_xml) - return 0; - return 4; - case 25: - /* CPSR */ - cpsr_write (env, tmp, 0xffffffff); - return 4; - } - /* Unknown register. */ - return 0; -} - -#elif defined (TARGET_M68K) - -#define NUM_CORE_REGS 18 - -#define GDB_CORE_XML "cf-core.xml" - -static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n) -{ - if (n < 8) { - /* D0-D7 */ - GET_REG32(env->dregs[n]); - } else if (n < 16) { - /* A0-A7 */ - GET_REG32(env->aregs[n - 8]); - } else { - switch (n) { - case 16: GET_REG32(env->sr); - case 17: GET_REG32(env->pc); - } - } - /* FP registers not included here because they vary between - ColdFire and m68k. Use XML bits for these. */ - return 0; -} - -static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n) -{ - uint32_t tmp; - - tmp = ldl_p(mem_buf); - - if (n < 8) { - /* D0-D7 */ - env->dregs[n] = tmp; - } else if (n < 16) { - /* A0-A7 */ - env->aregs[n - 8] = tmp; - } else { - switch (n) { - case 16: env->sr = tmp; break; - case 17: env->pc = tmp; break; - default: return 0; - } - } - return 4; -} -#elif defined (TARGET_MIPS) - -#define NUM_CORE_REGS 73 - -static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n) -{ - if (n < 32) { - GET_REGL(env->active_tc.gpr[n]); - } - if (env->CP0_Config1 & (1 << CP0C1_FP)) { - if (n >= 38 && n < 70) { - if (env->CP0_Status & (1 << CP0St_FR)) - GET_REGL(env->active_fpu.fpr[n - 38].d); - else - GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); - } - switch (n) { - case 70: GET_REGL((int32_t)env->active_fpu.fcr31); - case 71: GET_REGL((int32_t)env->active_fpu.fcr0); - } - } - switch (n) { - case 32: GET_REGL((int32_t)env->CP0_Status); - case 33: GET_REGL(env->active_tc.LO[0]); - case 34: GET_REGL(env->active_tc.HI[0]); - case 35: GET_REGL(env->CP0_BadVAddr); - case 36: GET_REGL((int32_t)env->CP0_Cause); - case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16)); - case 72: GET_REGL(0); /* fp */ - case 89: GET_REGL((int32_t)env->CP0_PRid); - } - if (n >= 73 && n <= 88) { - /* 16 embedded regs. */ - GET_REGL(0); - } - - return 0; -} - -/* convert MIPS rounding mode in FCR31 to IEEE library */ -static unsigned int ieee_rm[] = - { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down - }; -#define RESTORE_ROUNDING_MODE \ - set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status) - -static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n) -{ - target_ulong tmp; - - tmp = ldtul_p(mem_buf); - - if (n < 32) { - env->active_tc.gpr[n] = tmp; - return sizeof(target_ulong); - } - if (env->CP0_Config1 & (1 << CP0C1_FP) - && n >= 38 && n < 73) { - if (n < 70) { - if (env->CP0_Status & (1 << CP0St_FR)) - env->active_fpu.fpr[n - 38].d = tmp; - else - env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; - } - switch (n) { - case 70: - env->active_fpu.fcr31 = tmp & 0xFF83FFFF; - /* set rounding mode */ - RESTORE_ROUNDING_MODE; - break; - case 71: env->active_fpu.fcr0 = tmp; break; - } - return sizeof(target_ulong); - } - switch (n) { - case 32: env->CP0_Status = tmp; break; - case 33: env->active_tc.LO[0] = tmp; break; - case 34: env->active_tc.HI[0] = tmp; break; - case 35: env->CP0_BadVAddr = tmp; break; - case 36: env->CP0_Cause = tmp; break; - case 37: - env->active_tc.PC = tmp & ~(target_ulong)1; - if (tmp & 1) { - env->hflags |= MIPS_HFLAG_M16; - } else { - env->hflags &= ~(MIPS_HFLAG_M16); - } - break; - case 72: /* fp, ignored */ break; - default: - if (n > 89) - return 0; - /* Other registers are readonly. Ignore writes. */ - break; - } - - return sizeof(target_ulong); -} -#elif defined(TARGET_OPENRISC) - -#define NUM_CORE_REGS (32 + 3) - -static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n) -{ - if (n < 32) { - GET_REG32(env->gpr[n]); - } else { - switch (n) { - case 32: /* PPC */ - GET_REG32(env->ppc); - break; - - case 33: /* NPC */ - GET_REG32(env->npc); - break; - - case 34: /* SR */ - GET_REG32(env->sr); - break; - - default: - break; - } - } - return 0; -} - -static int cpu_gdb_write_register(CPUOpenRISCState *env, - uint8_t *mem_buf, int n) -{ - uint32_t tmp; - - if (n > NUM_CORE_REGS) { - return 0; - } - - tmp = ldl_p(mem_buf); - - if (n < 32) { - env->gpr[n] = tmp; - } else { - switch (n) { - case 32: /* PPC */ - env->ppc = tmp; - break; - - case 33: /* NPC */ - env->npc = tmp; - break; - - case 34: /* SR */ - env->sr = tmp; - break; - - default: - break; - } - } - return 4; -} -#elif defined (TARGET_SH4) - -/* Hint: Use "set architecture sh4" in GDB to see fpu registers */ -/* FIXME: We should use XML for this. */ - -#define NUM_CORE_REGS 59 - -static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n) -{ - switch (n) { - case 0 ... 7: - if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) { - GET_REGL(env->gregs[n + 16]); - } else { - GET_REGL(env->gregs[n]); - } - case 8 ... 15: - GET_REGL(env->gregs[n]); - case 16: - GET_REGL(env->pc); - case 17: - GET_REGL(env->pr); - case 18: - GET_REGL(env->gbr); - case 19: - GET_REGL(env->vbr); - case 20: - GET_REGL(env->mach); - case 21: - GET_REGL(env->macl); - case 22: - GET_REGL(env->sr); - case 23: - GET_REGL(env->fpul); - case 24: - GET_REGL(env->fpscr); - case 25 ... 40: - if (env->fpscr & FPSCR_FR) { - stfl_p(mem_buf, env->fregs[n - 9]); - } else { - stfl_p(mem_buf, env->fregs[n - 25]); - } - return 4; - case 41: - GET_REGL(env->ssr); - case 42: - GET_REGL(env->spc); - case 43 ... 50: - GET_REGL(env->gregs[n - 43]); - case 51 ... 58: - GET_REGL(env->gregs[n - (51 - 16)]); - } - - return 0; -} - -static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n) -{ - switch (n) { - case 0 ... 7: - if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) { - env->gregs[n + 16] = ldl_p(mem_buf); - } else { - env->gregs[n] = ldl_p(mem_buf); - } - break; - case 8 ... 15: - env->gregs[n] = ldl_p(mem_buf); - break; - case 16: - env->pc = ldl_p(mem_buf); - break; - case 17: - env->pr = ldl_p(mem_buf); - break; - case 18: - env->gbr = ldl_p(mem_buf); - break; - case 19: - env->vbr = ldl_p(mem_buf); - break; - case 20: - env->mach = ldl_p(mem_buf); - break; - case 21: - env->macl = ldl_p(mem_buf); - break; - case 22: - env->sr = ldl_p(mem_buf); - break; - case 23: - env->fpul = ldl_p(mem_buf); - break; - case 24: - env->fpscr = ldl_p(mem_buf); - break; - case 25 ... 40: - if (env->fpscr & FPSCR_FR) { - env->fregs[n - 9] = ldfl_p(mem_buf); - } else { - env->fregs[n - 25] = ldfl_p(mem_buf); - } - break; - case 41: - env->ssr = ldl_p(mem_buf); - break; - case 42: - env->spc = ldl_p(mem_buf); - break; - case 43 ... 50: - env->gregs[n - 43] = ldl_p(mem_buf); - break; - case 51 ... 58: - env->gregs[n - (51 - 16)] = ldl_p(mem_buf); - break; - default: return 0; - } - - return 4; -} -#elif defined (TARGET_MICROBLAZE) - -#define NUM_CORE_REGS (32 + 5) - -static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n) -{ - if (n < 32) { - GET_REG32(env->regs[n]); - } else { - GET_REG32(env->sregs[n - 32]); - } - return 0; -} - -static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n) -{ - uint32_t tmp; - - if (n > NUM_CORE_REGS) - return 0; - - tmp = ldl_p(mem_buf); - - if (n < 32) { - env->regs[n] = tmp; - } else { - env->sregs[n - 32] = tmp; - } - return 4; -} -#elif defined (TARGET_CRIS) - -#define NUM_CORE_REGS 49 - -static int -read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n) -{ - if (n < 15) { - GET_REG32(env->regs[n]); - } - - if (n == 15) { - GET_REG32(env->pc); - } - - if (n < 32) { - switch (n) { - case 16: - GET_REG8(env->pregs[n - 16]); - break; - case 17: - GET_REG8(env->pregs[n - 16]); - break; - case 20: - case 21: - GET_REG16(env->pregs[n - 16]); - break; - default: - if (n >= 23) { - GET_REG32(env->pregs[n - 16]); - } - break; - } - } - return 0; -} - -static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n) -{ - uint8_t srs; - - if (env->pregs[PR_VR] < 32) - return read_register_crisv10(env, mem_buf, n); - - srs = env->pregs[PR_SRS]; - if (n < 16) { - GET_REG32(env->regs[n]); - } - - if (n >= 21 && n < 32) { - GET_REG32(env->pregs[n - 16]); - } - if (n >= 33 && n < 49) { - GET_REG32(env->sregs[srs][n - 33]); - } - switch (n) { - case 16: GET_REG8(env->pregs[0]); - case 17: GET_REG8(env->pregs[1]); - case 18: GET_REG32(env->pregs[2]); - case 19: GET_REG8(srs); - case 20: GET_REG16(env->pregs[4]); - case 32: GET_REG32(env->pc); - } - - return 0; -} - -static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n) -{ - uint32_t tmp; - - if (n > 49) - return 0; - - tmp = ldl_p(mem_buf); - - if (n < 16) { - env->regs[n] = tmp; - } - - if (n >= 21 && n < 32) { - env->pregs[n - 16] = tmp; - } - - /* FIXME: Should support function regs be writable? */ - switch (n) { - case 16: return 1; - case 17: return 1; - case 18: env->pregs[PR_PID] = tmp; break; - case 19: return 1; - case 20: return 2; - case 32: env->pc = tmp; break; - } - - return 4; -} -#elif defined (TARGET_ALPHA) - -#define NUM_CORE_REGS 67 - -static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n) -{ - uint64_t val; - CPU_DoubleU d; - - switch (n) { - case 0 ... 30: - val = env->ir[n]; - break; - case 32 ... 62: - d.d = env->fir[n - 32]; - val = d.ll; - break; - case 63: - val = cpu_alpha_load_fpcr(env); - break; - case 64: - val = env->pc; - break; - case 66: - val = env->unique; - break; - case 31: - case 65: - /* 31 really is the zero register; 65 is unassigned in the - gdb protocol, but is still required to occupy 8 bytes. */ - val = 0; - break; - default: - return 0; - } - GET_REGL(val); -} - -static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n) -{ - target_ulong tmp = ldtul_p(mem_buf); - CPU_DoubleU d; - - switch (n) { - case 0 ... 30: - env->ir[n] = tmp; - break; - case 32 ... 62: - d.ll = tmp; - env->fir[n - 32] = d.d; - break; - case 63: - cpu_alpha_store_fpcr(env, tmp); - break; - case 64: - env->pc = tmp; - break; - case 66: - env->unique = tmp; - break; - case 31: - case 65: - /* 31 really is the zero register; 65 is unassigned in the - gdb protocol, but is still required to occupy 8 bytes. */ - break; - default: - return 0; - } - return 8; -} -#elif defined (TARGET_S390X) - -#define NUM_CORE_REGS S390_NUM_REGS - -static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n) -{ - uint64_t val; - int cc_op; - - switch (n) { - case S390_PSWM_REGNUM: - cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr); - val = deposit64(env->psw.mask, 44, 2, cc_op); - GET_REGL(val); - break; - case S390_PSWA_REGNUM: - GET_REGL(env->psw.addr); - break; - case S390_R0_REGNUM ... S390_R15_REGNUM: - GET_REGL(env->regs[n-S390_R0_REGNUM]); - break; - case S390_A0_REGNUM ... S390_A15_REGNUM: - GET_REG32(env->aregs[n-S390_A0_REGNUM]); - break; - case S390_FPC_REGNUM: - GET_REG32(env->fpc); - break; - case S390_F0_REGNUM ... S390_F15_REGNUM: - GET_REG64(env->fregs[n-S390_F0_REGNUM].ll); - break; - } - - return 0; -} - -static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n) -{ - target_ulong tmpl; - uint32_t tmp32; - int r = 8; - tmpl = ldtul_p(mem_buf); - tmp32 = ldl_p(mem_buf); - - switch (n) { - case S390_PSWM_REGNUM: - env->psw.mask = tmpl; - env->cc_op = extract64(tmpl, 44, 2); - break; - case S390_PSWA_REGNUM: - env->psw.addr = tmpl; - break; - case S390_R0_REGNUM ... S390_R15_REGNUM: - env->regs[n-S390_R0_REGNUM] = tmpl; - break; - case S390_A0_REGNUM ... S390_A15_REGNUM: - env->aregs[n-S390_A0_REGNUM] = tmp32; - r = 4; - break; - case S390_FPC_REGNUM: - env->fpc = tmp32; - r = 4; - break; - case S390_F0_REGNUM ... S390_F15_REGNUM: - env->fregs[n-S390_F0_REGNUM].ll = tmpl; - break; - default: - return 0; - } - return r; -} -#elif defined (TARGET_LM32) - -#include "hw/lm32/lm32_pic.h" -#define NUM_CORE_REGS (32 + 7) - -static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n) -{ - if (n < 32) { - GET_REG32(env->regs[n]); - } else { - switch (n) { - case 32: - GET_REG32(env->pc); - break; - /* FIXME: put in right exception ID */ - case 33: - GET_REG32(0); - break; - case 34: - GET_REG32(env->eba); - break; - case 35: - GET_REG32(env->deba); - break; - case 36: - GET_REG32(env->ie); - break; - case 37: - GET_REG32(lm32_pic_get_im(env->pic_state)); - break; - case 38: - GET_REG32(lm32_pic_get_ip(env->pic_state)); - break; - } - } - return 0; -} - -static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n) -{ - uint32_t tmp; - - if (n > NUM_CORE_REGS) { - return 0; - } - - tmp = ldl_p(mem_buf); - - if (n < 32) { - env->regs[n] = tmp; - } else { - switch (n) { - case 32: - env->pc = tmp; - break; - case 34: - env->eba = tmp; - break; - case 35: - env->deba = tmp; - break; - case 36: - env->ie = tmp; - break; - case 37: - lm32_pic_set_im(env->pic_state, tmp); - break; - case 38: - lm32_pic_set_ip(env->pic_state, tmp); - break; - } - } - return 4; -} -#elif defined(TARGET_XTENSA) - -/* Use num_core_regs to see only non-privileged registers in an unmodified gdb. - * Use num_regs to see all registers. gdb modification is required for that: - * reset bit 0 in the 'flags' field of the registers definitions in the - * gdb/xtensa-config.c inside gdb source tree or inside gdb overlay. - */ -#define NUM_CORE_REGS (env->config->gdb_regmap.num_regs) -#define num_g_regs NUM_CORE_REGS - -static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n) -{ - const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; - - if (n < 0 || n >= env->config->gdb_regmap.num_regs) { - return 0; - } - - switch (reg->type) { - case 9: /*pc*/ - GET_REG32(env->pc); - break; - - case 1: /*ar*/ - xtensa_sync_phys_from_window(env); - GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]); - break; - - case 2: /*SR*/ - GET_REG32(env->sregs[reg->targno & 0xff]); - break; - - case 3: /*UR*/ - GET_REG32(env->uregs[reg->targno & 0xff]); - break; - - case 4: /*f*/ - GET_REG32(float32_val(env->fregs[reg->targno & 0x0f])); - break; - - case 8: /*a*/ - GET_REG32(env->regs[reg->targno & 0x0f]); - break; - - default: - qemu_log("%s from reg %d of unsupported type %d\n", - __func__, n, reg->type); - return 0; - } -} - -static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n) -{ - uint32_t tmp; - const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; - - if (n < 0 || n >= env->config->gdb_regmap.num_regs) { - return 0; - } - - tmp = ldl_p(mem_buf); - - switch (reg->type) { - case 9: /*pc*/ - env->pc = tmp; - break; - - case 1: /*ar*/ - env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp; - xtensa_sync_window_from_phys(env); - break; - - case 2: /*SR*/ - env->sregs[reg->targno & 0xff] = tmp; - break; - - case 3: /*UR*/ - env->uregs[reg->targno & 0xff] = tmp; - break; - - case 4: /*f*/ - env->fregs[reg->targno & 0x0f] = make_float32(tmp); - break; - - case 8: /*a*/ - env->regs[reg->targno & 0x0f] = tmp; - break; - - default: - qemu_log("%s to reg %d of unsupported type %d\n", - __func__, n, reg->type); - return 0; - } - - return 4; -} -#else - -#define NUM_CORE_REGS 0 - -static int cpu_gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int n) -{ - return 0; -} - -static int cpu_gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int n) -{ - return 0; -} - -#endif - -#if !defined(TARGET_XTENSA) -static int num_g_regs = NUM_CORE_REGS; -#endif - -#ifdef GDB_CORE_XML /* Encode data using the encoding for 'x' packets. */ static int memtox(char *buf, const char *mem, int len) { @@ -1823,7 +506,8 @@ static int memtox(char *buf, const char *mem, int len) return p - buf; } -static const char *get_feature_xml(const char *p, const char **newp) +static const char *get_feature_xml(const char *p, const char **newp, + CPUClass *cc) { size_t len; int i; @@ -1847,7 +531,7 @@ static const char *get_feature_xml(const char *p, const char **newp) "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">" "<target>" "<xi:include href=\"%s\"/>", - GDB_CORE_XML); + cc->gdb_core_xml_file); for (r = cpu->gdb_regs; r; r = r->next) { pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\""); @@ -1865,15 +549,16 @@ static const char *get_feature_xml(const char *p, const char **newp) } return name ? xml_builtin[i][1] : NULL; } -#endif static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg) { + CPUClass *cc = CPU_GET_CLASS(cpu); CPUArchState *env = cpu->env_ptr; GDBRegisterState *r; - if (reg < NUM_CORE_REGS) - return cpu_gdb_read_register(env, mem_buf, reg); + if (reg < cc->gdb_num_core_regs) { + return cc->gdb_read_register(cpu, mem_buf, reg); + } for (r = cpu->gdb_regs; r; r = r->next) { if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) { @@ -1885,11 +570,13 @@ static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg) static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) { + CPUClass *cc = CPU_GET_CLASS(cpu); CPUArchState *env = cpu->env_ptr; GDBRegisterState *r; - if (reg < NUM_CORE_REGS) - return cpu_gdb_write_register(env, mem_buf, reg); + if (reg < cc->gdb_num_core_regs) { + return cc->gdb_write_register(cpu, mem_buf, reg); + } for (r = cpu->gdb_regs; r; r = r->next) { if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) { @@ -1899,7 +586,6 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) return 0; } -#if !defined(TARGET_XTENSA) /* Register a supplemental set of CPU registers. If g_pos is nonzero it specifies the first register number and these registers are included in a standard "g" packet. Direction is relative to gdb, i.e. get_reg is @@ -1912,7 +598,6 @@ void gdb_register_coprocessor(CPUState *cpu, { GDBRegisterState *s; GDBRegisterState **p; - static int last_reg = NUM_CORE_REGS; p = &cpu->gdb_regs; while (*p) { @@ -1923,25 +608,22 @@ void gdb_register_coprocessor(CPUState *cpu, } s = g_new0(GDBRegisterState, 1); - s->base_reg = last_reg; + s->base_reg = cpu->gdb_num_regs; s->num_regs = num_regs; s->get_reg = get_reg; s->set_reg = set_reg; s->xml = xml; /* Add to end of list. */ - last_reg += num_regs; + cpu->gdb_num_regs += num_regs; *p = s; if (g_pos) { if (g_pos != s->base_reg) { fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n" "Expected %d got %d\n", xml, g_pos, s->base_reg); - } else { - num_g_regs = last_reg; } } } -#endif #ifndef CONFIG_USER_ONLY static const int xlat_gdb_type[] = { @@ -2071,10 +753,8 @@ static CPUState *find_cpu(uint32_t thread_id) static int gdb_handle_packet(GDBState *s, const char *line_buf) { -#ifdef TARGET_XTENSA - CPUArchState *env; -#endif CPUState *cpu; + CPUClass *cc; const char *p; uint32_t thread; int ch, reg_size, type, res; @@ -2221,11 +901,8 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) break; case 'g': cpu_synchronize_state(s->g_cpu); -#ifdef TARGET_XTENSA - env = s->g_cpu->env_ptr; -#endif len = 0; - for (addr = 0; addr < num_g_regs; addr++) { + for (addr = 0; addr < s->g_cpu->gdb_num_regs; addr++) { reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr); len += reg_size; } @@ -2234,13 +911,10 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) break; case 'G': cpu_synchronize_state(s->g_cpu); -#ifdef TARGET_XTENSA - env = s->g_cpu->env_ptr; -#endif registers = mem_buf; len = strlen(p) / 2; hextomem((uint8_t *)registers, p, len); - for (addr = 0; addr < num_g_regs && len > 0; addr++) { + for (addr = 0; addr < s->g_cpu->gdb_num_regs && len > 0; addr++) { reg_size = gdb_write_register(s->g_cpu, registers, addr); len -= reg_size; registers += reg_size; @@ -2443,20 +1117,25 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) #endif /* !CONFIG_USER_ONLY */ if (strncmp(p, "Supported", 9) == 0) { snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH); -#ifdef GDB_CORE_XML - pstrcat(buf, sizeof(buf), ";qXfer:features:read+"); -#endif + cc = CPU_GET_CLASS(first_cpu); + if (cc->gdb_core_xml_file != NULL) { + pstrcat(buf, sizeof(buf), ";qXfer:features:read+"); + } put_packet(s, buf); break; } -#ifdef GDB_CORE_XML if (strncmp(p, "Xfer:features:read:", 19) == 0) { const char *xml; target_ulong total_len; - gdb_has_xml = 1; + cc = CPU_GET_CLASS(first_cpu); + if (cc->gdb_core_xml_file == NULL) { + goto unknown_command; + } + + gdb_has_xml = true; p += 19; - xml = get_feature_xml(p, &p); + xml = get_feature_xml(p, &p, cc); if (!xml) { snprintf(buf, sizeof(buf), "E00"); put_packet(s, buf); @@ -2488,7 +1167,6 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) put_packet_binary(s, buf, len + 1); break; } -#endif /* Unrecognised 'q' command. */ goto unknown_command; @@ -2863,7 +1541,7 @@ static void gdb_accept(void) s->c_cpu = first_cpu; s->g_cpu = first_cpu; s->fd = fd; - gdb_has_xml = 0; + gdb_has_xml = false; gdbserver_state = s; @@ -2949,7 +1627,7 @@ static void gdb_chr_event(void *opaque, int event) switch (event) { case CHR_EVENT_OPENED: vm_stop(RUN_STATE_PAUSED); - gdb_has_xml = 0; + gdb_has_xml = false; break; default: break; diff --git a/hw/9pfs/virtio-9p-device.c b/hw/9pfs/virtio-9p-device.c index 35e2af47b2..de6f0fe290 100644 --- a/hw/9pfs/virtio-9p-device.c +++ b/hw/9pfs/virtio-9p-device.c @@ -149,6 +149,7 @@ static void virtio_9p_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); dc->props = virtio_9p_properties; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); vdc->init = virtio_9p_device_init; vdc->get_features = virtio_9p_get_features; vdc->get_config = virtio_9p_get_config; diff --git a/hw/9pfs/virtio-9p-proxy.c b/hw/9pfs/virtio-9p-proxy.c index 8ba2959dbb..5f44bb758b 100644 --- a/hw/9pfs/virtio-9p-proxy.c +++ b/hw/9pfs/virtio-9p-proxy.c @@ -1153,10 +1153,12 @@ static int proxy_init(FsContext *ctx) sock_id = atoi(ctx->fs_root); if (sock_id < 0) { fprintf(stderr, "socket descriptor not initialized\n"); + g_free(proxy); return -1; } } g_free(ctx->fs_root); + ctx->fs_root = NULL; proxy->in_iovec.iov_base = g_malloc(PROXY_MAX_IO_SZ + PROXY_HDR_SZ); proxy->in_iovec.iov_len = PROXY_MAX_IO_SZ + PROXY_HDR_SZ; diff --git a/hw/audio/ac97.c b/hw/audio/ac97.c index 365b2f1864..01b4dfbc67 100644 --- a/hw/audio/ac97.c +++ b/hw/audio/ac97.c @@ -1420,6 +1420,7 @@ static void ac97_class_init (ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5; k->revision = 0x01; k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc = "Intel 82801AA AC97 Audio"; dc->vmsd = &vmstate_ac97; dc->props = ac97_properties; diff --git a/hw/audio/adlib.c b/hw/audio/adlib.c index f72e6ee372..0421d473ff 100644 --- a/hw/audio/adlib.c +++ b/hw/audio/adlib.c @@ -364,6 +364,7 @@ static void adlib_class_initfn (ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS (klass); dc->realize = adlib_realizefn; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc = ADLIB_DESC; dc->props = adlib_properties; } diff --git a/hw/audio/cs4231a.c b/hw/audio/cs4231a.c index 7365c3c1de..666096be07 100644 --- a/hw/audio/cs4231a.c +++ b/hw/audio/cs4231a.c @@ -685,6 +685,7 @@ static void cs4231a_class_initfn (ObjectClass *klass, void *data) dc->realize = cs4231a_realizefn; dc->reset = cs4231a_reset; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc = "Crystal Semiconductor CS4231A"; dc->vmsd = &vmstate_cs4231a; dc->props = cs4231a_properties; diff --git a/hw/audio/es1370.c b/hw/audio/es1370.c index f2c40daec1..adb66ced71 100644 --- a/hw/audio/es1370.c +++ b/hw/audio/es1370.c @@ -1069,6 +1069,7 @@ static void es1370_class_init (ObjectClass *klass, void *data) k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; k->subsystem_vendor_id = 0x4942; k->subsystem_id = 0x4c4c; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc = "ENSONIQ AudioPCI ES1370"; dc->vmsd = &vmstate_es1370; } diff --git a/hw/audio/gus.c b/hw/audio/gus.c index f45ed0b0e9..71be3c6ba5 100644 --- a/hw/audio/gus.c +++ b/hw/audio/gus.c @@ -315,6 +315,7 @@ static void gus_class_initfn (ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS (klass); dc->realize = gus_realizefn; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc = "Gravis Ultrasound GF1"; dc->vmsd = &vmstate_gus; dc->props = gus_properties; diff --git a/hw/audio/hda-codec.c b/hw/audio/hda-codec.c index 362d8c0cc0..9550c97e65 100644 --- a/hw/audio/hda-codec.c +++ b/hw/audio/hda-codec.c @@ -1034,6 +1034,7 @@ static void hda_audio_output_class_init(ObjectClass *klass, void *data) k->exit = hda_audio_exit; k->command = hda_audio_command; k->stream = hda_audio_stream; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc = "HDA Audio Codec, output-only (line-out)"; dc->vmsd = &vmstate_hda_audio; dc->props = hda_audio_properties; @@ -1055,6 +1056,7 @@ static void hda_audio_duplex_class_init(ObjectClass *klass, void *data) k->exit = hda_audio_exit; k->command = hda_audio_command; k->stream = hda_audio_stream; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc = "HDA Audio Codec, duplex (line-out, line-in)"; dc->vmsd = &vmstate_hda_audio; dc->props = hda_audio_properties; @@ -1076,6 +1078,7 @@ static void hda_audio_micro_class_init(ObjectClass *klass, void *data) k->exit = hda_audio_exit; k->command = hda_audio_command; k->stream = hda_audio_stream; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc = "HDA Audio Codec, duplex (speaker, microphone)"; dc->vmsd = &vmstate_hda_audio; dc->props = hda_audio_properties; diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index 58984dc738..32e44adb53 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -1258,6 +1258,7 @@ static void intel_hda_class_init_ich6(ObjectClass *klass, void *data) k->device_id = 0x2668; k->revision = 1; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc = "Intel HD Audio Controller (ich6)"; } @@ -1268,6 +1269,7 @@ static void intel_hda_class_init_ich9(ObjectClass *klass, void *data) k->device_id = 0x293e; k->revision = 3; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc = "Intel HD Audio Controller (ich9)"; } @@ -1296,6 +1298,7 @@ static void hda_codec_device_class_init(ObjectClass *klass, void *data) DeviceClass *k = DEVICE_CLASS(klass); k->init = hda_codec_dev_init; k->exit = hda_codec_dev_exit; + set_bit(DEVICE_CATEGORY_SOUND, k->categories); k->bus_type = TYPE_HDA_BUS; k->props = hda_props; } diff --git a/hw/audio/pcspk.c b/hw/audio/pcspk.c index 7ad59a13e4..9004ce3d1f 100644 --- a/hw/audio/pcspk.c +++ b/hw/audio/pcspk.c @@ -191,6 +191,7 @@ static void pcspk_class_initfn(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = pcspk_realizefn; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->no_user = 1; dc->props = pcspk_properties; } diff --git a/hw/audio/pl041.c b/hw/audio/pl041.c index 7d331b9577..b66d6d23f9 100644 --- a/hw/audio/pl041.c +++ b/hw/audio/pl041.c @@ -626,6 +626,7 @@ static void pl041_device_class_init(ObjectClass *klass, void *data) SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); k->init = pl041_init; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->no_user = 1; dc->reset = pl041_device_reset; dc->vmsd = &vmstate_pl041; diff --git a/hw/audio/sb16.c b/hw/audio/sb16.c index e697bc1498..3e586888eb 100644 --- a/hw/audio/sb16.c +++ b/hw/audio/sb16.c @@ -1412,6 +1412,7 @@ static void sb16_class_initfn (ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS (klass); dc->realize = sb16_realizefn; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc = "Creative Sound Blaster 16"; dc->vmsd = &vmstate_sb16; dc->props = sb16_properties; diff --git a/hw/block/fdc.c b/hw/block/fdc.c index d32f6ba411..50a350f7c8 100644 --- a/hw/block/fdc.c +++ b/hw/block/fdc.c @@ -2249,6 +2249,7 @@ static void isabus_fdc_class_init(ObjectClass *klass, void *data) dc->reset = fdctrl_external_reset_isa; dc->vmsd = &vmstate_isa_fdc; dc->props = isa_fdc_properties; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static const TypeInfo isa_fdc_info = { @@ -2282,6 +2283,7 @@ static void sysbus_fdc_class_init(ObjectClass *klass, void *data) dc->reset = fdctrl_external_reset_sysbus; dc->vmsd = &vmstate_sysbus_fdc; dc->props = sysbus_fdc_properties; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static const TypeInfo sysbus_fdc_info = { @@ -2305,6 +2307,7 @@ static void sun4m_fdc_class_init(ObjectClass *klass, void *data) dc->reset = fdctrl_external_reset_sysbus; dc->vmsd = &vmstate_sysbus_fdc; dc->props = sun4m_fdc_properties; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static const TypeInfo sun4m_fdc_info = { diff --git a/hw/block/nvme.c b/hw/block/nvme.c index f15f04a33c..0263e5c636 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -866,6 +866,7 @@ static void nvme_class_init(ObjectClass *oc, void *data) pc->revision = 1; pc->is_express = 1; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->desc = "Non-Volatile Memory Express"; dc->props = nvme_props; dc->vmsd = &nvme_vmstate; diff --git a/hw/block/pc_sysfw.c b/hw/block/pc_sysfw.c index 0669410cfc..7db68f0ca0 100644 --- a/hw/block/pc_sysfw.c +++ b/hw/block/pc_sysfw.c @@ -286,6 +286,7 @@ static void pcsysfw_class_init (ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS (klass); + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->desc = "PC System Firmware"; dc->init = pcsysfw_init; dc->props = pcsysfw_properties; diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 2bcd7318bc..825011d8cb 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -192,6 +192,9 @@ static uint32_t pflash_read (pflash_t *pfl, hwaddr offset, case 0xe8: /* Write block */ /* Status register read */ ret = pfl->status; + if (width > 2) { + ret |= pfl->status << 16; + } DPRINTF("%s: status %x\n", __func__, ret); break; case 0x90: @@ -720,6 +723,7 @@ static void pflash_cfi01_class_init(ObjectClass *klass, void *data) dc->realize = pflash_cfi01_realize; dc->props = pflash_cfi01_properties; dc->vmsd = &vmstate_pflash; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c index 1237b6acd3..e2f55cc946 100644 --- a/hw/block/virtio-blk.c +++ b/hw/block/virtio-blk.c @@ -736,6 +736,7 @@ static void virtio_blk_class_init(ObjectClass *klass, void *data) VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); dc->exit = virtio_blk_device_exit; dc->props = virtio_blk_properties; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); vdc->init = virtio_blk_device_init; vdc->get_config = virtio_blk_update_config; vdc->set_config = virtio_blk_set_config; diff --git a/hw/block/xen_disk.c b/hw/block/xen_disk.c index 247f32f4ee..727f4331c0 100644 --- a/hw/block/xen_disk.c +++ b/hw/block/xen_disk.c @@ -93,6 +93,7 @@ struct XenBlkDev { char *type; char *dev; char *devtype; + bool directiosafe; const char *fileproto; const char *filename; int ring_ref; @@ -701,6 +702,7 @@ static int blk_init(struct XenDevice *xendev) { struct XenBlkDev *blkdev = container_of(xendev, struct XenBlkDev, xendev); int info = 0; + char *directiosafe = NULL; /* read xenstore entries */ if (blkdev->params == NULL) { @@ -733,6 +735,8 @@ static int blk_init(struct XenDevice *xendev) if (blkdev->devtype == NULL) { blkdev->devtype = xenstore_read_be_str(&blkdev->xendev, "device-type"); } + directiosafe = xenstore_read_be_str(&blkdev->xendev, "direct-io-safe"); + blkdev->directiosafe = (directiosafe && atoi(directiosafe)); /* do we have all we need? */ if (blkdev->params == NULL || @@ -760,6 +764,8 @@ static int blk_init(struct XenDevice *xendev) xenstore_write_be_int(&blkdev->xendev, "feature-flush-cache", 1); xenstore_write_be_int(&blkdev->xendev, "feature-persistent", 1); xenstore_write_be_int(&blkdev->xendev, "info", info); + + g_free(directiosafe); return 0; out_error: @@ -773,6 +779,8 @@ out_error: blkdev->dev = NULL; g_free(blkdev->devtype); blkdev->devtype = NULL; + g_free(directiosafe); + blkdev->directiosafe = false; return -1; } @@ -783,7 +791,11 @@ static int blk_connect(struct XenDevice *xendev) bool readonly = true; /* read-only ? */ - qflags = BDRV_O_CACHE_WB | BDRV_O_NATIVE_AIO; + if (blkdev->directiosafe) { + qflags = BDRV_O_NOCACHE | BDRV_O_NATIVE_AIO; + } else { + qflags = BDRV_O_CACHE_WB; + } if (strcmp(blkdev->mode, "w") == 0) { qflags |= BDRV_O_RDWR; readonly = false; diff --git a/hw/char/debugcon.c b/hw/char/debugcon.c index 03db12fda8..02d0d57a79 100644 --- a/hw/char/debugcon.c +++ b/hw/char/debugcon.c @@ -122,6 +122,7 @@ static void debugcon_isa_class_initfn(ObjectClass *klass, void *data) dc->realize = debugcon_isa_realizefn; dc->props = debugcon_isa_properties; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo debugcon_isa_info = { diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index 69b9ed2c4d..5c17eaa577 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -449,6 +449,7 @@ static void imx_serial_class_init(ObjectClass *klass, void *data) k->init = imx_serial_init; dc->vmsd = &vmstate_imx_serial; dc->reset = imx_serial_reset_at_boot; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); dc->desc = "i.MX series UART"; dc->props = imx32_serial_properties; } diff --git a/hw/char/ipack.c b/hw/char/ipack.c index e15540d5cd..f890471db5 100644 --- a/hw/char/ipack.c +++ b/hw/char/ipack.c @@ -74,6 +74,7 @@ static Property ipack_device_props[] = { static void ipack_device_class_init(ObjectClass *klass, void *data) { DeviceClass *k = DEVICE_CLASS(klass); + set_bit(DEVICE_CATEGORY_INPUT, k->categories); k->bus_type = TYPE_IPACK_BUS; k->init = ipack_device_dev_init; k->exit = ipack_device_dev_exit; diff --git a/hw/char/ipoctal232.c b/hw/char/ipoctal232.c index c9698a6bc4..88e2ccae75 100644 --- a/hw/char/ipoctal232.c +++ b/hw/char/ipoctal232.c @@ -585,6 +585,7 @@ static void ipoctal_class_init(ObjectClass *klass, void *data) ic->mem_read8 = mem_read8; ic->mem_write8 = mem_write8; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); dc->desc = "GE IP-Octal 232 8-channel RS-232 IndustryPack"; dc->props = ipoctal_properties; dc->vmsd = &vmstate_ipoctal; diff --git a/hw/char/parallel.c b/hw/char/parallel.c index ad96ea59c6..7a3b2647cf 100644 --- a/hw/char/parallel.c +++ b/hw/char/parallel.c @@ -607,6 +607,7 @@ static void parallel_isa_class_initfn(ObjectClass *klass, void *data) dc->realize = parallel_isa_realizefn; dc->props = parallel_isa_properties; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } static const TypeInfo parallel_isa_info = { diff --git a/hw/char/serial-isa.c b/hw/char/serial-isa.c index cea8212428..5cb77b311a 100644 --- a/hw/char/serial-isa.c +++ b/hw/char/serial-isa.c @@ -102,6 +102,7 @@ static void serial_isa_class_initfn(ObjectClass *klass, void *data) dc->realize = serial_isa_realizefn; dc->vmsd = &vmstate_isa_serial; dc->props = serial_isa_properties; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } static const TypeInfo serial_isa_info = { diff --git a/hw/char/serial-pci.c b/hw/char/serial-pci.c index a17c702624..aec6705a01 100644 --- a/hw/char/serial-pci.c +++ b/hw/char/serial-pci.c @@ -205,6 +205,7 @@ static void serial_pci_class_initfn(ObjectClass *klass, void *data) pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; dc->vmsd = &vmstate_pci_serial; dc->props = serial_pci_properties; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data) @@ -219,6 +220,7 @@ static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data) pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; dc->vmsd = &vmstate_pci_multi_serial; dc->props = multi_2x_serial_pci_properties; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data) @@ -233,6 +235,7 @@ static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data) pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; dc->vmsd = &vmstate_pci_multi_serial; dc->props = multi_4x_serial_pci_properties; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } static const TypeInfo serial_pci_info = { diff --git a/hw/char/spapr_vty.c b/hw/char/spapr_vty.c index 2993848889..a7997213b6 100644 --- a/hw/char/spapr_vty.c +++ b/hw/char/spapr_vty.c @@ -142,6 +142,21 @@ static Property spapr_vty_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static const VMStateDescription vmstate_spapr_vty = { + .name = "spapr_vty", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_SPAPR_VIO(sdev, VIOsPAPRVTYDevice), + + VMSTATE_UINT32(in, VIOsPAPRVTYDevice), + VMSTATE_UINT32(out, VIOsPAPRVTYDevice), + VMSTATE_BUFFER(buf, VIOsPAPRVTYDevice), + VMSTATE_END_OF_LIST() + }, +}; + static void spapr_vty_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -152,6 +167,7 @@ static void spapr_vty_class_init(ObjectClass *klass, void *data) k->dt_type = "serial"; k->dt_compatible = "hvterm1"; dc->props = spapr_vty_properties; + dc->vmsd = &vmstate_spapr_vty; } static const TypeInfo spapr_vty_info = { diff --git a/hw/char/tpci200.c b/hw/char/tpci200.c index a199e57525..d9e17b2956 100644 --- a/hw/char/tpci200.c +++ b/hw/char/tpci200.c @@ -652,6 +652,7 @@ static void tpci200_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_BRIDGE_OTHER; k->subsystem_vendor_id = PCI_VENDOR_ID_TEWS; k->subsystem_id = 0x300A; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); dc->desc = "TEWS TPCI200 IndustryPack carrier"; dc->vmsd = &vmstate_tpci200; } diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c index cc3d1dd27a..da417c7010 100644 --- a/hw/char/virtio-serial-bus.c +++ b/hw/char/virtio-serial-bus.c @@ -971,6 +971,7 @@ static void virtio_serial_port_class_init(ObjectClass *klass, void *data) { DeviceClass *k = DEVICE_CLASS(klass); k->init = virtser_port_qdev_init; + set_bit(DEVICE_CATEGORY_INPUT, k->categories); k->bus_type = TYPE_VIRTIO_SERIAL_BUS; k->exit = virtser_port_qdev_exit; k->unplug = qdev_simple_unplug_cb; @@ -1017,6 +1018,7 @@ static void virtio_serial_class_init(ObjectClass *klass, void *data) VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); dc->exit = virtio_serial_device_exit; dc->props = virtio_serial_properties; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); vdc->init = virtio_serial_device_init; vdc->get_features = get_features; vdc->get_config = get_config; diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index 3a324fb0c3..6e1ed1e13c 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -74,13 +74,14 @@ static void bit_prop_set(DeviceState *dev, Property *props, bool val) } } -static int print_bit(DeviceState *dev, Property *prop, char *dest, size_t len) +static int prop_print_bit(DeviceState *dev, Property *prop, char *dest, + size_t len) { uint32_t *p = qdev_get_prop_ptr(dev, prop); return snprintf(dest, len, (*p & qdev_get_prop_mask(prop)) ? "on" : "off"); } -static void get_bit(Object *obj, Visitor *v, void *opaque, +static void prop_get_bit(Object *obj, Visitor *v, void *opaque, const char *name, Error **errp) { DeviceState *dev = DEVICE(obj); @@ -91,7 +92,7 @@ static void get_bit(Object *obj, Visitor *v, void *opaque, visit_type_bool(v, &value, name, errp); } -static void set_bit(Object *obj, Visitor *v, void *opaque, +static void prop_set_bit(Object *obj, Visitor *v, void *opaque, const char *name, Error **errp) { DeviceState *dev = DEVICE(obj); @@ -115,9 +116,9 @@ static void set_bit(Object *obj, Visitor *v, void *opaque, PropertyInfo qdev_prop_bit = { .name = "boolean", .legacy_name = "on/off", - .print = print_bit, - .get = get_bit, - .set = set_bit, + .print = prop_print_bit, + .get = prop_get_bit, + .set = prop_set_bit, }; /* --- bool --- */ diff --git a/hw/cpu/icc_bus.c b/hw/cpu/icc_bus.c index 8788144b98..8748cc5046 100644 --- a/hw/cpu/icc_bus.c +++ b/hw/cpu/icc_bus.c @@ -101,11 +101,19 @@ static void icc_bridge_init(Object *obj) s->icc_bus.apic_address_space = &s->apic_container; } +static void icc_bridge_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); +} + static const TypeInfo icc_bridge_info = { .name = TYPE_ICC_BRIDGE, .parent = TYPE_SYS_BUS_DEVICE, .instance_init = icc_bridge_init, .instance_size = sizeof(ICCBridgeState), + .class_init = icc_bridge_class_init, }; diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c index a440575def..dbd1f4a47b 100644 --- a/hw/display/cirrus_vga.c +++ b/hw/display/cirrus_vga.c @@ -2937,6 +2937,7 @@ static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_cirrus_vga; dc->realize = isa_cirrus_vga_realizefn; dc->props = isa_cirrus_vga_properties; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); } static const TypeInfo isa_cirrus_vga_info = { @@ -3002,6 +3003,7 @@ static void cirrus_vga_class_init(ObjectClass *klass, void *data) k->vendor_id = PCI_VENDOR_ID_CIRRUS; k->device_id = CIRRUS_ID_CLGD5446; k->class_id = PCI_CLASS_DISPLAY_VGA; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); dc->desc = "Cirrus CLGD 54xx VGA"; dc->vmsd = &vmstate_pci_cirrus_vga; dc->props = pci_vga_cirrus_properties; diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c index 79a0a5063e..2d3e9124a5 100644 --- a/hw/display/g364fb.c +++ b/hw/display/g364fb.c @@ -528,6 +528,7 @@ static void g364fb_sysbus_class_init(ObjectClass *klass, void *data) SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); k->init = g364fb_sysbus_init; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); dc->desc = "G364 framebuffer"; dc->reset = g364fb_sysbus_reset; dc->vmsd = &vmstate_g364fb; diff --git a/hw/display/pl110.c b/hw/display/pl110.c index 60afcf39e1..31993a7eee 100644 --- a/hw/display/pl110.c +++ b/hw/display/pl110.c @@ -481,6 +481,7 @@ static void pl110_class_init(ObjectClass *klass, void *data) SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); k->init = pl110_init; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); dc->no_user = 1; dc->vmsd = &vmstate_pl110; } @@ -498,6 +499,7 @@ static void pl110_versatile_class_init(ObjectClass *klass, void *data) SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); k->init = pl110_versatile_init; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); dc->no_user = 1; dc->vmsd = &vmstate_pl110; } @@ -515,6 +517,7 @@ static void pl111_class_init(ObjectClass *klass, void *data) SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); k->init = pl111_init; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); dc->no_user = 1; dc->vmsd = &vmstate_pl110; } diff --git a/hw/display/qxl.c b/hw/display/qxl.c index ddefa0668a..c5370575ea 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -2323,6 +2323,7 @@ static void qxl_primary_class_init(ObjectClass *klass, void *data) k->vendor_id = REDHAT_PCI_VENDOR_ID; k->device_id = QXL_DEVICE_ID_STABLE; k->class_id = PCI_CLASS_DISPLAY_VGA; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); dc->desc = "Spice QXL GPU (primary, vga compatible)"; dc->reset = qxl_reset_handler; dc->vmsd = &qxl_vmstate; @@ -2345,6 +2346,7 @@ static void qxl_secondary_class_init(ObjectClass *klass, void *data) k->vendor_id = REDHAT_PCI_VENDOR_ID; k->device_id = QXL_DEVICE_ID_STABLE; k->class_id = PCI_CLASS_DISPLAY_OTHER; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); dc->desc = "Spice QXL GPU (secondary)"; dc->reset = qxl_reset_handler; dc->vmsd = &qxl_vmstate; diff --git a/hw/display/vga-isa.c b/hw/display/vga-isa.c index 8d560ecef0..c2a19ad6ba 100644 --- a/hw/display/vga-isa.c +++ b/hw/display/vga-isa.c @@ -87,6 +87,7 @@ static void vga_isa_class_initfn(ObjectClass *klass, void *data) dc->reset = vga_isa_reset; dc->vmsd = &vmstate_vga_common; dc->props = vga_isa_properties; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); } static const TypeInfo vga_isa_info = { diff --git a/hw/display/vga-pci.c b/hw/display/vga-pci.c index 3e150abe8d..b3a45c81da 100644 --- a/hw/display/vga-pci.c +++ b/hw/display/vga-pci.c @@ -198,6 +198,7 @@ static void vga_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_DISPLAY_VGA; dc->vmsd = &vmstate_vga_pci; dc->props = vga_pci_properties; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); } static const TypeInfo vga_info = { diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c index 3536cded92..a6a8cdc2e1 100644 --- a/hw/display/vmware_vga.c +++ b/hw/display/vmware_vga.c @@ -1306,6 +1306,7 @@ static void vmsvga_class_init(ObjectClass *klass, void *data) dc->reset = vmsvga_reset; dc->vmsd = &vmstate_vmware_vga; dc->props = vga_vmware_properties; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); } static const TypeInfo vmsvga_info = { diff --git a/hw/i2c/bitbang_i2c.c b/hw/i2c/bitbang_i2c.c index 5f8b97291a..853d455a35 100644 --- a/hw/i2c/bitbang_i2c.c +++ b/hw/i2c/bitbang_i2c.c @@ -227,6 +227,7 @@ static void gpio_i2c_class_init(ObjectClass *klass, void *data) SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); k->init = gpio_i2c_init; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->desc = "Virtual GPIO to I2C bridge"; } diff --git a/hw/i2c/core.c b/hw/i2c/core.c index 22ef3b9617..c97e7f7dc0 100644 --- a/hw/i2c/core.c +++ b/hw/i2c/core.c @@ -224,6 +224,7 @@ static void i2c_slave_class_init(ObjectClass *klass, void *data) { DeviceClass *k = DEVICE_CLASS(klass); k->init = i2c_slave_qdev_init; + set_bit(DEVICE_CATEGORY_MISC, k->categories); k->bus_type = TYPE_I2C_BUS; k->props = i2c_props; } diff --git a/hw/i386/kvm/pci-assign.c b/hw/i386/kvm/pci-assign.c index ff33dc8850..5618173cc6 100644 --- a/hw/i386/kvm/pci-assign.c +++ b/hw/i386/kvm/pci-assign.c @@ -1856,6 +1856,7 @@ static void assign_class_init(ObjectClass *klass, void *data) dc->props = assigned_dev_properties; dc->vmsd = &vmstate_assigned_device; dc->reset = reset_assigned_device; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->desc = "KVM-based PCI passthrough"; } diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 419adde0ea..bba150fd74 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1338,6 +1338,7 @@ static void sysbus_ahci_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_sysbus_ahci; dc->props = sysbus_ahci_properties; dc->reset = sysbus_ahci_reset; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static const TypeInfo sysbus_ahci_info = { diff --git a/hw/ide/ich.c b/hw/ide/ich.c index 4eb5488993..bff952bf6a 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -160,6 +160,7 @@ static void ich_ahci_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_STORAGE_SATA; dc->vmsd = &vmstate_ich9_ahci; dc->reset = pci_ich9_reset; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static const TypeInfo ich_ahci_info = { diff --git a/hw/ide/isa.c b/hw/ide/isa.c index 7243c82c0f..bbc8c6b9c9 100644 --- a/hw/ide/isa.c +++ b/hw/ide/isa.c @@ -118,6 +118,7 @@ static void isa_ide_class_initfn(ObjectClass *klass, void *data) dc->fw_name = "ide"; dc->reset = isa_ide_reset; dc->props = isa_ide_properties; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static const TypeInfo isa_ide_info = { diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 38ad92423d..ef4ba2b2c5 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -131,7 +131,7 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret) int sector_num = (s->lba << 2) + (s->io_buffer_index >> 9); int nsector = io->len >> 9; - MACIO_DPRINTF("precopying unaligned %d bytes to %#lx\n", + MACIO_DPRINTF("precopying unaligned %d bytes to %#" HWADDR_PRIx "\n", unaligned, io->addr + io->len - unaligned); bdrv_read(s->bs, sector_num + nsector, io->remainder, 1); @@ -212,14 +212,15 @@ static void pmac_ide_transfer_cb(void *opaque, int ret) s->nsector -= n; } - MACIO_DPRINTF("remainder: %d io->len: %d nsector: %d sector_num: %ld\n", + MACIO_DPRINTF("remainder: %d io->len: %d nsector: %d " + "sector_num: %" PRId64 "\n", io->remainder_len, io->len, s->nsector, sector_num); if (io->remainder_len && io->len) { /* guest wants the rest of its previous transfer */ int remainder_len = MIN(io->remainder_len, io->len); uint8_t *p = &io->remainder[0x200 - remainder_len]; - MACIO_DPRINTF("copying remainder %d bytes at %#lx\n", + MACIO_DPRINTF("copying remainder %d bytes at %#" HWADDR_PRIx "\n", remainder_len, io->addr); switch (s->dma_cmd) { @@ -261,7 +262,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret) if (unaligned) { int nsector = io->len >> 9; - MACIO_DPRINTF("precopying unaligned %d bytes to %#lx\n", + MACIO_DPRINTF("precopying unaligned %d bytes to %#" HWADDR_PRIx "\n", unaligned, io->addr + io->len - unaligned); switch (s->dma_cmd) { diff --git a/hw/ide/piix.c b/hw/ide/piix.c index 58532fe09b..56cf00ea19 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -248,6 +248,7 @@ static void piix3_ide_class_init(ObjectClass *klass, void *data) k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1; k->class_id = PCI_CLASS_STORAGE_IDE; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->no_user = 1; } @@ -267,6 +268,7 @@ static void piix3_ide_xen_class_init(ObjectClass *klass, void *data) k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1; k->class_id = PCI_CLASS_STORAGE_IDE; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->no_user = 1; dc->unplug = pci_piix3_xen_ide_unplug; } @@ -289,6 +291,7 @@ static void piix4_ide_class_init(ObjectClass *klass, void *data) k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371AB; k->class_id = PCI_CLASS_STORAGE_IDE; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->no_user = 1; } diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c index 6a272b046d..1d84e15378 100644 --- a/hw/ide/qdev.c +++ b/hw/ide/qdev.c @@ -282,6 +282,7 @@ static void ide_device_class_init(ObjectClass *klass, void *data) { DeviceClass *k = DEVICE_CLASS(klass); k->init = ide_qdev_init; + set_bit(DEVICE_CATEGORY_STORAGE, k->categories); k->bus_type = TYPE_IDE_BUS; k->props = ide_props; } diff --git a/hw/ide/via.c b/hw/ide/via.c index 5a831916f1..d324884b71 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -223,6 +223,7 @@ static void via_ide_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_VIA_IDE; k->revision = 0x06; k->class_id = PCI_CLASS_STORAGE_IDE; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->no_user = 1; } diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 091912e2ca..6b3c071588 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -34,34 +34,19 @@ * ICP: Presentation layer */ -struct icp_server_state { - uint32_t xirr; - uint8_t pending_priority; - uint8_t mfrr; - qemu_irq output; -}; - #define XISR_MASK 0x00ffffff #define CPPR_MASK 0xff000000 #define XISR(ss) (((ss)->xirr) & XISR_MASK) #define CPPR(ss) (((ss)->xirr) >> 24) -struct ics_state; - -struct icp_state { - long nr_servers; - struct icp_server_state *ss; - struct ics_state *ics; -}; - -static void ics_reject(struct ics_state *ics, int nr); -static void ics_resend(struct ics_state *ics); -static void ics_eoi(struct ics_state *ics, int nr); +static void ics_reject(ICSState *ics, int nr); +static void ics_resend(ICSState *ics); +static void ics_eoi(ICSState *ics, int nr); -static void icp_check_ipi(struct icp_state *icp, int server) +static void icp_check_ipi(XICSState *icp, int server) { - struct icp_server_state *ss = icp->ss + server; + ICPState *ss = icp->ss + server; if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) { return; @@ -78,9 +63,9 @@ static void icp_check_ipi(struct icp_state *icp, int server) qemu_irq_raise(ss->output); } -static void icp_resend(struct icp_state *icp, int server) +static void icp_resend(XICSState *icp, int server) { - struct icp_server_state *ss = icp->ss + server; + ICPState *ss = icp->ss + server; if (ss->mfrr < CPPR(ss)) { icp_check_ipi(icp, server); @@ -88,9 +73,9 @@ static void icp_resend(struct icp_state *icp, int server) ics_resend(icp->ics); } -static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr) +static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr) { - struct icp_server_state *ss = icp->ss + server; + ICPState *ss = icp->ss + server; uint8_t old_cppr; uint32_t old_xisr; @@ -112,9 +97,9 @@ static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr) } } -static void icp_set_mfrr(struct icp_state *icp, int server, uint8_t mfrr) +static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr) { - struct icp_server_state *ss = icp->ss + server; + ICPState *ss = icp->ss + server; ss->mfrr = mfrr; if (mfrr < CPPR(ss)) { @@ -122,7 +107,7 @@ static void icp_set_mfrr(struct icp_state *icp, int server, uint8_t mfrr) } } -static uint32_t icp_accept(struct icp_server_state *ss) +static uint32_t icp_accept(ICPState *ss) { uint32_t xirr = ss->xirr; @@ -135,9 +120,9 @@ static uint32_t icp_accept(struct icp_server_state *ss) return xirr; } -static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr) +static void icp_eoi(XICSState *icp, int server, uint32_t xirr) { - struct icp_server_state *ss = icp->ss + server; + ICPState *ss = icp->ss + server; /* Send EOI -> ICS */ ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK); @@ -148,9 +133,9 @@ static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr) } } -static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority) +static void icp_irq(XICSState *icp, int server, int nr, uint8_t priority) { - struct icp_server_state *ss = icp->ss + server; + ICPState *ss = icp->ss + server; trace_xics_icp_irq(server, nr, priority); @@ -168,39 +153,59 @@ static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority) } } -/* - * ICS: Source layer - */ - -struct ics_irq_state { - int server; - uint8_t priority; - uint8_t saved_priority; -#define XICS_STATUS_ASSERTED 0x1 -#define XICS_STATUS_SENT 0x2 -#define XICS_STATUS_REJECTED 0x4 -#define XICS_STATUS_MASKED_PENDING 0x8 - uint8_t status; +static const VMStateDescription vmstate_icp_server = { + .name = "icp/server", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + /* Sanity check */ + VMSTATE_UINT32(xirr, ICPState), + VMSTATE_UINT8(pending_priority, ICPState), + VMSTATE_UINT8(mfrr, ICPState), + VMSTATE_END_OF_LIST() + }, }; -struct ics_state { - int nr_irqs; - int offset; - qemu_irq *qirqs; - bool *islsi; - struct ics_irq_state *irqs; - struct icp_state *icp; +static void icp_reset(DeviceState *dev) +{ + ICPState *icp = ICP(dev); + + icp->xirr = 0; + icp->pending_priority = 0xff; + icp->mfrr = 0xff; + + /* Make all outputs are deasserted */ + qemu_set_irq(icp->output, 0); +} + +static void icp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = icp_reset; + dc->vmsd = &vmstate_icp_server; +} + +static TypeInfo icp_info = { + .name = TYPE_ICP, + .parent = TYPE_DEVICE, + .instance_size = sizeof(ICPState), + .class_init = icp_class_init, }; -static int ics_valid_irq(struct ics_state *ics, uint32_t nr) +/* + * ICS: Source layer + */ +static int ics_valid_irq(ICSState *ics, uint32_t nr) { return (nr >= ics->offset) && (nr < (ics->offset + ics->nr_irqs)); } -static void resend_msi(struct ics_state *ics, int srcno) +static void resend_msi(ICSState *ics, int srcno) { - struct ics_irq_state *irq = ics->irqs + srcno; + ICSIRQState *irq = ics->irqs + srcno; /* FIXME: filter by server#? */ if (irq->status & XICS_STATUS_REJECTED) { @@ -212,9 +217,9 @@ static void resend_msi(struct ics_state *ics, int srcno) } } -static void resend_lsi(struct ics_state *ics, int srcno) +static void resend_lsi(ICSState *ics, int srcno) { - struct ics_irq_state *irq = ics->irqs + srcno; + ICSIRQState *irq = ics->irqs + srcno; if ((irq->priority != 0xff) && (irq->status & XICS_STATUS_ASSERTED) @@ -224,9 +229,9 @@ static void resend_lsi(struct ics_state *ics, int srcno) } } -static void set_irq_msi(struct ics_state *ics, int srcno, int val) +static void set_irq_msi(ICSState *ics, int srcno, int val) { - struct ics_irq_state *irq = ics->irqs + srcno; + ICSIRQState *irq = ics->irqs + srcno; trace_xics_set_irq_msi(srcno, srcno + ics->offset); @@ -240,9 +245,9 @@ static void set_irq_msi(struct ics_state *ics, int srcno, int val) } } -static void set_irq_lsi(struct ics_state *ics, int srcno, int val) +static void set_irq_lsi(ICSState *ics, int srcno, int val) { - struct ics_irq_state *irq = ics->irqs + srcno; + ICSIRQState *irq = ics->irqs + srcno; trace_xics_set_irq_lsi(srcno, srcno + ics->offset); if (val) { @@ -255,7 +260,7 @@ static void set_irq_lsi(struct ics_state *ics, int srcno, int val) static void ics_set_irq(void *opaque, int srcno, int val) { - struct ics_state *ics = (struct ics_state *)opaque; + ICSState *ics = (ICSState *)opaque; if (ics->islsi[srcno]) { set_irq_lsi(ics, srcno, val); @@ -264,9 +269,9 @@ static void ics_set_irq(void *opaque, int srcno, int val) } } -static void write_xive_msi(struct ics_state *ics, int srcno) +static void write_xive_msi(ICSState *ics, int srcno) { - struct ics_irq_state *irq = ics->irqs + srcno; + ICSIRQState *irq = ics->irqs + srcno; if (!(irq->status & XICS_STATUS_MASKED_PENDING) || (irq->priority == 0xff)) { @@ -277,16 +282,16 @@ static void write_xive_msi(struct ics_state *ics, int srcno) icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority); } -static void write_xive_lsi(struct ics_state *ics, int srcno) +static void write_xive_lsi(ICSState *ics, int srcno) { resend_lsi(ics, srcno); } -static void ics_write_xive(struct ics_state *ics, int nr, int server, +static void ics_write_xive(ICSState *ics, int nr, int server, uint8_t priority, uint8_t saved_priority) { int srcno = nr - ics->offset; - struct ics_irq_state *irq = ics->irqs + srcno; + ICSIRQState *irq = ics->irqs + srcno; irq->server = server; irq->priority = priority; @@ -301,16 +306,16 @@ static void ics_write_xive(struct ics_state *ics, int nr, int server, } } -static void ics_reject(struct ics_state *ics, int nr) +static void ics_reject(ICSState *ics, int nr) { - struct ics_irq_state *irq = ics->irqs + nr - ics->offset; + ICSIRQState *irq = ics->irqs + nr - ics->offset; trace_xics_ics_reject(nr, nr - ics->offset); irq->status |= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */ irq->status &= ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */ } -static void ics_resend(struct ics_state *ics) +static void ics_resend(ICSState *ics) { int i; @@ -324,10 +329,10 @@ static void ics_resend(struct ics_state *ics) } } -static void ics_eoi(struct ics_state *ics, int nr) +static void ics_eoi(ICSState *ics, int nr) { int srcno = nr - ics->offset; - struct ics_irq_state *irq = ics->irqs + srcno; + ICSIRQState *irq = ics->irqs + srcno; trace_xics_ics_eoi(nr); @@ -336,11 +341,92 @@ static void ics_eoi(struct ics_state *ics, int nr) } } +static void ics_reset(DeviceState *dev) +{ + ICSState *ics = ICS(dev); + int i; + + memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); + for (i = 0; i < ics->nr_irqs; i++) { + ics->irqs[i].priority = 0xff; + ics->irqs[i].saved_priority = 0xff; + } +} + +static int ics_post_load(void *opaque, int version_id) +{ + int i; + ICSState *ics = opaque; + + for (i = 0; i < ics->icp->nr_servers; i++) { + icp_resend(ics->icp, i); + } + + return 0; +} + +static const VMStateDescription vmstate_ics_irq = { + .name = "ics/irq", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT32(server, ICSIRQState), + VMSTATE_UINT8(priority, ICSIRQState), + VMSTATE_UINT8(saved_priority, ICSIRQState), + VMSTATE_UINT8(status, ICSIRQState), + VMSTATE_END_OF_LIST() + }, +}; + +static const VMStateDescription vmstate_ics = { + .name = "ics", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .post_load = ics_post_load, + .fields = (VMStateField []) { + /* Sanity check */ + VMSTATE_UINT32_EQUAL(nr_irqs, ICSState), + + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs, + vmstate_ics_irq, ICSIRQState), + VMSTATE_END_OF_LIST() + }, +}; + +static int ics_realize(DeviceState *dev) +{ + ICSState *ics = ICS(dev); + + ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); + ics->islsi = g_malloc0(ics->nr_irqs * sizeof(bool)); + ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs); + + return 0; +} + +static void ics_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->init = ics_realize; + dc->vmsd = &vmstate_ics; + dc->reset = ics_reset; +} + +static TypeInfo ics_info = { + .name = TYPE_ICS, + .parent = TYPE_DEVICE, + .instance_size = sizeof(ICSState), + .class_init = ics_class_init, +}; + /* * Exported functions */ -qemu_irq xics_get_qirq(struct icp_state *icp, int irq) +qemu_irq xics_get_qirq(XICSState *icp, int irq) { if (!ics_valid_irq(icp->ics, irq)) { return NULL; @@ -349,13 +435,17 @@ qemu_irq xics_get_qirq(struct icp_state *icp, int irq) return icp->ics->qirqs[irq - icp->ics->offset]; } -void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi) +void xics_set_irq_type(XICSState *icp, int irq, bool lsi) { assert(ics_valid_irq(icp->ics, irq)); icp->ics->islsi[irq - icp->ics->offset] = lsi; } +/* + * Guest interfaces + */ + static target_ulong h_cppr(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { @@ -405,7 +495,7 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPREnvironment *spapr, uint32_t nargs, target_ulong args, uint32_t nret, target_ulong rets) { - struct ics_state *ics = spapr->icp->ics; + ICSState *ics = spapr->icp->ics; uint32_t nr, server, priority; if ((nargs != 3) || (nret != 1)) { @@ -433,7 +523,7 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPREnvironment *spapr, uint32_t nargs, target_ulong args, uint32_t nret, target_ulong rets) { - struct ics_state *ics = spapr->icp->ics; + ICSState *ics = spapr->icp->ics; uint32_t nr; if ((nargs != 1) || (nret != 3)) { @@ -458,7 +548,7 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPREnvironment *spapr, uint32_t nargs, target_ulong args, uint32_t nret, target_ulong rets) { - struct ics_state *ics = spapr->icp->ics; + ICSState *ics = spapr->icp->ics; uint32_t nr; if ((nargs != 1) || (nret != 1)) { @@ -484,7 +574,7 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPREnvironment *spapr, uint32_t nargs, target_ulong args, uint32_t nret, target_ulong rets) { - struct ics_state *ics = spapr->icp->ics; + ICSState *ics = spapr->icp->ics; uint32_t nr; if ((nargs != 1) || (nret != 1)) { @@ -506,32 +596,27 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPREnvironment *spapr, rtas_st(rets, 0, 0); /* Success */ } -static void xics_reset(void *opaque) +/* + * XICS + */ + +static void xics_reset(DeviceState *d) { - struct icp_state *icp = (struct icp_state *)opaque; - struct ics_state *ics = icp->ics; + XICSState *icp = XICS(d); int i; for (i = 0; i < icp->nr_servers; i++) { - icp->ss[i].xirr = 0; - icp->ss[i].pending_priority = 0xff; - icp->ss[i].mfrr = 0xff; - /* Make all outputs are deasserted */ - qemu_set_irq(icp->ss[i].output, 0); + device_reset(DEVICE(&icp->ss[i])); } - memset(ics->irqs, 0, sizeof(struct ics_irq_state) * ics->nr_irqs); - for (i = 0; i < ics->nr_irqs; i++) { - ics->irqs[i].priority = 0xff; - ics->irqs[i].saved_priority = 0xff; - } + device_reset(DEVICE(icp->ics)); } -void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu) +void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; - struct icp_server_state *ss = &icp->ss[cs->cpu_index]; + ICPState *ss = &icp->ss[cs->cpu_index]; assert(cs->cpu_index < icp->nr_servers); @@ -551,37 +636,73 @@ void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu) } } -struct icp_state *xics_system_init(int nr_servers, int nr_irqs) +static void xics_realize(DeviceState *dev, Error **errp) { - struct icp_state *icp; - struct ics_state *ics; - - icp = g_malloc0(sizeof(*icp)); - icp->nr_servers = nr_servers; - icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state)); + XICSState *icp = XICS(dev); + ICSState *ics = icp->ics; + int i; - ics = g_malloc0(sizeof(*ics)); - ics->nr_irqs = nr_irqs; + ics->nr_irqs = icp->nr_irqs; ics->offset = XICS_IRQ_BASE; - ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state)); - ics->islsi = g_malloc0(nr_irqs * sizeof(bool)); - - icp->ics = ics; ics->icp = icp; + qdev_init_nofail(DEVICE(ics)); - ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, nr_irqs); + icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState)); + for (i = 0; i < icp->nr_servers; i++) { + char buffer[32]; + object_initialize(&icp->ss[i], TYPE_ICP); + snprintf(buffer, sizeof(buffer), "icp[%d]", i); + object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]), NULL); + qdev_init_nofail(DEVICE(&icp->ss[i])); + } +} - spapr_register_hypercall(H_CPPR, h_cppr); - spapr_register_hypercall(H_IPI, h_ipi); - spapr_register_hypercall(H_XIRR, h_xirr); - spapr_register_hypercall(H_EOI, h_eoi); +static void xics_initfn(Object *obj) +{ + XICSState *xics = XICS(obj); + + xics->ics = ICS(object_new(TYPE_ICS)); + object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL); +} + +static Property xics_properties[] = { + DEFINE_PROP_UINT32("nr_servers", XICSState, nr_servers, -1), + DEFINE_PROP_UINT32("nr_irqs", XICSState, nr_irqs, -1), + DEFINE_PROP_END_OF_LIST(), +}; + +static void xics_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = xics_realize; + dc->props = xics_properties; + dc->reset = xics_reset; spapr_rtas_register("ibm,set-xive", rtas_set_xive); spapr_rtas_register("ibm,get-xive", rtas_get_xive); spapr_rtas_register("ibm,int-off", rtas_int_off); spapr_rtas_register("ibm,int-on", rtas_int_on); - qemu_register_reset(xics_reset, icp); + spapr_register_hypercall(H_CPPR, h_cppr); + spapr_register_hypercall(H_IPI, h_ipi); + spapr_register_hypercall(H_XIRR, h_xirr); + spapr_register_hypercall(H_EOI, h_eoi); +} + +static const TypeInfo xics_info = { + .name = TYPE_XICS, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XICSState), + .class_init = xics_class_init, + .instance_init = xics_initfn, +}; - return icp; +static void xics_register_types(void) +{ + type_register_static(&xics_info); + type_register_static(&ics_info); + type_register_static(&icp_info); } + +type_init(xics_register_types) diff --git a/hw/isa/i82378.c b/hw/isa/i82378.c index b25ed04af3..a542134585 100644 --- a/hw/isa/i82378.c +++ b/hw/isa/i82378.c @@ -261,6 +261,7 @@ static void pci_i82378_class_init(ObjectClass *klass, void *data) k->subsystem_vendor_id = 0x0; k->subsystem_id = 0x0; dc->vmsd = &vmstate_pci_i82378; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->props = i82378_properties; } diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index d1921aa635..5633d08b62 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -600,6 +600,7 @@ static void ich9_lpc_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->reset = ich9_lpc_reset; k->init = ich9_lpc_initfn; dc->vmsd = &vmstate_ich9_lpc; diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 2174eaaf87..8fe4fcb4a1 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -281,6 +281,7 @@ static void via_ac97_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_VIA_AC97; k->revision = 0x50; k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc = "AC97"; } @@ -322,6 +323,7 @@ static void via_mc97_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_VIA_MC97; k->class_id = PCI_CLASS_COMMUNICATION_OTHER; k->revision = 0x30; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); dc->desc = "MC97"; } @@ -401,6 +403,7 @@ static void via_pm_class_init(ObjectClass *klass, void *data) k->revision = 0x40; dc->desc = "PM"; dc->vmsd = &vmstate_acpi; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->props = via_pm_properties; } diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index a7e9dcf4bf..99014415ca 100644 --- a/hw/mips/mips_fulong2e.c +++ b/hw/mips/mips_fulong2e.c @@ -126,7 +126,7 @@ static int64_t load_kernel (CPUMIPSState *env) if (loaderparams.initrd_filename) { initrd_size = get_image_size (loaderparams.initrd_filename); if (initrd_size > 0) { - initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; + initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK; if (initrd_offset + initrd_size > ram_size) { fprintf(stderr, "qemu: memory too small for initial ram disk '%s'\n", diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index dad58c0ed2..1589b59194 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -47,6 +47,7 @@ #include "sysemu/blockdev.h" #include "exec/address-spaces.h" #include "hw/sysbus.h" /* SysBusDevice */ +#include "qemu/host-utils.h" //#define DEBUG_BOARD_INIT @@ -79,8 +80,12 @@ typedef struct { SerialState *uart; } MaltaFPGAState; +#define TYPE_MIPS_MALTA "mips-malta" +#define MIPS_MALTA(obj) OBJECT_CHECK(MaltaState, (obj), TYPE_MIPS_MALTA) + typedef struct { - SysBusDevice busdev; + SysBusDevice parent_obj; + qemu_irq *i8259; } MaltaState; @@ -144,12 +149,12 @@ struct _eeprom24c0x_t { typedef struct _eeprom24c0x_t eeprom24c0x_t; -static eeprom24c0x_t eeprom = { +static eeprom24c0x_t spd_eeprom = { .contents = { - /* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00, + /* 00000000: */ 0x80,0x08,0xFF,0x0D,0x0A,0xFF,0x40,0x00, /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01, - /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00, - /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40, + /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x00,0x00, + /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0xFF, /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00, /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -165,69 +170,157 @@ static eeprom24c0x_t eeprom = { }, }; -static uint8_t eeprom24c0x_read(void) +static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size) +{ + enum { SDR = 0x4, DDR2 = 0x8 } type; + uint8_t *spd = spd_eeprom.contents; + uint8_t nbanks = 0; + uint16_t density = 0; + int i; + + /* work in terms of MB */ + ram_size >>= 20; + + while ((ram_size >= 4) && (nbanks <= 2)) { + int sz_log2 = MIN(31 - clz32(ram_size), 14); + nbanks++; + density |= 1 << (sz_log2 - 2); + ram_size -= 1 << sz_log2; + } + + /* split to 2 banks if possible */ + if ((nbanks == 1) && (density > 1)) { + nbanks++; + density >>= 1; + } + + if (density & 0xff00) { + density = (density & 0xe0) | ((density >> 8) & 0x1f); + type = DDR2; + } else if (!(density & 0x1f)) { + type = DDR2; + } else { + type = SDR; + } + + if (ram_size) { + fprintf(stderr, "Warning: SPD cannot represent final %dMB" + " of SDRAM\n", (int)ram_size); + } + + /* fill in SPD memory information */ + spd[2] = type; + spd[5] = nbanks; + spd[31] = density; + + /* checksum */ + spd[63] = 0; + for (i = 0; i < 63; i++) { + spd[63] += spd[i]; + } + + /* copy for SMBUS */ + memcpy(eeprom, spd, sizeof(spd_eeprom.contents)); +} + +static void generate_eeprom_serial(uint8_t *eeprom) +{ + int i, pos = 0; + uint8_t mac[6] = { 0x00 }; + uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 }; + + /* version */ + eeprom[pos++] = 0x01; + + /* count */ + eeprom[pos++] = 0x02; + + /* MAC address */ + eeprom[pos++] = 0x01; /* MAC */ + eeprom[pos++] = 0x06; /* length */ + memcpy(&eeprom[pos], mac, sizeof(mac)); + pos += sizeof(mac); + + /* serial number */ + eeprom[pos++] = 0x02; /* serial */ + eeprom[pos++] = 0x05; /* length */ + memcpy(&eeprom[pos], sn, sizeof(sn)); + pos += sizeof(sn); + + /* checksum */ + eeprom[pos] = 0; + for (i = 0; i < pos; i++) { + eeprom[pos] += eeprom[i]; + } +} + +static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom) { logout("%u: scl = %u, sda = %u, data = 0x%02x\n", - eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data); - return eeprom.sda; + eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data); + return eeprom->sda; } -static void eeprom24c0x_write(int scl, int sda) +static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda) { - if (eeprom.scl && scl && (eeprom.sda != sda)) { + if (eeprom->scl && scl && (eeprom->sda != sda)) { logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n", - eeprom.tick, eeprom.scl, scl, eeprom.sda, sda, sda ? "stop" : "start"); + eeprom->tick, eeprom->scl, scl, eeprom->sda, sda, + sda ? "stop" : "start"); if (!sda) { - eeprom.tick = 1; - eeprom.command = 0; + eeprom->tick = 1; + eeprom->command = 0; } - } else if (eeprom.tick == 0 && !eeprom.ack) { + } else if (eeprom->tick == 0 && !eeprom->ack) { /* Waiting for start. */ logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n", - eeprom.tick, eeprom.scl, scl, eeprom.sda, sda); - } else if (!eeprom.scl && scl) { + eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); + } else if (!eeprom->scl && scl) { logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n", - eeprom.tick, eeprom.scl, scl, eeprom.sda, sda); - if (eeprom.ack) { + eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); + if (eeprom->ack) { logout("\ti2c ack bit = 0\n"); sda = 0; - eeprom.ack = 0; - } else if (eeprom.sda == sda) { + eeprom->ack = 0; + } else if (eeprom->sda == sda) { uint8_t bit = (sda != 0); logout("\ti2c bit = %d\n", bit); - if (eeprom.tick < 9) { - eeprom.command <<= 1; - eeprom.command += bit; - eeprom.tick++; - if (eeprom.tick == 9) { - logout("\tcommand 0x%04x, %s\n", eeprom.command, bit ? "read" : "write"); - eeprom.ack = 1; + if (eeprom->tick < 9) { + eeprom->command <<= 1; + eeprom->command += bit; + eeprom->tick++; + if (eeprom->tick == 9) { + logout("\tcommand 0x%04x, %s\n", eeprom->command, + bit ? "read" : "write"); + eeprom->ack = 1; } - } else if (eeprom.tick < 17) { - if (eeprom.command & 1) { - sda = ((eeprom.data & 0x80) != 0); + } else if (eeprom->tick < 17) { + if (eeprom->command & 1) { + sda = ((eeprom->data & 0x80) != 0); } - eeprom.address <<= 1; - eeprom.address += bit; - eeprom.tick++; - eeprom.data <<= 1; - if (eeprom.tick == 17) { - eeprom.data = eeprom.contents[eeprom.address]; - logout("\taddress 0x%04x, data 0x%02x\n", eeprom.address, eeprom.data); - eeprom.ack = 1; - eeprom.tick = 0; + eeprom->address <<= 1; + eeprom->address += bit; + eeprom->tick++; + eeprom->data <<= 1; + if (eeprom->tick == 17) { + eeprom->data = eeprom->contents[eeprom->address]; + logout("\taddress 0x%04x, data 0x%02x\n", + eeprom->address, eeprom->data); + eeprom->ack = 1; + eeprom->tick = 0; } - } else if (eeprom.tick >= 17) { + } else if (eeprom->tick >= 17) { sda = 0; } } else { logout("\tsda changed with raising scl\n"); } } else { - logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom.tick, eeprom.scl, scl, eeprom.sda, sda); + logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl, + scl, eeprom->sda, sda); } - eeprom.scl = scl; - eeprom.sda = sda; + eeprom->scl = scl; + eeprom->sda = sda; } static uint64_t malta_fpga_read(void *opaque, hwaddr addr, @@ -290,7 +383,7 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr, /* I2CINP Register */ case 0x00b00: - val = ((s->i2cin & ~1) | eeprom24c0x_read()); + val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom)); break; /* I2COE Register */ @@ -386,7 +479,7 @@ static void malta_fpga_write(void *opaque, hwaddr addr, /* I2COUT Register */ case 0x00b10: - eeprom24c0x_write(val & 0x02, val & 0x01); + eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01); s->i2cout = val; break; @@ -699,7 +792,7 @@ static int64_t load_kernel (void) if (loaderparams.initrd_filename) { initrd_size = get_image_size (loaderparams.initrd_filename); if (initrd_size > 0) { - initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; + initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK; if (initrd_offset + initrd_size > ram_size) { fprintf(stderr, "qemu: memory too small for initial ram disk '%s'\n", @@ -789,8 +882,10 @@ void mips_malta_init(QEMUMachineInitArgs *args) pflash_t *fl; MemoryRegion *system_memory = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); - MemoryRegion *bios, *bios_alias = g_new(MemoryRegion, 1); + MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1); target_long bios_size = FLASH_SIZE; + const size_t smbus_eeprom_size = 8 * 256; + uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); int64_t kernel_entry; PCIBus *pci_bus; ISABus *isa_bus; @@ -808,8 +903,8 @@ void mips_malta_init(QEMUMachineInitArgs *args) int fl_sectors = bios_size >> 16; int be; - DeviceState *dev = qdev_create(NULL, "mips-malta"); - MaltaState *s = DO_UPCAST(MaltaState, busdev.qdev, dev); + DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA); + MaltaState *s = MIPS_MALTA(dev); qdev_init_nofail(dev); @@ -858,6 +953,10 @@ void mips_malta_init(QEMUMachineInitArgs *args) vmstate_register_ram_global(ram); memory_region_add_subregion(system_memory, 0, ram); + /* generate SPD EEPROM data */ + generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); + generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); + #ifdef TARGET_WORDS_BIGENDIAN be = 1; #else @@ -916,8 +1015,11 @@ void mips_malta_init(QEMUMachineInitArgs *args) a neat trick which allows bi-endian firmware. */ #ifndef TARGET_WORDS_BIGENDIAN { - uint32_t *addr = memory_region_get_ram_ptr(bios); - uint32_t *end = addr + bios_size; + uint32_t *end, *addr = rom_ptr(FLASH_ADDRESS); + if (!addr) { + addr = memory_region_get_ram_ptr(bios); + } + end = (void *)addr + MIN(bios_size, 0x3e0000); while (addr < end) { bswap32s(addr); addr++; @@ -926,14 +1028,23 @@ void mips_malta_init(QEMUMachineInitArgs *args) #endif } - /* Map the BIOS at a 2nd physical location, as on the real board. */ - memory_region_init_alias(bios_alias, NULL, "bios.1fc", bios, 0, BIOS_SIZE); - memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_alias); + /* + * Map the BIOS at a 2nd physical location, as on the real board. + * Copy it so that we can patch in the MIPS revision, which cannot be + * handled by an overlapping region as the resulting ROM code subpage + * regions are not executable. + */ + memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE); + if (!rom_copy(memory_region_get_ram_ptr(bios_copy), + FLASH_ADDRESS, BIOS_SIZE)) { + memcpy(memory_region_get_ram_ptr(bios_copy), + memory_region_get_ram_ptr(bios), BIOS_SIZE); + } + memory_region_set_readonly(bios_copy, true); + memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy); - /* Board ID = 0x420 (Malta Board with CoreLV) - XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should - map to the board ID. */ - stl_p(memory_region_get_ram_ptr(bios) + 0x10, 0x00000420); + /* Board ID = 0x420 (Malta Board with CoreLV) */ + stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); /* Init internal devices */ cpu_mips_irq_init_cpu(env); @@ -965,8 +1076,8 @@ void mips_malta_init(QEMUMachineInitArgs *args) pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci"); smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_get_irq(NULL, 9), NULL, 0, NULL); - /* TODO: Populate SPD eeprom data. */ - smbus_eeprom_init(smbus, 8, NULL, 0); + smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size); + g_free(smbus_eeprom_buf); pit = pit_init(isa_bus, 0x40, 0, NULL); cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); DMA_init(0, cpu_exit_irq); @@ -1004,7 +1115,7 @@ static void mips_malta_class_init(ObjectClass *klass, void *data) } static const TypeInfo mips_malta_device = { - .name = "mips-malta", + .name = TYPE_MIPS_MALTA, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(MaltaState), .class_init = mips_malta_class_init, diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c index e8802c128e..fea1a15916 100644 --- a/hw/mips/mips_mipssim.c +++ b/hw/mips/mips_mipssim.c @@ -83,7 +83,7 @@ static int64_t load_kernel(void) if (loaderparams.initrd_filename) { initrd_size = get_image_size (loaderparams.initrd_filename); if (initrd_size > 0) { - initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; + initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK; if (initrd_offset + initrd_size > loaderparams.ram_size) { fprintf(stderr, "qemu: memory too small for initial ram disk '%s'\n", diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index 4bc2e3fa7a..7af08b8d0f 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -102,7 +102,7 @@ static int64_t load_kernel(void) if (loaderparams.initrd_filename) { initrd_size = get_image_size (loaderparams.initrd_filename); if (initrd_size > 0) { - initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; + initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK; if (initrd_offset + initrd_size > ram_size) { fprintf(stderr, "qemu: memory too small for initial ram disk '%s'\n", diff --git a/hw/misc/applesmc.c b/hw/misc/applesmc.c index bfafa518e1..1e8d183e7f 100644 --- a/hw/misc/applesmc.c +++ b/hw/misc/applesmc.c @@ -263,6 +263,7 @@ static void qdev_applesmc_class_init(ObjectClass *klass, void *data) dc->realize = applesmc_isa_realize; dc->reset = qdev_applesmc_isa_reset; dc->props = applesmc_isa_properties; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo applesmc_isa_info = { diff --git a/hw/misc/debugexit.c b/hw/misc/debugexit.c index d754cf1f2e..9db5680015 100644 --- a/hw/misc/debugexit.c +++ b/hw/misc/debugexit.c @@ -58,6 +58,7 @@ static void debug_exit_class_initfn(ObjectClass *klass, void *data) dc->realize = debug_exit_realizefn; dc->props = debug_exit_properties; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo debug_exit_info = { diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index 4a74856c95..2838866f45 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -821,6 +821,7 @@ static void ivshmem_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_MEMORY_RAM; dc->reset = ivshmem_reset; dc->props = ivshmem_properties; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo ivshmem_info = { diff --git a/hw/misc/pc-testdev.c b/hw/misc/pc-testdev.c index 5867c70069..18e94e07b1 100644 --- a/hw/misc/pc-testdev.c +++ b/hw/misc/pc-testdev.c @@ -188,6 +188,7 @@ static void testdev_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->realize = testdev_realizefn; } diff --git a/hw/misc/pci-testdev.c b/hw/misc/pci-testdev.c index d69ff3364d..ca53b3f500 100644 --- a/hw/misc/pci-testdev.c +++ b/hw/misc/pci-testdev.c @@ -315,6 +315,7 @@ static void pci_testdev_class_init(ObjectClass *klass, void *data) k->revision = 0x00; k->class_id = PCI_CLASS_OTHERS; dc->desc = "PCI Test Device"; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->reset = qdev_pci_testdev_reset; } diff --git a/hw/misc/sga.c b/hw/misc/sga.c index 08803e7ddc..83d2fd9d3d 100644 --- a/hw/misc/sga.c +++ b/hw/misc/sga.c @@ -47,6 +47,7 @@ static void sga_class_initfn(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); dc->realize = sga_realizefn; dc->desc = "Serial Graphics Adapter"; } diff --git a/hw/misc/vfio.c b/hw/misc/vfio.c index ad8ce770dc..017e69352a 100644 --- a/hw/misc/vfio.c +++ b/hw/misc/vfio.c @@ -3299,6 +3299,7 @@ static void vfio_pci_dev_class_init(ObjectClass *klass, void *data) dc->props = vfio_pci_dev_properties; dc->vmsd = &vfio_pci_vmstate; dc->desc = "VFIO-based PCI device assignment"; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); pdc->init = vfio_initfn; pdc->exit = vfio_exitfn; pdc->config_read = vfio_pci_read_config; diff --git a/hw/net/e1000.c b/hw/net/e1000.c index b952d8d0f3..fdb1f890b4 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -1400,6 +1400,7 @@ static void e1000_class_init(ObjectClass *klass, void *data) k->device_id = E1000_DEVID; k->revision = 0x03; k->class_id = PCI_CLASS_NETWORK_ETHERNET; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); dc->desc = "Intel Gigabit Ethernet"; dc->reset = qdev_e1000_reset; dc->vmsd = &vmstate_e1000; diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index e0befb2590..ffa60d5c96 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -47,6 +47,7 @@ #include "hw/nvram/eeprom93xx.h" #include "sysemu/sysemu.h" #include "sysemu/dma.h" +#include "qemu/bitops.h" /* QEMU sends frames smaller than 60 bytes to ethernet nics. * Such frames are rejected by real nics and their emulations. @@ -105,7 +106,6 @@ #define PCI_IO_SIZE 64 #define PCI_FLASH_SIZE (128 * KiB) -#define BIT(n) (1 << (n)) #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) /* The SCB accepts the following controls for the Tx and Rx units: */ @@ -2083,6 +2083,7 @@ static void eepro100_class_init(ObjectClass *klass, void *data) info = eepro100_get_class_by_name(object_class_get_name(klass)); + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); dc->props = e100_properties; dc->desc = info->desc; k->vendor_id = PCI_VENDOR_ID_INTEL; diff --git a/hw/net/lance.c b/hw/net/lance.c index 98bcdfce8b..1be7b72506 100644 --- a/hw/net/lance.c +++ b/hw/net/lance.c @@ -150,6 +150,7 @@ static void lance_class_init(ObjectClass *klass, void *data) SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); k->init = lance_init; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); dc->fw_name = "ethernet"; dc->reset = lance_reset; dc->vmsd = &vmstate_lance; diff --git a/hw/net/mipsnet.c b/hw/net/mipsnet.c index 908085073a..61578edcf0 100644 --- a/hw/net/mipsnet.c +++ b/hw/net/mipsnet.c @@ -264,6 +264,7 @@ static void mipsnet_class_init(ObjectClass *klass, void *data) SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); k->init = mipsnet_sysbus_init; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); dc->desc = "MIPS Simulator network device"; dc->reset = mipsnet_sysbus_reset; dc->vmsd = &vmstate_mipsnet; diff --git a/hw/net/ne2000-isa.c b/hw/net/ne2000-isa.c index e3c8076382..26b83cef0d 100644 --- a/hw/net/ne2000-isa.c +++ b/hw/net/ne2000-isa.c @@ -98,6 +98,7 @@ static void isa_ne2000_class_initfn(ObjectClass *klass, void *data) dc->realize = isa_ne2000_realizefn; dc->props = ne2000_isa_properties; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); } static const TypeInfo ne2000_isa_info = { diff --git a/hw/net/ne2000.c b/hw/net/ne2000.c index 8d43fd9afe..31afd28c7c 100644 --- a/hw/net/ne2000.c +++ b/hw/net/ne2000.c @@ -772,6 +772,7 @@ static void ne2000_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_NETWORK_ETHERNET; dc->vmsd = &vmstate_pci_ne2000; dc->props = ne2000_properties; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); } static const TypeInfo ne2000_info = { diff --git a/hw/net/opencores_eth.c b/hw/net/opencores_eth.c index 46375574e4..513f345eec 100644 --- a/hw/net/opencores_eth.c +++ b/hw/net/opencores_eth.c @@ -713,6 +713,7 @@ static void open_eth_class_init(ObjectClass *klass, void *data) SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); k->init = sysbus_open_eth_init; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); dc->desc = "Opencores 10/100 Mbit Ethernet"; dc->reset = qdev_open_eth_reset; dc->props = open_eth_properties; diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c index 6ef28f77a2..2c2301c360 100644 --- a/hw/net/pcnet-pci.c +++ b/hw/net/pcnet-pci.c @@ -366,6 +366,7 @@ static void pcnet_class_init(ObjectClass *klass, void *data) dc->reset = pci_reset; dc->vmsd = &vmstate_pci_pcnet; dc->props = pcnet_properties; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); } static const TypeInfo pcnet_info = { diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c index 65520340fc..ee3b6903a1 100644 --- a/hw/net/rtl8139.c +++ b/hw/net/rtl8139.c @@ -3563,6 +3563,7 @@ static void rtl8139_class_init(ObjectClass *klass, void *data) dc->reset = rtl8139_reset; dc->vmsd = &vmstate_rtl8139; dc->props = rtl8139_properties; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); } static const TypeInfo rtl8139_info = { diff --git a/hw/net/spapr_llan.c b/hw/net/spapr_llan.c index 03a09f2047..46f7d5fa6d 100644 --- a/hw/net/spapr_llan.c +++ b/hw/net/spapr_llan.c @@ -81,9 +81,9 @@ typedef struct VIOsPAPRVLANDevice { VIOsPAPRDevice sdev; NICConf nicconf; NICState *nic; - int isopen; + bool isopen; target_ulong buf_list; - int add_buf_ptr, use_buf_ptr, rx_bufs; + uint32_t add_buf_ptr, use_buf_ptr, rx_bufs; target_ulong rxq_ptr; } VIOsPAPRVLANDevice; @@ -500,6 +500,25 @@ static Property spapr_vlan_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static const VMStateDescription vmstate_spapr_llan = { + .name = "spapr_llan", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_SPAPR_VIO(sdev, VIOsPAPRVLANDevice), + /* LLAN state */ + VMSTATE_BOOL(isopen, VIOsPAPRVLANDevice), + VMSTATE_UINTTL(buf_list, VIOsPAPRVLANDevice), + VMSTATE_UINT32(add_buf_ptr, VIOsPAPRVLANDevice), + VMSTATE_UINT32(use_buf_ptr, VIOsPAPRVLANDevice), + VMSTATE_UINT32(rx_bufs, VIOsPAPRVLANDevice), + VMSTATE_UINTTL(rxq_ptr, VIOsPAPRVLANDevice), + + VMSTATE_END_OF_LIST() + }, +}; + static void spapr_vlan_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -514,6 +533,7 @@ static void spapr_vlan_class_init(ObjectClass *klass, void *data) k->signal_mask = 0x1; dc->props = spapr_vlan_properties; k->rtce_window_size = 0x10000000; + dc->vmsd = &vmstate_spapr_llan; } static const TypeInfo spapr_vlan_info = { diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c index 679f50c33a..aa1880cb87 100644 --- a/hw/net/virtio-net.c +++ b/hw/net/virtio-net.c @@ -1638,6 +1638,7 @@ static void virtio_net_class_init(ObjectClass *klass, void *data) VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); dc->exit = virtio_net_device_exit; dc->props = virtio_net_properties; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); vdc->init = virtio_net_device_init; vdc->get_config = virtio_net_get_config; vdc->set_config = virtio_net_set_config; diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c index b39ff08f28..49c2466434 100644 --- a/hw/net/vmxnet3.c +++ b/hw/net/vmxnet3.c @@ -528,7 +528,7 @@ vmxnet3_setup_tx_offloads(VMXNET3State *s) break; default: - assert(false); + g_assert_not_reached(); return false; } @@ -575,7 +575,7 @@ vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx, stats->ucastBytesTxOK += tot_len; break; default: - assert(false); + g_assert_not_reached(); } if (s->offload_mode == VMXNET3_OM_TSO) { @@ -599,7 +599,7 @@ vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx, break; default: - assert(false); + g_assert_not_reached(); } } @@ -634,7 +634,7 @@ vmxnet3_on_rx_done_update_stats(VMXNET3State *s, stats->ucastBytesRxOK += tot_len; break; default: - assert(false); + g_assert_not_reached(); } if (tot_len > s->mtu) { @@ -643,7 +643,7 @@ vmxnet3_on_rx_done_update_stats(VMXNET3State *s, } break; default: - assert(false); + g_assert_not_reached(); } } @@ -1106,7 +1106,7 @@ vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size) { if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { - assert(false); + g_assert_not_reached(); } VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size); @@ -1651,7 +1651,7 @@ vmxnet3_io_bar1_write(void *opaque, case VMXNET3_REG_ICR: VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d", val, size); - assert(false); + g_assert_not_reached(); break; /* Event Cause Register */ @@ -1801,7 +1801,7 @@ vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data, break; default: - assert(false); + g_assert_not_reached(); } return true; @@ -2453,6 +2453,7 @@ static void vmxnet3_class_init(ObjectClass *class, void *data) dc->reset = vmxnet3_qdev_reset; dc->vmsd = &vmstate_vmxnet3; dc->props = vmxnet3_properties; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); } static const TypeInfo vmxnet3_info = { diff --git a/hw/net/vmxnet_tx_pkt.c b/hw/net/vmxnet_tx_pkt.c index fc01e4da3c..f7344c4cb3 100644 --- a/hw/net/vmxnet_tx_pkt.c +++ b/hw/net/vmxnet_tx_pkt.c @@ -287,7 +287,7 @@ void vmxnet_tx_pkt_build_vheader(struct VmxnetTxPkt *pkt, bool tso_enable, break; default: - assert(false); + g_assert_not_reached(); } if (csum_enable) { diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 924438bcc2..a08f27ce2e 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -82,7 +82,7 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size, } if (kernel_size < 0) { - qemu_log("QEMU: couldn't load the kernel '%s'\n", + fprintf(stderr, "QEMU: couldn't load the kernel '%s'\n", kernel_filename); exit(1); } @@ -96,7 +96,7 @@ static void openrisc_sim_init(QEMUMachineInitArgs *args) ram_addr_t ram_size = args->ram_size; const char *cpu_model = args->cpu_model; const char *kernel_filename = args->kernel_filename; - OpenRISCCPU *cpu = NULL; + OpenRISCCPU *cpu = NULL; MemoryRegion *ram; int n; @@ -107,7 +107,7 @@ static void openrisc_sim_init(QEMUMachineInitArgs *args) for (n = 0; n < smp_cpus; n++) { cpu = cpu_openrisc_init(cpu_model); if (cpu == NULL) { - qemu_log("Unable to find CPU definition!\n"); + fprintf(stderr, "Unable to find CPU definition!\n"); exit(1); } qemu_register_reset(main_cpu_reset, cpu); diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c index b98bfb0664..0e521a86fe 100644 --- a/hw/pci-bridge/i82801b11.c +++ b/hw/pci-bridge/i82801b11.c @@ -81,12 +81,14 @@ err_bridge: static void i82801b11_bridge_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); k->is_bridge = 1; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82801BA_11; k->revision = ICH9_D2P_A2_REVISION; k->init = i82801b11_bridge_initfn; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } static const TypeInfo i82801b11_bridge_info = { diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c index bb541ebb12..47122c5276 100644 --- a/hw/pci-bridge/ioh3420.c +++ b/hw/pci-bridge/ioh3420.c @@ -220,6 +220,7 @@ static void ioh3420_class_init(ObjectClass *klass, void *data) k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_IOH_EPORT; k->revision = PCI_DEVICE_ID_IOH_REV; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->desc = "Intel IOH device id 3420 PCIE Root Port"; dc->reset = ioh3420_reset; dc->vmsd = &vmstate_ioh3420; diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index 5f11323fe6..a00642cf09 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -141,6 +141,7 @@ static void pci_bridge_dev_class_init(ObjectClass *klass, void *data) dc->reset = qdev_pci_bridge_dev_reset; dc->props = pci_bridge_dev_properties; dc->vmsd = &pci_bridge_dev_vmstate; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } static const TypeInfo pci_bridge_dev_info = { diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 1810dd23f2..33eff37d89 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -187,6 +187,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data) k->vendor_id = PCI_VENDOR_ID_TI; k->device_id = PCI_DEVICE_ID_TI_XIO3130D; k->revision = XIO3130_REVISION; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->desc = "TI X3130 Downstream Port of PCI Express Switch"; dc->reset = xio3130_downstream_reset; dc->vmsd = &vmstate_xio3130_downstream; diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c index 8e0d97a644..e9969a9356 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -161,6 +161,7 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data) k->vendor_id = PCI_VENDOR_ID_TI; k->device_id = PCI_DEVICE_ID_TI_XIO3130U; k->revision = XIO3130_REVISION; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->desc = "TI X3130 Upstream Port of PCI Express Switch"; dc->reset = xio3130_upstream_reset; dc->vmsd = &vmstate_xio3130_upstream; diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 3756ce9a4b..bef7be194f 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -536,6 +536,7 @@ static void pbm_host_class_init(ObjectClass *klass, void *data) SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); k->init = pci_pbm_init_device; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->reset = pci_pbm_reset; } @@ -558,6 +559,7 @@ static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) k->revision = 0x11; k->config_write = pci_bridge_write_config; k->is_bridge = 1; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->reset = pci_bridge_reset; dc->vmsd = &vmstate_pci_device; } diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index 646204e1e5..f00793d819 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -407,6 +407,7 @@ static void e500_pcihost_class_init(ObjectClass *klass, void *data) SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); k->init = e500_pcihost_initfn; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->props = pcihost_properties; dc->vmsd = &vmstate_ppce500_pci; } diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index b41d5646cd..09d3b32291 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -210,6 +210,7 @@ static void raven_pcihost_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->realize = raven_pcihost_realizefn; dc->fw_name = "pci"; dc->no_user = 1; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 6b1b3b7ab1..69234de871 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -78,6 +78,7 @@ static void q35_host_class_init(ObjectClass *klass, void *data) hc->root_bus_path = q35_host_root_bus_path; dc->realize = q35_host_realize; dc->props = mch_props; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->fw_name = "pci"; } @@ -306,6 +307,7 @@ static void mch_class_init(ObjectClass *klass, void *data) k->init = mch_init; k->config_write = mch_write_config; dc->reset = mch_reset; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->desc = "Host bridge"; dc->vmsd = &vmstate_mch; k->vendor_id = PCI_VENDOR_ID_INTEL; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 48ae09283d..16bfab90b0 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -32,6 +32,7 @@ #include "sysemu/cpus.h" #include "sysemu/kvm.h" #include "kvm_ppc.h" +#include "mmu-hash64.h" #include "hw/boards.h" #include "hw/ppc/ppc.h" @@ -128,6 +129,34 @@ int spapr_allocate_irq_block(int num, bool lsi) return first; } +static XICSState *try_create_xics(const char *type, int nr_servers, + int nr_irqs) +{ + DeviceState *dev; + + dev = qdev_create(NULL, type); + qdev_prop_set_uint32(dev, "nr_servers", nr_servers); + qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); + if (qdev_init(dev) < 0) { + return NULL; + } + + return XICS(dev); +} + +static XICSState *xics_system_init(int nr_servers, int nr_irqs) +{ + XICSState *icp = NULL; + + icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); + if (!icp) { + perror("Failed to create XICS\n"); + abort(); + } + + return icp; +} + static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) { int ret = 0, offset; @@ -666,7 +695,7 @@ static void spapr_cpu_reset(void *opaque) env->spr[SPR_HIOR] = 0; - env->external_htab = spapr->htab; + env->external_htab = (uint8_t *)spapr->htab; env->htab_base = -1; env->htab_mask = HTAB_SIZE(spapr) - 1; env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | @@ -710,6 +739,330 @@ static int spapr_vga_init(PCIBus *pci_bus) } } +static const VMStateDescription vmstate_spapr = { + .name = "spapr", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT32(next_irq, sPAPREnvironment), + + /* RTC offset */ + VMSTATE_UINT64(rtc_offset, sPAPREnvironment), + + VMSTATE_END_OF_LIST() + }, +}; + +#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) +#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) +#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) +#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) + +static int htab_save_setup(QEMUFile *f, void *opaque) +{ + sPAPREnvironment *spapr = opaque; + + /* "Iteration" header */ + qemu_put_be32(f, spapr->htab_shift); + + if (spapr->htab) { + spapr->htab_save_index = 0; + spapr->htab_first_pass = true; + } else { + assert(kvm_enabled()); + + spapr->htab_fd = kvmppc_get_htab_fd(false); + if (spapr->htab_fd < 0) { + fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", + strerror(errno)); + return -1; + } + } + + + return 0; +} + +static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, + int64_t max_ns) +{ + int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; + int index = spapr->htab_save_index; + int64_t starttime = qemu_get_clock_ns(rt_clock); + + assert(spapr->htab_first_pass); + + do { + int chunkstart; + + /* Consume invalid HPTEs */ + while ((index < htabslots) + && !HPTE_VALID(HPTE(spapr->htab, index))) { + index++; + CLEAN_HPTE(HPTE(spapr->htab, index)); + } + + /* Consume valid HPTEs */ + chunkstart = index; + while ((index < htabslots) + && HPTE_VALID(HPTE(spapr->htab, index))) { + index++; + CLEAN_HPTE(HPTE(spapr->htab, index)); + } + + if (index > chunkstart) { + int n_valid = index - chunkstart; + + qemu_put_be32(f, chunkstart); + qemu_put_be16(f, n_valid); + qemu_put_be16(f, 0); + qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), + HASH_PTE_SIZE_64 * n_valid); + + if ((qemu_get_clock_ns(rt_clock) - starttime) > max_ns) { + break; + } + } + } while ((index < htabslots) && !qemu_file_rate_limit(f)); + + if (index >= htabslots) { + assert(index == htabslots); + index = 0; + spapr->htab_first_pass = false; + } + spapr->htab_save_index = index; +} + +static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, + int64_t max_ns) +{ + bool final = max_ns < 0; + int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; + int examined = 0, sent = 0; + int index = spapr->htab_save_index; + int64_t starttime = qemu_get_clock_ns(rt_clock); + + assert(!spapr->htab_first_pass); + + do { + int chunkstart, invalidstart; + + /* Consume non-dirty HPTEs */ + while ((index < htabslots) + && !HPTE_DIRTY(HPTE(spapr->htab, index))) { + index++; + examined++; + } + + chunkstart = index; + /* Consume valid dirty HPTEs */ + while ((index < htabslots) + && HPTE_DIRTY(HPTE(spapr->htab, index)) + && HPTE_VALID(HPTE(spapr->htab, index))) { + CLEAN_HPTE(HPTE(spapr->htab, index)); + index++; + examined++; + } + + invalidstart = index; + /* Consume invalid dirty HPTEs */ + while ((index < htabslots) + && HPTE_DIRTY(HPTE(spapr->htab, index)) + && !HPTE_VALID(HPTE(spapr->htab, index))) { + CLEAN_HPTE(HPTE(spapr->htab, index)); + index++; + examined++; + } + + if (index > chunkstart) { + int n_valid = invalidstart - chunkstart; + int n_invalid = index - invalidstart; + + qemu_put_be32(f, chunkstart); + qemu_put_be16(f, n_valid); + qemu_put_be16(f, n_invalid); + qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), + HASH_PTE_SIZE_64 * n_valid); + sent += index - chunkstart; + + if (!final && (qemu_get_clock_ns(rt_clock) - starttime) > max_ns) { + break; + } + } + + if (examined >= htabslots) { + break; + } + + if (index >= htabslots) { + assert(index == htabslots); + index = 0; + } + } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); + + if (index >= htabslots) { + assert(index == htabslots); + index = 0; + } + + spapr->htab_save_index = index; + + return (examined >= htabslots) && (sent == 0) ? 1 : 0; +} + +#define MAX_ITERATION_NS 5000000 /* 5 ms */ +#define MAX_KVM_BUF_SIZE 2048 + +static int htab_save_iterate(QEMUFile *f, void *opaque) +{ + sPAPREnvironment *spapr = opaque; + int rc = 0; + + /* Iteration header */ + qemu_put_be32(f, 0); + + if (!spapr->htab) { + assert(kvm_enabled()); + + rc = kvmppc_save_htab(f, spapr->htab_fd, + MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); + if (rc < 0) { + return rc; + } + } else if (spapr->htab_first_pass) { + htab_save_first_pass(f, spapr, MAX_ITERATION_NS); + } else { + rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); + } + + /* End marker */ + qemu_put_be32(f, 0); + qemu_put_be16(f, 0); + qemu_put_be16(f, 0); + + return rc; +} + +static int htab_save_complete(QEMUFile *f, void *opaque) +{ + sPAPREnvironment *spapr = opaque; + + /* Iteration header */ + qemu_put_be32(f, 0); + + if (!spapr->htab) { + int rc; + + assert(kvm_enabled()); + + rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); + if (rc < 0) { + return rc; + } + close(spapr->htab_fd); + spapr->htab_fd = -1; + } else { + htab_save_later_pass(f, spapr, -1); + } + + /* End marker */ + qemu_put_be32(f, 0); + qemu_put_be16(f, 0); + qemu_put_be16(f, 0); + + return 0; +} + +static int htab_load(QEMUFile *f, void *opaque, int version_id) +{ + sPAPREnvironment *spapr = opaque; + uint32_t section_hdr; + int fd = -1; + + if (version_id < 1 || version_id > 1) { + fprintf(stderr, "htab_load() bad version\n"); + return -EINVAL; + } + + section_hdr = qemu_get_be32(f); + + if (section_hdr) { + /* First section, just the hash shift */ + if (spapr->htab_shift != section_hdr) { + return -EINVAL; + } + return 0; + } + + if (!spapr->htab) { + assert(kvm_enabled()); + + fd = kvmppc_get_htab_fd(true); + if (fd < 0) { + fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", + strerror(errno)); + } + } + + while (true) { + uint32_t index; + uint16_t n_valid, n_invalid; + + index = qemu_get_be32(f); + n_valid = qemu_get_be16(f); + n_invalid = qemu_get_be16(f); + + if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { + /* End of Stream */ + break; + } + + if ((index + n_valid + n_invalid) > + (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { + /* Bad index in stream */ + fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " + "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, + spapr->htab_shift); + return -EINVAL; + } + + if (spapr->htab) { + if (n_valid) { + qemu_get_buffer(f, HPTE(spapr->htab, index), + HASH_PTE_SIZE_64 * n_valid); + } + if (n_invalid) { + memset(HPTE(spapr->htab, index + n_valid), 0, + HASH_PTE_SIZE_64 * n_invalid); + } + } else { + int rc; + + assert(fd >= 0); + + rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); + if (rc < 0) { + return rc; + } + } + } + + if (!spapr->htab) { + assert(fd >= 0); + close(fd); + } + + return 0; +} + +static SaveVMHandlers savevm_htab_handlers = { + .save_live_setup = htab_save_setup, + .save_live_iterate = htab_save_iterate, + .save_live_complete = htab_save_complete, + .load_state = htab_load, +}; + /* pSeries LPAR / sPAPR hardware init */ static void ppc_spapr_init(QEMUMachineInitArgs *args) { @@ -848,9 +1201,6 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args) /* Set up EPOW events infrastructure */ spapr_events_init(spapr); - /* Set up IOMMU */ - spapr_iommu_init(); - /* Set up VIO bus */ spapr->vio_bus = spapr_vio_bus_init(); @@ -953,6 +1303,10 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args) spapr->entry_point = 0x100; + vmstate_register(NULL, 0, &vmstate_spapr, spapr); + register_savevm_live(NULL, "spapr/htab", -1, 1, + &savevm_htab_handlers, spapr); + /* Prepare the device tree */ spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, initrd_base, initrd_size, diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index ed32decebf..67d6cd91d1 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -115,7 +115,7 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr, } ppc_hash64_store_hpte1(env, hpte, ptel); /* eieio(); FIXME: need some sort of barrier for smp? */ - ppc_hash64_store_hpte0(env, hpte, pteh); + ppc_hash64_store_hpte0(env, hpte, pteh | HPTE64_V_HPTE_DIRTY); args[0] = pte_index + i; return H_SUCCESS; @@ -152,7 +152,7 @@ static RemoveResult remove_hpte(CPUPPCState *env, target_ulong ptex, } *vp = v; *rp = r; - ppc_hash64_store_hpte0(env, hpte, 0); + ppc_hash64_store_hpte0(env, hpte, HPTE64_V_HPTE_DIRTY); rb = compute_tlbie_rb(v, r, ptex); ppc_tlb_invalidate_one(env, rb); return REMOVE_SUCCESS; @@ -282,11 +282,11 @@ static target_ulong h_protect(PowerPCCPU *cpu, sPAPREnvironment *spapr, r |= (flags << 48) & HPTE64_R_KEY_HI; r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); rb = compute_tlbie_rb(v, r, pte_index); - ppc_hash64_store_hpte0(env, hpte, v & ~HPTE64_V_VALID); + ppc_hash64_store_hpte0(env, hpte, (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY); ppc_tlb_invalidate_one(env, rb); ppc_hash64_store_hpte1(env, hpte, r); /* Don't need a memory barrier, due to qemu's global lock */ - ppc_hash64_store_hpte0(env, hpte, v); + ppc_hash64_store_hpte0(env, hpte, v | HPTE64_V_HPTE_DIRTY); return H_SUCCESS; } diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index 89b33a5478..3d4a1fcfe1 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -36,17 +36,6 @@ enum sPAPRTCEAccess { SPAPR_TCE_RW = 3, }; -struct sPAPRTCETable { - uint32_t liobn; - uint32_t window_size; - sPAPRTCE *table; - bool bypass; - int fd; - MemoryRegion iommu; - QLIST_ENTRY(sPAPRTCETable) list; -}; - - QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables; static sPAPRTCETable *spapr_tce_find_by_liobn(uint32_t liobn) @@ -96,7 +85,7 @@ static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr addr) return (IOMMUTLBEntry) { .perm = IOMMU_NONE }; } - tce = tcet->table[addr >> SPAPR_TCE_PAGE_SHIFT].tce; + tce = tcet->table[addr >> SPAPR_TCE_PAGE_SHIFT]; #ifdef DEBUG_TCE fprintf(stderr, " -> *paddr=0x%llx, *len=0x%llx\n", @@ -112,55 +101,97 @@ static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr addr) }; } +static int spapr_tce_table_pre_load(void *opaque) +{ + sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque); + + tcet->nb_table = tcet->window_size >> SPAPR_TCE_PAGE_SHIFT; + + return 0; +} + +static const VMStateDescription vmstate_spapr_tce_table = { + .name = "spapr_iommu", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .pre_load = spapr_tce_table_pre_load, + .fields = (VMStateField []) { + /* Sanity check */ + VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable), + VMSTATE_UINT32_EQUAL(window_size, sPAPRTCETable), + + /* IOMMU state */ + VMSTATE_BOOL(bypass, sPAPRTCETable), + VMSTATE_VARRAY_UINT32(table, sPAPRTCETable, nb_table, 0, vmstate_info_uint64, uint64_t), + + VMSTATE_END_OF_LIST() + }, +}; + static MemoryRegionIOMMUOps spapr_iommu_ops = { .translate = spapr_tce_translate_iommu, }; -sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, size_t window_size) +static int spapr_tce_table_realize(DeviceState *dev) { - sPAPRTCETable *tcet; - - if (spapr_tce_find_by_liobn(liobn)) { - fprintf(stderr, "Attempted to create TCE table with duplicate" - " LIOBN 0x%x\n", liobn); - return NULL; - } - - if (!window_size) { - return NULL; - } - - tcet = g_malloc0(sizeof(*tcet)); - tcet->liobn = liobn; - tcet->window_size = window_size; + sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); if (kvm_enabled()) { - tcet->table = kvmppc_create_spapr_tce(liobn, - window_size, + tcet->table = kvmppc_create_spapr_tce(tcet->liobn, + tcet->window_size, &tcet->fd); } if (!tcet->table) { - size_t table_size = (window_size >> SPAPR_TCE_PAGE_SHIFT) - * sizeof(sPAPRTCE); + size_t table_size = (tcet->window_size >> SPAPR_TCE_PAGE_SHIFT) + * sizeof(uint64_t); tcet->table = g_malloc0(table_size); } + tcet->nb_table = tcet->window_size >> SPAPR_TCE_PAGE_SHIFT; #ifdef DEBUG_TCE fprintf(stderr, "spapr_iommu: New TCE table @ %p, liobn=0x%x, " "table @ %p, fd=%d\n", tcet, liobn, tcet->table, tcet->fd); #endif - memory_region_init_iommu(&tcet->iommu, OBJECT(owner), &spapr_iommu_ops, + memory_region_init_iommu(&tcet->iommu, OBJECT(dev), &spapr_iommu_ops, "iommu-spapr", UINT64_MAX); QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list); + return 0; +} + +sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, size_t window_size) +{ + sPAPRTCETable *tcet; + + if (spapr_tce_find_by_liobn(liobn)) { + fprintf(stderr, "Attempted to create TCE table with duplicate" + " LIOBN 0x%x\n", liobn); + return NULL; + } + + if (!window_size) { + return NULL; + } + + tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE)); + tcet->liobn = liobn; + tcet->window_size = window_size; + + object_property_add_child(OBJECT(owner), "tce-table", OBJECT(tcet), NULL); + + qdev_init_nofail(DEVICE(tcet)); + return tcet; } -void spapr_tce_free(sPAPRTCETable *tcet) +static void spapr_tce_table_finalize(Object *obj) { + sPAPRTCETable *tcet = SPAPR_TCE_TABLE(obj); + QLIST_REMOVE(tcet, list); if (!kvm_enabled() || @@ -168,8 +199,6 @@ void spapr_tce_free(sPAPRTCETable *tcet) tcet->window_size) != 0)) { g_free(tcet->table); } - - g_free(tcet); } MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet) @@ -182,10 +211,11 @@ void spapr_tce_set_bypass(sPAPRTCETable *tcet, bool bypass) tcet->bypass = bypass; } -void spapr_tce_reset(sPAPRTCETable *tcet) +static void spapr_tce_reset(DeviceState *dev) { + sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); size_t table_size = (tcet->window_size >> SPAPR_TCE_PAGE_SHIFT) - * sizeof(sPAPRTCE); + * sizeof(uint64_t); tcet->bypass = false; memset(tcet->table, 0, table_size); @@ -194,7 +224,6 @@ void spapr_tce_reset(sPAPRTCETable *tcet) static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba, target_ulong tce) { - sPAPRTCE *tcep; IOMMUTLBEntry entry; if (ioba >= tcet->window_size) { @@ -203,8 +232,7 @@ static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba, return H_PARAMETER; } - tcep = tcet->table + (ioba >> SPAPR_TCE_PAGE_SHIFT); - tcep->tce = tce; + tcet->table[ioba >> SPAPR_TCE_PAGE_SHIFT] = tce; entry.target_as = &address_space_memory, entry.iova = ioba & ~SPAPR_TCE_PAGE_MASK; @@ -238,14 +266,6 @@ static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPREnvironment *spapr, return H_PARAMETER; } -void spapr_iommu_init(void) -{ - QLIST_INIT(&spapr_tce_tables); - - /* hcall-tce */ - spapr_register_hypercall(H_PUT_TCE, h_put_tce); -} - int spapr_dma_dt(void *fdt, int node_off, const char *propname, uint32_t liobn, uint64_t window, uint32_t size) { @@ -286,3 +306,31 @@ int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, return spapr_dma_dt(fdt, node_off, propname, tcet->liobn, 0, tcet->window_size); } + +static void spapr_tce_table_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + dc->vmsd = &vmstate_spapr_tce_table; + dc->init = spapr_tce_table_realize; + dc->reset = spapr_tce_reset; + + QLIST_INIT(&spapr_tce_tables); + + /* hcall-tce */ + spapr_register_hypercall(H_PUT_TCE, h_put_tce); +} + +static TypeInfo spapr_tce_table_info = { + .name = TYPE_SPAPR_TCE_TABLE, + .parent = TYPE_DEVICE, + .instance_size = sizeof(sPAPRTCETable), + .class_init = spapr_tce_table_class_init, + .instance_finalize = spapr_tce_table_finalize, +}; + +static void register_types(void) +{ + type_register_static(&spapr_tce_table_info); +} + +type_init(register_types); diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index c880a757c8..3156fdd8af 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -645,7 +645,7 @@ static void spapr_phb_reset(DeviceState *qdev) sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); /* Reset the IOMMU state */ - spapr_tce_reset(sphb->tcet); + device_reset(DEVICE(sphb->tcet)); } static Property spapr_phb_properties[] = { @@ -662,6 +662,54 @@ static Property spapr_phb_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static const VMStateDescription vmstate_spapr_pci_lsi = { + .name = "spapr_pci/lsi", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), + + VMSTATE_END_OF_LIST() + }, +}; + +static const VMStateDescription vmstate_spapr_pci_msi = { + .name = "spapr_pci/lsi", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT32(config_addr, struct spapr_pci_msi), + VMSTATE_UINT32(irq, struct spapr_pci_msi), + VMSTATE_UINT32(nvec, struct spapr_pci_msi), + + VMSTATE_END_OF_LIST() + }, +}; + +static const VMStateDescription vmstate_spapr_pci = { + .name = "spapr_pci", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), + VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState), + VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState), + VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState), + VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState), + VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState), + VMSTATE_UINT64_EQUAL(msi_win_addr, sPAPRPHBState), + VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, + vmstate_spapr_pci_lsi, struct spapr_pci_lsi), + VMSTATE_STRUCT_ARRAY(msi_table, sPAPRPHBState, SPAPR_MSIX_MAX_DEVS, 0, + vmstate_spapr_pci_msi, struct spapr_pci_msi), + + VMSTATE_END_OF_LIST() + }, +}; + static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, PCIBus *rootbus) { @@ -680,6 +728,7 @@ static void spapr_phb_class_init(ObjectClass *klass, void *data) sdc->init = spapr_phb_init; dc->props = spapr_phb_properties; dc->reset = spapr_phb_reset; + dc->vmsd = &vmstate_spapr_pci; } static const TypeInfo spapr_phb_info = { diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index 7c6f6e4275..c3f85bf078 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -316,7 +316,7 @@ int spapr_vio_send_crq(VIOsPAPRDevice *dev, uint8_t *crq) static void spapr_vio_quiesce_one(VIOsPAPRDevice *dev) { if (dev->tcet) { - spapr_tce_reset(dev->tcet); + device_reset(DEVICE(dev->tcet)); } free_crq(dev); } @@ -542,6 +542,26 @@ static const TypeInfo spapr_vio_bridge_info = { .class_init = spapr_vio_bridge_class_init, }; +const VMStateDescription vmstate_spapr_vio = { + .name = "spapr_vio", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + /* Sanity check */ + VMSTATE_UINT32_EQUAL(reg, VIOsPAPRDevice), + VMSTATE_UINT32_EQUAL(irq, VIOsPAPRDevice), + + /* General VIO device state */ + VMSTATE_UINTTL(signal_state, VIOsPAPRDevice), + VMSTATE_UINT64(crq.qladdr, VIOsPAPRDevice), + VMSTATE_UINT32(crq.qsize, VIOsPAPRDevice), + VMSTATE_UINT32(crq.qnext, VIOsPAPRDevice), + + VMSTATE_END_OF_LIST() + }, +}; + static void vio_spapr_device_class_init(ObjectClass *klass, void *data) { DeviceClass *k = DEVICE_CLASS(klass); diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index 0aeb003c9d..d69adb2f5b 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -154,17 +154,19 @@ static void s390_ipl_reset(DeviceState *dev) env->psw.mask = IPL_PSW_MASK; if (!ipl->kernel) { - /* booting firmware, tell what device to boot from */ + /* Tell firmware, if there is a preferred boot device */ + env->regs[7] = -1; DeviceState *dev_st = get_boot_device(0); - VirtioCcwDevice *ccw_dev = (VirtioCcwDevice *) object_dynamic_cast( - OBJECT(&(dev_st->parent_obj)), "virtio-blk-ccw"); - - if (ccw_dev) { - env->regs[7] = ccw_dev->sch->cssid << 24 | - ccw_dev->sch->ssid << 16 | - ccw_dev->sch->devno; - } else { - env->regs[7] = -1; + if (dev_st) { + VirtioCcwDevice *ccw_dev = (VirtioCcwDevice *) object_dynamic_cast( + OBJECT(qdev_get_parent_bus(dev_st)->parent), + TYPE_VIRTIO_CCW_DEVICE); + + if (ccw_dev) { + env->regs[7] = ccw_dev->sch->cssid << 24 | + ccw_dev->sch->ssid << 16 | + ccw_dev->sch->devno; + } } } diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c index 2ac21d4487..d7ec1736c0 100644 --- a/hw/scsi/esp-pci.c +++ b/hw/scsi/esp-pci.c @@ -392,6 +392,7 @@ static void esp_pci_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_AMD_SCSI; k->revision = 0x10; k->class_id = PCI_CLASS_STORAGE_SCSI; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter"; dc->reset = esp_pci_hard_reset; dc->vmsd = &vmstate_esp_pci_scsi; @@ -512,6 +513,7 @@ static void dc390_class_init(ObjectClass *klass, void *data) k->init = dc390_scsi_init; k->config_read = dc390_read_config; k->config_write = dc390_write_config; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->desc = "Tekram DC-390 SCSI adapter"; } diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 94639b8391..101e957d4d 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -720,6 +720,7 @@ static void sysbus_esp_class_init(ObjectClass *klass, void *data) dc->realize = sysbus_esp_realize; dc->reset = sysbus_esp_hard_reset; dc->vmsd = &vmstate_sysbus_esp_scsi; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static const TypeInfo sysbus_esp_info = { diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c index 776e31abbe..611f2aa1b2 100644 --- a/hw/scsi/lsi53c895a.c +++ b/hw/scsi/lsi53c895a.c @@ -2141,6 +2141,7 @@ static void lsi_class_init(ObjectClass *klass, void *data) k->subsystem_id = 0x1000; dc->reset = lsi_scsi_reset; dc->vmsd = &vmstate_lsi_scsi; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static const TypeInfo lsi_info = { diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index eb52164f6d..a6d5285911 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -2213,6 +2213,7 @@ static void megasas_class_init(ObjectClass *oc, void *data) dc->props = megasas_properties; dc->reset = megasas_scsi_reset; dc->vmsd = &vmstate_megasas; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->desc = "LSI MegaRAID SAS 1078"; } diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c index b5a863aa5c..fbf9173fb4 100644 --- a/hw/scsi/scsi-bus.c +++ b/hw/scsi/scsi-bus.c @@ -1881,6 +1881,7 @@ const VMStateDescription vmstate_scsi_device = { static void scsi_device_class_init(ObjectClass *klass, void *data) { DeviceClass *k = DEVICE_CLASS(klass); + set_bit(DEVICE_CATEGORY_STORAGE, k->categories); k->bus_type = TYPE_SCSI_BUS; k->init = scsi_qdev_init; k->unplug = scsi_qdev_unplug; diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c index 55b44b9910..3f4c53fc19 100644 --- a/hw/scsi/spapr_vscsi.c +++ b/hw/scsi/spapr_vscsi.c @@ -75,20 +75,19 @@ typedef struct vscsi_req { /* SCSI request tracking */ SCSIRequest *sreq; uint32_t qtag; /* qemu tag != srp tag */ - int lun; - int active; - long data_len; - int writing; - int senselen; + bool active; + uint32_t data_len; + bool writing; + uint32_t senselen; uint8_t sense[SCSI_SENSE_BUF_SIZE]; /* RDMA related bits */ uint8_t dma_fmt; - struct srp_direct_buf ext_desc; - struct srp_direct_buf *cur_desc; - struct srp_indirect_buf *ind_desc; - int local_desc; - int total_desc; + uint16_t local_desc; + uint16_t total_desc; + uint16_t cdb_offset; + uint16_t cur_desc_num; + uint16_t cur_desc_offset; } vscsi_req; #define TYPE_VIO_SPAPR_VSCSI_DEVICE "spapr-vscsi" @@ -217,6 +216,7 @@ static int vscsi_send_rsp(VSCSIState *s, vscsi_req *req, union viosrp_iu *iu = &req->iu; uint64_t tag = iu->srp.rsp.tag; int total_len = sizeof(iu->srp.rsp); + uint8_t sol_not = iu->srp.cmd.sol_not; dprintf("VSCSI: Sending resp status: 0x%x, " "res_in: %d, res_out: %d\n", status, res_in, res_out); @@ -249,7 +249,7 @@ static int vscsi_send_rsp(VSCSIState *s, vscsi_req *req, /* Handle success vs. failure */ iu->srp.rsp.status = status; if (status) { - iu->srp.rsp.sol_not = (iu->srp.cmd.sol_not & 0x04) >> 2; + iu->srp.rsp.sol_not = (sol_not & 0x04) >> 2; if (req->senselen) { req->iu.srp.rsp.flags |= SRP_RSP_FLAG_SNSVALID; req->iu.srp.rsp.sense_data_len = cpu_to_be32(req->senselen); @@ -257,100 +257,145 @@ static int vscsi_send_rsp(VSCSIState *s, vscsi_req *req, total_len += req->senselen; } } else { - iu->srp.rsp.sol_not = (iu->srp.cmd.sol_not & 0x02) >> 1; + iu->srp.rsp.sol_not = (sol_not & 0x02) >> 1; } vscsi_send_iu(s, req, total_len, VIOSRP_SRP_FORMAT); return 0; } -static inline void vscsi_swap_desc(struct srp_direct_buf *desc) +static inline struct srp_direct_buf vscsi_swap_desc(struct srp_direct_buf desc) { - desc->va = be64_to_cpu(desc->va); - desc->len = be32_to_cpu(desc->len); + desc.va = be64_to_cpu(desc.va); + desc.len = be32_to_cpu(desc.len); + return desc; +} + +static int vscsi_fetch_desc(VSCSIState *s, struct vscsi_req *req, + unsigned n, unsigned buf_offset, + struct srp_direct_buf *ret) +{ + struct srp_cmd *cmd = &req->iu.srp.cmd; + + switch (req->dma_fmt) { + case SRP_NO_DATA_DESC: { + dprintf("VSCSI: no data descriptor\n"); + return 0; + } + case SRP_DATA_DESC_DIRECT: { + memcpy(ret, cmd->add_data + req->cdb_offset, sizeof(*ret)); + assert(req->cur_desc_num == 0); + dprintf("VSCSI: direct segment\n"); + break; + } + case SRP_DATA_DESC_INDIRECT: { + struct srp_indirect_buf *tmp = (struct srp_indirect_buf *) + (cmd->add_data + req->cdb_offset); + if (n < req->local_desc) { + *ret = tmp->desc_list[n]; + dprintf("VSCSI: indirect segment local tag=0x%x desc#%d/%d\n", + req->qtag, n, req->local_desc); + + } else if (n < req->total_desc) { + int rc; + struct srp_direct_buf tbl_desc = vscsi_swap_desc(tmp->table_desc); + unsigned desc_offset = n * sizeof(struct srp_direct_buf); + + if (desc_offset >= tbl_desc.len) { + dprintf("VSCSI: #%d is ouf of range (%d bytes)\n", + n, desc_offset); + return -1; + } + rc = spapr_vio_dma_read(&s->vdev, tbl_desc.va + desc_offset, + ret, sizeof(struct srp_direct_buf)); + if (rc) { + dprintf("VSCSI: spapr_vio_dma_read -> %d reading ext_desc\n", + rc); + return -1; + } + dprintf("VSCSI: indirect segment ext. tag=0x%x desc#%d/%d { va=%"PRIx64" len=%x }\n", + req->qtag, n, req->total_desc, tbl_desc.va, tbl_desc.len); + } else { + dprintf("VSCSI: Out of descriptors !\n"); + return 0; + } + break; + } + default: + fprintf(stderr, "VSCSI: Unknown format %x\n", req->dma_fmt); + return -1; + } + + *ret = vscsi_swap_desc(*ret); + if (buf_offset > ret->len) { + dprintf(" offset=%x is out of a descriptor #%d boundary=%x\n", + buf_offset, req->cur_desc_num, ret->len); + return -1; + } + ret->va += buf_offset; + ret->len -= buf_offset; + + dprintf(" cur=%d offs=%x ret { va=%"PRIx64" len=%x }\n", + req->cur_desc_num, req->cur_desc_offset, ret->va, ret->len); + + return ret->len ? 1 : 0; } static int vscsi_srp_direct_data(VSCSIState *s, vscsi_req *req, uint8_t *buf, uint32_t len) { - struct srp_direct_buf *md = req->cur_desc; + struct srp_direct_buf md; uint32_t llen; int rc = 0; - dprintf("VSCSI: direct segment 0x%x bytes, va=0x%llx desc len=0x%x\n", - len, (unsigned long long)md->va, md->len); + rc = vscsi_fetch_desc(s, req, req->cur_desc_num, req->cur_desc_offset, &md); + if (rc < 0) { + return -1; + } else if (rc == 0) { + return 0; + } - llen = MIN(len, md->len); + llen = MIN(len, md.len); if (llen) { if (req->writing) { /* writing = to device = reading from memory */ - rc = spapr_vio_dma_read(&s->vdev, md->va, buf, llen); + rc = spapr_vio_dma_read(&s->vdev, md.va, buf, llen); } else { - rc = spapr_vio_dma_write(&s->vdev, md->va, buf, llen); + rc = spapr_vio_dma_write(&s->vdev, md.va, buf, llen); } } - md->len -= llen; - md->va += llen; if (rc) { return -1; } + req->cur_desc_offset += llen; + return llen; } static int vscsi_srp_indirect_data(VSCSIState *s, vscsi_req *req, uint8_t *buf, uint32_t len) { - struct srp_direct_buf *td = &req->ind_desc->table_desc; - struct srp_direct_buf *md = req->cur_desc; + struct srp_direct_buf md; int rc = 0; uint32_t llen, total = 0; - dprintf("VSCSI: indirect segment 0x%x bytes, td va=0x%llx len=0x%x\n", - len, (unsigned long long)td->va, td->len); + dprintf("VSCSI: indirect segment 0x%x bytes\n", len); /* While we have data ... */ while (len) { - /* If we have a descriptor but it's empty, go fetch a new one */ - if (md && md->len == 0) { - /* More local available, use one */ - if (req->local_desc) { - md = ++req->cur_desc; - --req->local_desc; - --req->total_desc; - td->va += sizeof(struct srp_direct_buf); - } else { - md = req->cur_desc = NULL; - } - } - /* No descriptor at hand, fetch one */ - if (!md) { - if (!req->total_desc) { - dprintf("VSCSI: Out of descriptors !\n"); - break; - } - md = req->cur_desc = &req->ext_desc; - dprintf("VSCSI: Reading desc from 0x%llx\n", - (unsigned long long)td->va); - rc = spapr_vio_dma_read(&s->vdev, td->va, md, - sizeof(struct srp_direct_buf)); - if (rc) { - dprintf("VSCSI: spapr_vio_dma_read -> %d reading ext_desc\n", - rc); - break; - } - vscsi_swap_desc(md); - td->va += sizeof(struct srp_direct_buf); - --req->total_desc; + rc = vscsi_fetch_desc(s, req, req->cur_desc_num, req->cur_desc_offset, &md); + if (rc < 0) { + return -1; + } else if (rc == 0) { + break; } - dprintf("VSCSI: [desc va=0x%llx,len=0x%x] remaining=0x%x\n", - (unsigned long long)md->va, md->len, len); /* Perform transfer */ - llen = MIN(len, md->len); + llen = MIN(len, md.len); if (req->writing) { /* writing = to device = reading from memory */ - rc = spapr_vio_dma_read(&s->vdev, md->va, buf, llen); + rc = spapr_vio_dma_read(&s->vdev, md.va, buf, llen); } else { - rc = spapr_vio_dma_write(&s->vdev, md->va, buf, llen); + rc = spapr_vio_dma_write(&s->vdev, md.va, buf, llen); } if (rc) { dprintf("VSCSI: spapr_vio_dma_r/w(%d) -> %d\n", req->writing, rc); @@ -361,10 +406,18 @@ static int vscsi_srp_indirect_data(VSCSIState *s, vscsi_req *req, len -= llen; buf += llen; + total += llen; - md->va += llen; - md->len -= llen; + + /* Update current position in the current descriptor */ + req->cur_desc_offset += llen; + if (md.len == llen) { + /* Go to the next descriptor if the current one finished */ + ++req->cur_desc_num; + req->cur_desc_offset = 0; + } } + return rc ? -1 : total; } @@ -412,14 +465,13 @@ static int data_out_desc_size(struct srp_cmd *cmd) static int vscsi_preprocess_desc(vscsi_req *req) { struct srp_cmd *cmd = &req->iu.srp.cmd; - int offset, i; - offset = cmd->add_cdb_len & ~3; + req->cdb_offset = cmd->add_cdb_len & ~3; if (req->writing) { req->dma_fmt = cmd->buf_fmt >> 4; } else { - offset += data_out_desc_size(cmd); + req->cdb_offset += data_out_desc_size(cmd); req->dma_fmt = cmd->buf_fmt & ((1U << 4) - 1); } @@ -427,31 +479,18 @@ static int vscsi_preprocess_desc(vscsi_req *req) case SRP_NO_DATA_DESC: break; case SRP_DATA_DESC_DIRECT: - req->cur_desc = (struct srp_direct_buf *)(cmd->add_data + offset); req->total_desc = req->local_desc = 1; - vscsi_swap_desc(req->cur_desc); - dprintf("VSCSI: using direct RDMA %s, 0x%x bytes MD: 0x%llx\n", - req->writing ? "write" : "read", - req->cur_desc->len, (unsigned long long)req->cur_desc->va); break; - case SRP_DATA_DESC_INDIRECT: - req->ind_desc = (struct srp_indirect_buf *)(cmd->add_data + offset); - vscsi_swap_desc(&req->ind_desc->table_desc); - req->total_desc = req->ind_desc->table_desc.len / - sizeof(struct srp_direct_buf); + case SRP_DATA_DESC_INDIRECT: { + struct srp_indirect_buf *ind_tmp = (struct srp_indirect_buf *) + (cmd->add_data + req->cdb_offset); + + req->total_desc = be32_to_cpu(ind_tmp->table_desc.len) / + sizeof(struct srp_direct_buf); req->local_desc = req->writing ? cmd->data_out_desc_cnt : - cmd->data_in_desc_cnt; - for (i = 0; i < req->local_desc; i++) { - vscsi_swap_desc(&req->ind_desc->desc_list[i]); - } - req->cur_desc = req->local_desc ? &req->ind_desc->desc_list[0] : NULL; - dprintf("VSCSI: using indirect RDMA %s, 0x%x bytes %d descs " - "(%d local) VA: 0x%llx\n", - req->writing ? "read" : "write", - be32_to_cpu(req->ind_desc->len), - req->total_desc, req->local_desc, - (unsigned long long)req->ind_desc->table_desc.va); + cmd->data_in_desc_cnt; break; + } default: fprintf(stderr, "vscsi_preprocess_desc: Unknown format %x\n", req->dma_fmt); @@ -499,8 +538,8 @@ static void vscsi_command_complete(SCSIRequest *sreq, uint32_t status, size_t re vscsi_req *req = sreq->hba_private; int32_t res_in = 0, res_out = 0; - dprintf("VSCSI: SCSI cmd complete, r=0x%x tag=0x%x status=0x%x, req=%p\n", - reason, sreq->tag, status, req); + dprintf("VSCSI: SCSI cmd complete, tag=0x%x status=0x%x, req=%p\n", + sreq->tag, status, req); if (req == NULL) { fprintf(stderr, "VSCSI: Can't find request for tag 0x%x\n", sreq->tag); return; @@ -509,7 +548,7 @@ static void vscsi_command_complete(SCSIRequest *sreq, uint32_t status, size_t re if (status == CHECK_CONDITION) { req->senselen = scsi_req_get_sense(req->sreq, req->sense, sizeof(req->sense)); - dprintf("VSCSI: Sense data, %d bytes:\n", len); + dprintf("VSCSI: Sense data, %d bytes:\n", req->senselen); dprintf(" %02x %02x %02x %02x %02x %02x %02x %02x\n", req->sense[0], req->sense[1], req->sense[2], req->sense[3], req->sense[4], req->sense[5], req->sense[6], req->sense[7]); @@ -540,6 +579,69 @@ static void vscsi_request_cancelled(SCSIRequest *sreq) vscsi_put_req(req); } +static const VMStateDescription vmstate_spapr_vscsi_req = { + .name = "spapr_vscsi_req", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_BUFFER(crq.raw, vscsi_req), + VMSTATE_BUFFER(iu.srp.reserved, vscsi_req), + VMSTATE_UINT32(qtag, vscsi_req), + VMSTATE_BOOL(active, vscsi_req), + VMSTATE_UINT32(data_len, vscsi_req), + VMSTATE_BOOL(writing, vscsi_req), + VMSTATE_UINT32(senselen, vscsi_req), + VMSTATE_BUFFER(sense, vscsi_req), + VMSTATE_UINT8(dma_fmt, vscsi_req), + VMSTATE_UINT16(local_desc, vscsi_req), + VMSTATE_UINT16(total_desc, vscsi_req), + VMSTATE_UINT16(cdb_offset, vscsi_req), + /*Restart SCSI request from the beginning for now */ + /*VMSTATE_UINT16(cur_desc_num, vscsi_req), + VMSTATE_UINT16(cur_desc_offset, vscsi_req),*/ + VMSTATE_END_OF_LIST() + }, +}; + +static void vscsi_save_request(QEMUFile *f, SCSIRequest *sreq) +{ + vscsi_req *req = sreq->hba_private; + assert(req->active); + + vmstate_save_state(f, &vmstate_spapr_vscsi_req, req); + + dprintf("VSCSI: saving tag=%u, current desc#%d, offset=%x\n", + req->qtag, req->cur_desc_num, req->cur_desc_offset); +} + +static void *vscsi_load_request(QEMUFile *f, SCSIRequest *sreq) +{ + SCSIBus *bus = sreq->bus; + VSCSIState *s = VIO_SPAPR_VSCSI_DEVICE(bus->qbus.parent); + vscsi_req *req; + int rc; + + assert(sreq->tag < VSCSI_REQ_LIMIT); + req = &s->reqs[sreq->tag]; + assert(!req->active); + + memset(req, 0, sizeof(*req)); + rc = vmstate_load_state(f, &vmstate_spapr_vscsi_req, req, 1); + if (rc) { + fprintf(stderr, "VSCSI: failed loading request tag#%u\n", sreq->tag); + return NULL; + } + assert(req->active); + + req->sreq = scsi_req_ref(sreq); + + dprintf("VSCSI: restoring tag=%u, current desc#%d, offset=%x\n", + req->qtag, req->cur_desc_num, req->cur_desc_offset); + + return req; +} + static void vscsi_process_login(VSCSIState *s, vscsi_req *req) { union viosrp_iu *iu = &req->iu; @@ -621,12 +723,11 @@ static int vscsi_queue_cmd(VSCSIState *s, vscsi_req *req) } return 1; } - req->lun = lun; req->sreq = scsi_req_new(sdev, req->qtag, lun, srp->cmd.cdb, req); n = scsi_req_enqueue(req->sreq); - dprintf("VSCSI: Queued command tag 0x%x CMD 0x%x ID %d LUN %d ret: %d\n", - req->qtag, srp->cmd.cdb[0], id, lun, n); + dprintf("VSCSI: Queued command tag 0x%x CMD 0x%x LUN %d ret: %d\n", + req->qtag, srp->cmd.cdb[0], lun, n); if (n) { /* Transfer direction must be set before preprocessing the @@ -895,7 +996,9 @@ static const struct SCSIBusInfo vscsi_scsi_info = { .transfer_data = vscsi_transfer_data, .complete = vscsi_command_complete, - .cancel = vscsi_request_cancelled + .cancel = vscsi_request_cancelled, + .save_request = vscsi_save_request, + .load_request = vscsi_load_request, }; static void spapr_vscsi_reset(VIOsPAPRDevice *dev) @@ -959,6 +1062,20 @@ static Property spapr_vscsi_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static const VMStateDescription vmstate_spapr_vscsi = { + .name = "spapr_vscsi", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_SPAPR_VIO(vdev, VSCSIState), + /* VSCSI state */ + /* ???? */ + + VMSTATE_END_OF_LIST() + }, +}; + static void spapr_vscsi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -973,6 +1090,7 @@ static void spapr_vscsi_class_init(ObjectClass *klass, void *data) k->signal_mask = 0x00000001; dc->props = spapr_vscsi_properties; k->rtce_window_size = 0x10000000; + dc->vmsd = &vmstate_spapr_vscsi; } static const TypeInfo spapr_vscsi_info = { diff --git a/hw/scsi/vhost-scsi.c b/hw/scsi/vhost-scsi.c index 785e93f545..9e770fba98 100644 --- a/hw/scsi/vhost-scsi.c +++ b/hw/scsi/vhost-scsi.c @@ -267,6 +267,7 @@ static void vhost_scsi_class_init(ObjectClass *klass, void *data) VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); dc->exit = vhost_scsi_exit; dc->props = vhost_scsi_properties; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); vdc->init = vhost_scsi_init; vdc->get_features = vhost_scsi_get_features; vdc->set_config = vhost_scsi_set_config; diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c index 42cb73bb4e..05da56bd24 100644 --- a/hw/scsi/virtio-scsi.c +++ b/hw/scsi/virtio-scsi.c @@ -669,8 +669,10 @@ static Property virtio_scsi_properties[] = { static void virtio_scsi_common_class_init(ObjectClass *klass, void *data) { VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); vdc->get_config = virtio_scsi_get_config; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static void virtio_scsi_class_init(ObjectClass *klass, void *data) @@ -679,6 +681,7 @@ static void virtio_scsi_class_init(ObjectClass *klass, void *data) VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); dc->exit = virtio_scsi_device_exit; dc->props = virtio_scsi_properties; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); vdc->init = virtio_scsi_device_init; vdc->set_config = virtio_scsi_set_config; vdc->get_features = virtio_scsi_get_features; diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index e1074e1d8d..d42b35941b 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -1197,6 +1197,7 @@ static void pvscsi_class_init(ObjectClass *klass, void *data) dc->reset = pvscsi_reset; dc->vmsd = &vmstate_pvscsi; dc->props = pvscsi_properties; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); k->config_write = pvscsi_write_config; } diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 7a0c1ab776..5c7bd31e62 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -66,6 +66,8 @@ #define PROM_FILENAME "openbios-sparc32" #define CFG_ADDR 0xd00000510ULL #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) +#define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) +#define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) #define MAX_CPUS 16 #define MAX_PILS 16 @@ -991,6 +993,8 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); + fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); + fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); if (kernel_cmdline) { diff --git a/hw/usb/ccid-card-emulated.c b/hw/usb/ccid-card-emulated.c index deb6d4703b..aa913df853 100644 --- a/hw/usb/ccid-card-emulated.c +++ b/hw/usb/ccid-card-emulated.c @@ -592,6 +592,7 @@ static void emulated_class_initfn(ObjectClass *klass, void *data) cc->exitfn = emulated_exitfn; cc->get_atr = emulated_get_atr; cc->apdu_from_guest = emulated_apdu_from_guest; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); dc->desc = "emulated smartcard"; dc->props = emulated_card_properties; } diff --git a/hw/usb/ccid-card-passthru.c b/hw/usb/ccid-card-passthru.c index 5f01ff1e16..10f1d309a6 100644 --- a/hw/usb/ccid-card-passthru.c +++ b/hw/usb/ccid-card-passthru.c @@ -392,6 +392,7 @@ static void passthru_class_initfn(ObjectClass *klass, void *data) cc->exitfn = passthru_exitfn; cc->get_atr = passthru_get_atr; cc->apdu_from_guest = passthru_apdu_from_guest; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); dc->desc = "passthrough smartcard"; dc->vmsd = &passthru_vmstate; dc->props = passthru_card_properties; diff --git a/hw/usb/dev-audio.c b/hw/usb/dev-audio.c index 04933a985a..c5420eb057 100644 --- a/hw/usb/dev-audio.c +++ b/hw/usb/dev-audio.c @@ -673,6 +673,7 @@ static void usb_audio_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_usb_audio; dc->props = usb_audio_properties; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); k->product_desc = "QEMU USB Audio Interface"; k->usb_desc = &desc_audio; k->init = usb_audio_initfn; diff --git a/hw/usb/dev-bluetooth.c b/hw/usb/dev-bluetooth.c index 68cc1d4fab..f2fc2a8034 100644 --- a/hw/usb/dev-bluetooth.c +++ b/hw/usb/dev-bluetooth.c @@ -553,6 +553,7 @@ static void usb_bt_class_initfn(ObjectClass *klass, void *data) uc->handle_data = usb_bt_handle_data; uc->handle_destroy = usb_bt_handle_destroy; dc->vmsd = &vmstate_usb_bt; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); } static const TypeInfo bt_info = { diff --git a/hw/usb/dev-hid.c b/hw/usb/dev-hid.c index 31f3cdef42..66c63317d6 100644 --- a/hw/usb/dev-hid.c +++ b/hw/usb/dev-hid.c @@ -658,6 +658,7 @@ static void usb_tablet_class_initfn(ObjectClass *klass, void *data) uc->product_desc = "QEMU USB Tablet"; dc->vmsd = &vmstate_usb_ptr; dc->props = usb_tablet_properties; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo usb_tablet_info = { @@ -677,6 +678,7 @@ static void usb_mouse_class_initfn(ObjectClass *klass, void *data) uc->product_desc = "QEMU USB Mouse"; uc->usb_desc = &desc_mouse; dc->vmsd = &vmstate_usb_ptr; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } static const TypeInfo usb_mouse_info = { @@ -696,6 +698,7 @@ static void usb_keyboard_class_initfn(ObjectClass *klass, void *data) uc->product_desc = "QEMU USB Keyboard"; uc->usb_desc = &desc_keyboard; dc->vmsd = &vmstate_usb_kbd; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } static const TypeInfo usb_keyboard_info = { diff --git a/hw/usb/dev-hub.c b/hw/usb/dev-hub.c index 0b71abd028..e865a98751 100644 --- a/hw/usb/dev-hub.c +++ b/hw/usb/dev-hub.c @@ -574,6 +574,7 @@ static void usb_hub_class_initfn(ObjectClass *klass, void *data) uc->handle_control = usb_hub_handle_control; uc->handle_data = usb_hub_handle_data; uc->handle_destroy = usb_hub_handle_destroy; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->fw_name = "hub"; dc->vmsd = &vmstate_usb_hub; } diff --git a/hw/usb/dev-network.c b/hw/usb/dev-network.c index 5473ac2cd5..660d7743fe 100644 --- a/hw/usb/dev-network.c +++ b/hw/usb/dev-network.c @@ -1429,6 +1429,7 @@ static void usb_net_class_initfn(ObjectClass *klass, void *data) uc->handle_control = usb_net_handle_control; uc->handle_data = usb_net_handle_data; uc->handle_destroy = usb_net_handle_destroy; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); dc->fw_name = "network"; dc->vmsd = &vmstate_usb_net; dc->props = net_properties; diff --git a/hw/usb/dev-serial.c b/hw/usb/dev-serial.c index 2fc8a3b136..0b150d43fb 100644 --- a/hw/usb/dev-serial.c +++ b/hw/usb/dev-serial.c @@ -590,6 +590,7 @@ static void usb_serial_class_initfn(ObjectClass *klass, void *data) uc->handle_data = usb_serial_handle_data; dc->vmsd = &vmstate_usb_serial; dc->props = serial_properties; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } static const TypeInfo serial_info = { @@ -617,6 +618,7 @@ static void usb_braille_class_initfn(ObjectClass *klass, void *data) uc->handle_data = usb_serial_handle_data; dc->vmsd = &vmstate_usb_serial; dc->props = braille_properties; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } static const TypeInfo braille_info = { diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-reader.c index b33eb25b39..2233c548fa 100644 --- a/hw/usb/dev-smartcard-reader.c +++ b/hw/usb/dev-smartcard-reader.c @@ -1449,6 +1449,7 @@ static void ccid_class_initfn(ObjectClass *klass, void *data) dc->desc = "CCID Rev 1.1 smartcard reader"; dc->vmsd = &ccid_vmstate; dc->props = ccid_properties; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } static const TypeInfo ccid_info = { diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c index 1954811ec4..a8dc2fa960 100644 --- a/hw/usb/dev-storage.c +++ b/hw/usb/dev-storage.c @@ -746,6 +746,7 @@ static void usb_msd_class_initfn_common(ObjectClass *klass) uc->handle_reset = usb_msd_handle_reset; uc->handle_control = usb_msd_handle_control; uc->handle_data = usb_msd_handle_data; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->fw_name = "storage"; dc->vmsd = &vmstate_usb_msd; } diff --git a/hw/usb/dev-uas.c b/hw/usb/dev-uas.c index 6efab62544..63ad12ea6b 100644 --- a/hw/usb/dev-uas.c +++ b/hw/usb/dev-uas.c @@ -916,6 +916,7 @@ static void usb_uas_class_initfn(ObjectClass *klass, void *data) uc->handle_control = usb_uas_handle_control; uc->handle_data = usb_uas_handle_data; uc->handle_destroy = usb_uas_handle_destroy; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->fw_name = "storage"; dc->vmsd = &vmstate_usb_uas; } diff --git a/hw/usb/dev-wacom.c b/hw/usb/dev-wacom.c index 3be5cdefda..1b092358f9 100644 --- a/hw/usb/dev-wacom.c +++ b/hw/usb/dev-wacom.c @@ -362,6 +362,7 @@ static void usb_wacom_class_init(ObjectClass *klass, void *data) uc->handle_control = usb_wacom_handle_control; uc->handle_data = usb_wacom_handle_data; uc->handle_destroy = usb_wacom_handle_destroy; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); dc->desc = "QEMU PenPartner Tablet"; dc->vmsd = &vmstate_usb_wacom; } diff --git a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c index 5d229bc792..4d21a0b7bb 100644 --- a/hw/usb/hcd-ehci-pci.c +++ b/hw/usb/hcd-ehci-pci.c @@ -140,11 +140,13 @@ static const TypeInfo ehci_pci_type_info = { static void ehci_data_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); EHCIPCIInfo *i = data; k->vendor_id = i->vendor_id; k->device_id = i->device_id; k->revision = i->revision; + set_bit(DEVICE_CATEGORY_USB, dc->categories); } static struct EHCIPCIInfo ehci_pci_info[] = { diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index 54147b5fee..fe6eea5908 100644 --- a/hw/usb/hcd-ehci-sysbus.c +++ b/hw/usb/hcd-ehci-sysbus.c @@ -70,6 +70,7 @@ static void ehci_sysbus_class_init(ObjectClass *klass, void *data) dc->realize = usb_ehci_sysbus_realize; dc->vmsd = &vmstate_ehci_sysbus; dc->props = ehci_sysbus_properties; + set_bit(DEVICE_CATEGORY_USB, dc->categories); } static const TypeInfo ehci_type_info = { @@ -85,7 +86,9 @@ static const TypeInfo ehci_type_info = { static void ehci_xlnx_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); + set_bit(DEVICE_CATEGORY_USB, dc->categories); sec->capsbase = 0x100; sec->opregbase = 0x140; } @@ -99,9 +102,11 @@ static const TypeInfo ehci_xlnx_type_info = { static void ehci_exynos4210_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); sec->capsbase = 0x0; sec->opregbase = 0x10; + set_bit(DEVICE_CATEGORY_USB, dc->categories); } static const TypeInfo ehci_exynos4210_type_info = { @@ -113,9 +118,11 @@ static const TypeInfo ehci_exynos4210_type_info = { static void ehci_tegra2_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); sec->capsbase = 0x100; sec->opregbase = 0x140; + set_bit(DEVICE_CATEGORY_USB, dc->categories); } static const TypeInfo ehci_tegra2_type_info = { @@ -183,11 +190,13 @@ static void fusbh200_ehci_init(Object *obj) static void fusbh200_ehci_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); sec->capsbase = 0x0; sec->opregbase = 0x10; sec->portscbase = 0x20; sec->portnr = 1; + set_bit(DEVICE_CATEGORY_USB, dc->categories); } static const TypeInfo ehci_fusbh200_type_info = { diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index 67e4b24273..010a0d0d32 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -1357,7 +1357,7 @@ static void ehci_execute_complete(EHCIQueue *q) default: /* should not be triggerable */ fprintf(stderr, "USB invalid response %d\n", p->packet.status); - assert(0); + g_assert_not_reached(); break; } @@ -2142,7 +2142,7 @@ static void ehci_advance_state(EHCIState *ehci, int async) default: fprintf(stderr, "Bad state!\n"); again = -1; - assert(0); + g_assert_not_reached(); break; } @@ -2206,7 +2206,7 @@ static void ehci_advance_async_state(EHCIState *ehci) /* this should only be due to a developer mistake */ fprintf(stderr, "ehci: Bad asynchronous state %d. " "Resetting to active\n", ehci->astate); - assert(0); + g_assert_not_reached(); } } @@ -2256,7 +2256,7 @@ static void ehci_advance_periodic_state(EHCIState *ehci) /* this should only be due to a developer mistake */ fprintf(stderr, "ehci: Bad periodic state %d. " "Resetting to active\n", ehci->pstate); - assert(0); + g_assert_not_reached(); } } diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index 2bab8ffb75..d438d648b3 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -1917,6 +1917,7 @@ static void ohci_pci_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB; k->class_id = PCI_CLASS_SERIAL_USB; k->no_hotplug = 1; + set_bit(DEVICE_CATEGORY_USB, dc->categories); dc->desc = "Apple USB Controller"; dc->props = ohci_pci_properties; } @@ -1939,6 +1940,7 @@ static void ohci_sysbus_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = ohci_realize_pxa; + set_bit(DEVICE_CATEGORY_USB, dc->categories); dc->desc = "OHCI USB Controller"; dc->props = ohci_sysbus_properties; } diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index 066072eb3f..cb44abc7bc 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -1315,6 +1315,7 @@ static void uhci_class_init(ObjectClass *klass, void *data) k->no_hotplug = 1; dc->vmsd = &vmstate_uhci; dc->props = uhci_properties; + set_bit(DEVICE_CATEGORY_USB, dc->categories); u->info = *info; } diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 9ba3e3e86d..58f311db0f 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -3591,6 +3591,7 @@ static void xhci_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_xhci; dc->props = xhci_properties; dc->reset = xhci_reset; + set_bit(DEVICE_CATEGORY_USB, dc->categories); k->init = usb_xhci_initfn; k->vendor_id = PCI_VENDOR_ID_NEC; k->device_id = PCI_DEVICE_ID_NEC_UPD720200; diff --git a/hw/usb/host-libusb.c b/hw/usb/host-libusb.c index e2f3cc8ade..f660770076 100644 --- a/hw/usb/host-libusb.c +++ b/hw/usb/host-libusb.c @@ -1351,6 +1351,7 @@ static void usb_host_class_initfn(ObjectClass *klass, void *data) uc->flush_ep_queue = usb_host_flush_ep_queue; dc->vmsd = &vmstate_usb_host; dc->props = usb_host_dev_properties; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } static TypeInfo usb_host_dev_info = { diff --git a/hw/usb/host-linux.c b/hw/usb/host-linux.c index ca09a891ee..7901f4c01a 100644 --- a/hw/usb/host-linux.c +++ b/hw/usb/host-linux.c @@ -1530,6 +1530,7 @@ static void usb_host_class_initfn(ObjectClass *klass, void *data) uc->handle_destroy = usb_host_handle_destroy; dc->vmsd = &vmstate_usb_host; dc->props = usb_host_dev_properties; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } static const TypeInfo usb_host_dev_info = { diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index a594e954e4..8b8c010d94 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -2362,6 +2362,7 @@ static void usbredir_class_initfn(ObjectClass *klass, void *data) uc->ep_stopped = usbredir_ep_stopped; dc->vmsd = &usbredir_vmstate; dc->props = usbredir_properties; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo usbredir_dev_info = { diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c index 3fa72a97b9..aac7f83ccf 100644 --- a/hw/virtio/virtio-balloon.c +++ b/hw/virtio/virtio-balloon.c @@ -53,8 +53,8 @@ static const char *balloon_stat_names[] = { /* * reset_stats - Mark all items in the stats array as unset * - * This function needs to be called at device intialization and before - * before updating to a set of newly-generated stats. This will ensure that no + * This function needs to be called at device initialization and before + * updating to a set of newly-generated stats. This will ensure that no * stale values stick around in case the guest reports a subset of the supported * statistics. */ @@ -392,6 +392,7 @@ static void virtio_balloon_class_init(ObjectClass *klass, void *data) VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); dc->exit = virtio_balloon_device_exit; dc->props = virtio_balloon_properties; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); vdc->init = virtio_balloon_device_init; vdc->get_config = virtio_balloon_get_config; vdc->set_config = virtio_balloon_set_config; diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index 54d6679516..88cf994b97 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -370,6 +370,7 @@ static void virtio_mmio_class_init(ObjectClass *klass, void *data) dc->realize = virtio_mmio_realizefn; dc->reset = virtio_mmio_reset; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo virtio_mmio_info = { diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index c38cfd1515..d37037ef17 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -911,6 +911,7 @@ static void virtio_9p_pci_class_init(ObjectClass *klass, void *data) pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_9P; pcidev_k->revision = VIRTIO_PCI_ABI_VERSION; pcidev_k->class_id = 0x2; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->props = virtio_9p_pci_properties; } @@ -1065,6 +1066,7 @@ static void virtio_blk_pci_class_init(ObjectClass *klass, void *data) VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass); PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->props = virtio_blk_pci_properties; k->init = virtio_blk_pci_init; pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; @@ -1135,6 +1137,7 @@ static void virtio_scsi_pci_class_init(ObjectClass *klass, void *data) VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass); PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); k->init = virtio_scsi_pci_init_pci; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->props = virtio_scsi_pci_properties; pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI; @@ -1191,6 +1194,7 @@ static void vhost_scsi_pci_class_init(ObjectClass *klass, void *data) VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass); PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); k->init = vhost_scsi_pci_init_pci; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->props = vhost_scsi_pci_properties; pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI; @@ -1271,6 +1275,7 @@ static void virtio_balloon_pci_class_init(ObjectClass *klass, void *data) VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass); PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); k->init = virtio_balloon_pci_init; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->props = virtio_balloon_pci_properties; pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BALLOON; @@ -1356,6 +1361,7 @@ static void virtio_serial_pci_class_init(ObjectClass *klass, void *data) VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass); PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); k->init = virtio_serial_pci_init; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); dc->props = virtio_serial_pci_properties; pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_CONSOLE; @@ -1417,6 +1423,7 @@ static void virtio_net_pci_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_VIRTIO_NET; k->revision = VIRTIO_PCI_ABI_VERSION; k->class_id = PCI_CLASS_NETWORK_ETHERNET; + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); dc->props = virtio_net_properties; vpciklass->init = virtio_net_pci_init; } @@ -1468,6 +1475,7 @@ static void virtio_rng_pci_class_init(ObjectClass *klass, void *data) PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); k->init = virtio_rng_pci_init; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->props = virtio_rng_pci_properties; pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; diff --git a/hw/virtio/virtio-rng.c b/hw/virtio/virtio-rng.c index cb787c792d..bac8421a20 100644 --- a/hw/virtio/virtio-rng.c +++ b/hw/virtio/virtio-rng.c @@ -207,6 +207,7 @@ static void virtio_rng_class_init(ObjectClass *klass, void *data) VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); dc->exit = virtio_rng_device_exit; dc->props = virtio_rng_properties; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); vdc->init = virtio_rng_device_init; vdc->get_features = get_features; } diff --git a/hw/watchdog/watchdog.c b/hw/watchdog/watchdog.c index cb4e1f9e47..387962ec4a 100644 --- a/hw/watchdog/watchdog.c +++ b/hw/watchdog/watchdog.c @@ -128,7 +128,6 @@ void watchdog_perform_action(void) case WDT_POWEROFF: /* same as 'quit' command in monitor */ watchdog_mon_event("poweroff"); exit(0); - break; case WDT_PAUSE: /* same as 'stop' command in monitor */ watchdog_mon_event("pause"); diff --git a/hw/watchdog/wdt_i6300esb.c b/hw/watchdog/wdt_i6300esb.c index 85aebc28a3..2e064bac81 100644 --- a/hw/watchdog/wdt_i6300esb.c +++ b/hw/watchdog/wdt_i6300esb.c @@ -451,6 +451,7 @@ static void i6300esb_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_SYSTEM_OTHER; dc->reset = i6300esb_reset; dc->vmsd = &vmstate_i6300esb; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo i6300esb_info = { diff --git a/hw/watchdog/wdt_ib700.c b/hw/watchdog/wdt_ib700.c index c78855444c..e97b4c3049 100644 --- a/hw/watchdog/wdt_ib700.c +++ b/hw/watchdog/wdt_ib700.c @@ -137,6 +137,7 @@ static void wdt_ib700_class_init(ObjectClass *klass, void *data) dc->realize = wdt_ib700_realize; dc->reset = wdt_ib700_reset; dc->vmsd = &vmstate_ib700; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo wdt_ib700_info = { diff --git a/hw/xen/Makefile.objs b/hw/xen/Makefile.objs index 20175602b6..ce640c61a5 100644 --- a/hw/xen/Makefile.objs +++ b/hw/xen/Makefile.objs @@ -1,6 +1,6 @@ # xen backend driver support common-obj-$(CONFIG_XEN_BACKEND) += xen_backend.o xen_devconfig.o -obj-$(CONFIG_XEN_I386) += xen_platform.o xen_apic.o +obj-$(CONFIG_XEN_I386) += xen_platform.o xen_apic.o xen_pvdevice.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o diff --git a/hw/xen/xen_platform.c b/hw/xen/xen_platform.c index 6a8ba7e9aa..79bf0b33d3 100644 --- a/hw/xen/xen_platform.c +++ b/hw/xen/xen_platform.c @@ -428,6 +428,7 @@ static void xen_platform_class_init(ObjectClass *klass, void *data) k->subsystem_vendor_id = PCI_VENDOR_ID_XEN; k->subsystem_id = PCI_DEVICE_ID_XEN_PLATFORM; k->revision = 1; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->desc = "XEN platform pci device"; dc->reset = platform_reset; dc->vmsd = &vmstate_xen_platform; diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c index d7ee7745c8..ca2d460785 100644 --- a/hw/xen/xen_pt.c +++ b/hw/xen/xen_pt.c @@ -756,7 +756,8 @@ static int xen_pt_initfn(PCIDevice *d) out: memory_listener_register(&s->memory_listener, &address_space_memory); memory_listener_register(&s->io_listener, &address_space_io); - XEN_PT_LOG(d, "Real physical device %02x:%02x.%d registered successfuly!\n", + XEN_PT_LOG(d, + "Real physical device %02x:%02x.%d registered successfully!\n", s->hostaddr.bus, s->hostaddr.slot, s->hostaddr.function); return 0; @@ -829,6 +830,7 @@ static void xen_pci_passthrough_class_init(ObjectClass *klass, void *data) k->exit = xen_pt_unregister_device; k->config_read = xen_pt_pci_read_config; k->config_write = xen_pt_pci_write_config; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->desc = "Assign an host PCI device with Xen"; dc->props = xen_pci_passthrough_properties; }; diff --git a/hw/xen/xen_pvdevice.c b/hw/xen/xen_pvdevice.c new file mode 100644 index 0000000000..1132c8934f --- /dev/null +++ b/hw/xen/xen_pvdevice.c @@ -0,0 +1,131 @@ +/* Copyright (c) Citrix Systems Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, + * with or without modification, are permitted provided + * that the following conditions are met: + * + * * Redistributions of source code must retain the above + * copyright notice, this list of conditions and the + * following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "hw/hw.h" +#include "hw/pci/pci.h" +#include "trace.h" + +#define TYPE_XEN_PV_DEVICE "xen-pvdevice" + +#define XEN_PV_DEVICE(obj) \ + OBJECT_CHECK(XenPVDevice, (obj), TYPE_XEN_PV_DEVICE) + +typedef struct XenPVDevice { + /*< private >*/ + PCIDevice parent_obj; + /*< public >*/ + uint16_t vendor_id; + uint16_t device_id; + uint8_t revision; + uint32_t size; + MemoryRegion mmio; +} XenPVDevice; + +static uint64_t xen_pv_mmio_read(void *opaque, hwaddr addr, + unsigned size) +{ + trace_xen_pv_mmio_read(addr); + + return ~(uint64_t)0; +} + +static void xen_pv_mmio_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + trace_xen_pv_mmio_write(addr); +} + +static const MemoryRegionOps xen_pv_mmio_ops = { + .read = &xen_pv_mmio_read, + .write = &xen_pv_mmio_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static int xen_pv_init(PCIDevice *pci_dev) +{ + XenPVDevice *d = XEN_PV_DEVICE(pci_dev); + uint8_t *pci_conf; + + pci_conf = pci_dev->config; + + pci_set_word(pci_conf + PCI_VENDOR_ID, d->vendor_id); + pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, d->vendor_id); + pci_set_word(pci_conf + PCI_DEVICE_ID, d->device_id); + pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, d->device_id); + pci_set_byte(pci_conf + PCI_REVISION_ID, d->revision); + + pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_MEMORY); + + pci_config_set_prog_interface(pci_conf, 0); + + pci_conf[PCI_INTERRUPT_PIN] = 1; + + memory_region_init_io(&d->mmio, NULL, &xen_pv_mmio_ops, d, + "mmio", d->size); + + pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, + &d->mmio); + + return 0; +} + +static Property xen_pv_props[] = { + DEFINE_PROP_UINT16("vendor-id", XenPVDevice, vendor_id, PCI_VENDOR_ID_XEN), + DEFINE_PROP_UINT16("device-id", XenPVDevice, device_id, PCI_DEVICE_ID_XEN_PVDEVICE), + DEFINE_PROP_UINT8("revision", XenPVDevice, revision, 0x01), + DEFINE_PROP_UINT32("size", XenPVDevice, size, 0x400000), + DEFINE_PROP_END_OF_LIST() +}; + +static void xen_pv_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->init = xen_pv_init; + k->class_id = PCI_CLASS_SYSTEM_OTHER; + dc->desc = "Xen PV Device"; + dc->props = xen_pv_props; +} + +static const TypeInfo xen_pv_type_info = { + .name = TYPE_XEN_PV_DEVICE, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(XenPVDevice), + .class_init = xen_pv_class_init, +}; + +static void xen_pv_register_types(void) +{ + type_register_static(&xen_pv_type_info); +} + +type_init(xen_pv_register_types) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index b5b93db842..a5c028c536 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -154,8 +154,6 @@ typedef struct CPUWatchpoint { memory was accessed */ \ CPU_COMMON_TLB \ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ - /* buffer for temporaries in the code generator */ \ - long temp_buf[CPU_TEMP_BUF_NLONGS]; \ \ int64_t icount_extra; /* Instructions until next timer event. */ \ /* Number of cycles left, with interrupt flag in high bit. \ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b2162a4ec4..5920f73c90 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -358,6 +358,20 @@ static inline uintptr_t tcg_getpc_ldst(uintptr_t ra) not the start of the next opcode */ return ra; } +#elif defined(__aarch64__) +# define GETRA() ((uintptr_t)__builtin_return_address(0)) +# define GETPC_LDST() tcg_getpc_ldst(GETRA()) +static inline uintptr_t tcg_getpc_ldst(uintptr_t ra) +{ + int32_t b; + ra += 4; /* skip one instruction */ + b = *(int32_t *)ra; /* load the branch insn */ + b = (b << 6) >> (6 - 2); /* extract the displacement */ + ra += b; /* apply the displacement */ + ra -= 4; /* return a pointer into the current opcode, + not the start of the next opcode */ + return ra; +} # else # error "CONFIG_QEMU_LDST_OPTIMIZATION needs GETPC_LDST() implementation!" # endif diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index 7ea1ad7f9c..a608a26c30 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -39,6 +39,43 @@ static inline int cpu_index(CPUState *cpu) #endif } +/* The GDB remote protocol transfers values in target byte order. This means + * we can use the raw memory access routines to access the value buffer. + * Conveniently, these also handle the case where the buffer is mis-aligned. + */ + +static inline int gdb_get_reg8(uint8_t *mem_buf, uint8_t val) +{ + stb_p(mem_buf, val); + return 1; +} + +static inline int gdb_get_reg16(uint8_t *mem_buf, uint16_t val) +{ + stw_p(mem_buf, val); + return 2; +} + +static inline int gdb_get_reg32(uint8_t *mem_buf, uint32_t val) +{ + stl_p(mem_buf, val); + return 4; +} + +static inline int gdb_get_reg64(uint8_t *mem_buf, uint64_t val) +{ + stq_p(mem_buf, val); + return 8; +} + +#if TARGET_LONG_BITS == 64 +#define gdb_get_regl(buf, val) gdb_get_reg64(buf, val) +#define ldtul_p(addr) ldq_p(addr) +#else +#define gdb_get_regl(buf, val) gdb_get_reg32(buf, val) +#define ldtul_p(addr) ldl_p(addr) +#endif + #endif #ifdef CONFIG_USER_ONLY @@ -47,6 +84,14 @@ int gdbserver_start(int); int gdbserver_start(const char *port); #endif +/** + * gdb_has_xml: + * This is an ugly hack to cope with both new and old gdb. + * If gdb sends qXfer:features:read then assume we're talking to a newish + * gdb that understands target descriptions. + */ +extern bool gdb_has_xml; + /* in gdbstub-xml.c, generated by scripts/feature_to_c.sh */ extern const char *const xml_builtin[][2]; diff --git a/include/exec/poison.h b/include/exec/poison.h index 2341a75041..a4b1eca24f 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -36,7 +36,6 @@ #pragma GCC poison TARGET_PAGE_ALIGN #pragma GCC poison CPUArchState -#pragma GCC poison env #pragma GCC poison lduw_phys #pragma GCC poison ldl_phys diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 7fb97b08a2..09c2dd411b 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -235,6 +235,10 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t); .driver = "virtio-net-pci",\ .property = "any_layout",\ .value = "off",\ + },{\ + .driver = TYPE_X86_CPU,\ + .property = "pmu",\ + .value = "on",\ } #define PC_COMPAT_1_4 \ diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h index 291e85f6b9..2a7a9c9f42 100644 --- a/include/hw/mips/mips.h +++ b/include/hw/mips/mips.h @@ -2,6 +2,9 @@ #define HW_MIPS_H /* Definitions for mips board emulation. */ +/* Kernels can be configured with 64KB pages */ +#define INITRD_PAGE_MASK (~((1 << 16) - 1)) + #include "exec/memory.h" /* gt64xxx.c */ diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 1e23dbfb4a..93f9511325 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -52,14 +52,14 @@ typedef struct sPAPRPHBState { sPAPRTCETable *tcet; AddressSpace iommu_as; - struct { + struct spapr_pci_lsi { uint32_t irq; } lsi_table[PCI_NUM_PINS]; - struct { + struct spapr_pci_msi { uint32_t config_addr; uint32_t irq; - int nvec; + uint32_t nvec; } msi_table[SPAPR_MSIX_MAX_DEVS]; QLIST_ENTRY(sPAPRPHBState) list; diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index d7933bfd16..3ddaf6aad5 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -143,8 +143,9 @@ #define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0 -#define PCI_VENDOR_ID_XEN 0x5853 -#define PCI_DEVICE_ID_XEN_PLATFORM 0x0001 +#define PCI_VENDOR_ID_XEN 0x5853 +#define PCI_DEVICE_ID_XEN_PLATFORM 0x0001 +#define PCI_DEVICE_ID_XEN_PVDEVICE 0x0002 #define PCI_VENDOR_ID_NEC 0x1033 #define PCI_DEVICE_ID_NEC_UPD720200 0x0194 diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index de95480734..9fc197286c 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -7,30 +7,36 @@ struct VIOsPAPRBus; struct sPAPRPHBState; struct sPAPRNVRAM; -struct icp_state; + +#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL typedef struct sPAPREnvironment { struct VIOsPAPRBus *vio_bus; QLIST_HEAD(, sPAPRPHBState) phbs; struct sPAPRNVRAM *nvram; - struct icp_state *icp; + XICSState *icp; hwaddr ram_limit; void *htab; - long htab_shift; + uint32_t htab_shift; hwaddr rma_size; int vrma_adjust; hwaddr fdt_addr, rtas_addr; long rtas_size; void *fdt_skel; target_ulong entry_point; - int next_irq; - int rtc_offset; + uint32_t next_irq; + uint64_t rtc_offset; char *cpu_model; bool has_graphics; uint32_t epow_irq; Notifier epow_notifier; + + /* Migration state */ + int htab_save_index; + bool htab_first_pass; + int htab_fd; } sPAPREnvironment; #define H_SUCCESS 0 @@ -334,10 +340,6 @@ int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) -typedef struct sPAPRTCE { - uint64_t tce; -} sPAPRTCE; - #define SPAPR_VIO_BASE_LIOBN 0x00000000 #define SPAPR_PCI_BASE_LIOBN 0x80000000 @@ -345,14 +347,27 @@ typedef struct sPAPRTCE { typedef struct sPAPRTCETable sPAPRTCETable; -void spapr_iommu_init(void); +#define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" +#define SPAPR_TCE_TABLE(obj) \ + OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) + +struct sPAPRTCETable { + DeviceState parent; + uint32_t liobn; + uint32_t window_size; + uint32_t nb_table; + uint64_t *table; + bool bypass; + int fd; + MemoryRegion iommu; + QLIST_ENTRY(sPAPRTCETable) list; +}; + void spapr_events_init(sPAPREnvironment *spapr); void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq); sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, size_t window_size); MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); -void spapr_tce_free(sPAPRTCETable *tcet); -void spapr_tce_reset(sPAPRTCETable *tcet); void spapr_tce_set_bypass(sPAPRTCETable *tcet, bool bypass); int spapr_dma_dt(void *fdt, int node_off, const char *propname, uint32_t liobn, uint64_t window, uint32_t size); diff --git a/include/hw/ppc/spapr_vio.h b/include/hw/ppc/spapr_vio.h index 36093270e6..46edc2a20c 100644 --- a/include/hw/ppc/spapr_vio.h +++ b/include/hw/ppc/spapr_vio.h @@ -134,4 +134,9 @@ VIOsPAPRDevice *spapr_vty_get_default(VIOsPAPRBus *bus); void spapr_vio_quiesce(void); +extern const VMStateDescription vmstate_spapr_vio; + +#define VMSTATE_SPAPR_VIO(_f, _s) \ + VMSTATE_STRUCT(_f, _s, 0, vmstate_spapr_vio, VIOsPAPRDevice) + #endif /* _HW_SPAPR_VIO_H */ diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 6bce0424df..66364c5faf 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -27,15 +27,77 @@ #if !defined(__XICS_H__) #define __XICS_H__ +#include "hw/sysbus.h" + +#define TYPE_XICS "xics" +#define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS) + #define XICS_IPI 0x2 -#define XICS_IRQ_BASE 0x10 +#define XICS_BUID 0x1 +#define XICS_IRQ_BASE (XICS_BUID << 12) + +/* + * We currently only support one BUID which is our interrupt base + * (the kernel implementation supports more but we don't exploit + * that yet) + */ +typedef struct XICSState XICSState; +typedef struct ICPState ICPState; +typedef struct ICSState ICSState; +typedef struct ICSIRQState ICSIRQState; + +struct XICSState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + uint32_t nr_servers; + uint32_t nr_irqs; + ICPState *ss; + ICSState *ics; +}; + +#define TYPE_ICP "icp" +#define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) + +struct ICPState { + /*< private >*/ + DeviceState parent_obj; + /*< public >*/ + uint32_t xirr; + uint8_t pending_priority; + uint8_t mfrr; + qemu_irq output; +}; + +#define TYPE_ICS "ics" +#define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS) + +struct ICSState { + /*< private >*/ + DeviceState parent_obj; + /*< public >*/ + uint32_t nr_irqs; + uint32_t offset; + qemu_irq *qirqs; + bool *islsi; + ICSIRQState *irqs; + XICSState *icp; +}; -struct icp_state; +struct ICSIRQState { + uint32_t server; + uint8_t priority; + uint8_t saved_priority; +#define XICS_STATUS_ASSERTED 0x1 +#define XICS_STATUS_SENT 0x2 +#define XICS_STATUS_REJECTED 0x4 +#define XICS_STATUS_MASKED_PENDING 0x8 + uint8_t status; +}; -qemu_irq xics_get_qirq(struct icp_state *icp, int irq); -void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi); +qemu_irq xics_get_qirq(XICSState *icp, int irq); +void xics_set_irq_type(XICSState *icp, int irq, bool lsi); -struct icp_state *xics_system_init(int nr_servers, int nr_irqs); -void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu); +void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu); #endif /* __XICS_H__ */ diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 7fbffcbaad..46972f4961 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -4,6 +4,7 @@ #include "qemu/queue.h" #include "qemu/option.h" #include "qemu/typedefs.h" +#include "qemu/bitmap.h" #include "qom/object.h" #include "hw/irq.h" #include "qapi/error.h" @@ -17,6 +18,34 @@ enum { #define DEVICE_CLASS(klass) OBJECT_CLASS_CHECK(DeviceClass, (klass), TYPE_DEVICE) #define DEVICE_GET_CLASS(obj) OBJECT_GET_CLASS(DeviceClass, (obj), TYPE_DEVICE) +typedef enum DeviceCategory { + DEVICE_CATEGORY_BRIDGE, + DEVICE_CATEGORY_USB, + DEVICE_CATEGORY_STORAGE, + DEVICE_CATEGORY_NETWORK, + DEVICE_CATEGORY_INPUT, + DEVICE_CATEGORY_DISPLAY, + DEVICE_CATEGORY_SOUND, + DEVICE_CATEGORY_MISC, + DEVICE_CATEGORY_MAX +} DeviceCategory; + +static inline const char *qdev_category_get_name(DeviceCategory category) +{ + static const char *category_names[DEVICE_CATEGORY_MAX] = { + [DEVICE_CATEGORY_BRIDGE] = "Controller/Bridge/Hub", + [DEVICE_CATEGORY_USB] = "USB", + [DEVICE_CATEGORY_STORAGE] = "Storage", + [DEVICE_CATEGORY_NETWORK] = "Network", + [DEVICE_CATEGORY_INPUT] = "Input", + [DEVICE_CATEGORY_DISPLAY] = "Display", + [DEVICE_CATEGORY_SOUND] = "Sound", + [DEVICE_CATEGORY_MISC] = "Misc", + }; + + return category_names[category]; +}; + typedef int (*qdev_initfn)(DeviceState *dev); typedef int (*qdev_event)(DeviceState *dev); typedef void (*qdev_resetfn)(DeviceState *dev); @@ -80,6 +109,7 @@ typedef struct DeviceClass { ObjectClass parent_class; /*< public >*/ + DECLARE_BITMAP(categories, DEVICE_CATEGORY_MAX); const char *fw_name; const char *desc; Property *props; diff --git a/include/qom/cpu.h b/include/qom/cpu.h index daf1835c1a..0d6e95c0b6 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -80,7 +80,11 @@ struct TranslationBlock; * @synchronize_from_tb: Callback for synchronizing state from a TCG * #TranslationBlock. * @get_phys_page_debug: Callback for obtaining a physical address. + * @gdb_read_register: Callback for letting GDB read a register. + * @gdb_write_register: Callback for letting GDB write a register. * @vmsd: State description for migration. + * @gdb_num_core_regs: Number of core registers accessible to GDB. + * @gdb_core_xml_file: File name for core registers GDB XML description. * * Represents a CPU family or model. */ @@ -108,8 +112,9 @@ typedef struct CPUClass { void (*set_pc)(CPUState *cpu, vaddr value); void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); + int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); + int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); - const struct VMStateDescription *vmsd; int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque); int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, @@ -118,6 +123,10 @@ typedef struct CPUClass { int cpuid, void *opaque); int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, void *opaque); + + const struct VMStateDescription *vmsd; + int gdb_num_core_regs; + const char *gdb_core_xml_file; } CPUClass; struct KVMState; @@ -142,6 +151,7 @@ struct kvm_run; * @env_ptr: Pointer to subclass-specific CPUArchState field. * @current_tb: Currently executing TB. * @gdb_regs: Additional GDB registers. + * @gdb_num_regs: Number of total registers accessible to GDB. * @next_cpu: Next CPU sharing TB cache. * @kvm_fd: vCPU file descriptor for KVM. * @@ -177,6 +187,7 @@ struct CPUState { void *env_ptr; /* CPUArchState */ struct TranslationBlock *current_tb; struct GDBRegisterState *gdb_regs; + int gdb_num_regs; CPUState *next_cpu; int kvm_fd; diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index f8ac448e0b..de74411f41 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -174,7 +174,7 @@ int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, target_ulong len, int type); void kvm_remove_all_breakpoints(CPUState *cpu); -int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap); +int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap); #ifndef _WIN32 int kvm_set_signal_mask(CPUState *cpu, const sigset_t *sigset); #endif @@ -1883,9 +1883,8 @@ static void kvm_invoke_set_guest_debug(void *data) &dbg_data->dbg); } -int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap) +int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) { - CPUState *cpu = ENV_GET_CPU(env); struct kvm_set_guest_debug_data data; data.dbg.control = reinject_trap; @@ -1935,9 +1934,7 @@ int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, } for (cpu = first_cpu; cpu != NULL; cpu = cpu->next_cpu) { - CPUArchState *env = cpu->env_ptr; - - err = kvm_update_guest_debug(env, 0); + err = kvm_update_guest_debug(cpu, 0); if (err) { return err; } @@ -1977,9 +1974,7 @@ int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, } for (cpu = first_cpu; cpu != NULL; cpu = cpu->next_cpu) { - CPUArchState *env = cpu->env_ptr; - - err = kvm_update_guest_debug(env, 0); + err = kvm_update_guest_debug(cpu, 0); if (err) { return err; } @@ -2007,15 +2002,13 @@ void kvm_remove_all_breakpoints(CPUState *cpu) kvm_arch_remove_all_hw_breakpoints(); for (cpu = first_cpu; cpu != NULL; cpu = cpu->next_cpu) { - CPUArchState *env = cpu->env_ptr; - - kvm_update_guest_debug(env, 0); + kvm_update_guest_debug(cpu, 0); } } #else /* !KVM_CAP_SET_GUEST_DEBUG */ -int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap) +int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) { return -EINVAL; } diff --git a/kvm-stub.c b/kvm-stub.c index 7b2233ae82..771360b3ca 100644 --- a/kvm-stub.c +++ b/kvm-stub.c @@ -78,7 +78,7 @@ void kvm_setup_guest_memory(void *start, size_t size) { } -int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap) +int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) { return -ENOSYS; } diff --git a/linux-user/main.c b/linux-user/main.c index 5dc09471e4..03859bcc23 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1920,7 +1920,7 @@ static const uint8_t mips_syscall_args[] = { MIPS_SYS(sys_sched_get_priority_min, 1) MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ MIPS_SYS(sys_nanosleep, 2) - MIPS_SYS(sys_mremap , 4) + MIPS_SYS(sys_mremap , 5) MIPS_SYS(sys_accept , 3) MIPS_SYS(sys_bind , 3) MIPS_SYS(sys_connect , 3) /* 4170 */ @@ -2057,7 +2057,7 @@ static const uint8_t mips_syscall_args[] = { MIPS_SYS(sys_pselect6, 6) MIPS_SYS(sys_ppoll, 5) MIPS_SYS(sys_unshare, 1) - MIPS_SYS(sys_splice, 4) + MIPS_SYS(sys_splice, 6) MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ MIPS_SYS(sys_tee, 4) MIPS_SYS(sys_vmsplice, 4) @@ -3637,7 +3637,7 @@ int main(int argc, char **argv, char **envp) exit(1); } cpu = ENV_GET_CPU(env); - cpu_reset(ENV_GET_CPU(env)); + cpu_reset(cpu); thread_cpu = cpu; @@ -19,6 +19,7 @@ #include "qemu/bitops.h" #include "qom/object.h" #include "sysemu/kvm.h" +#include "trace.h" #include <assert.h> #include "exec/memory-internal.h" @@ -388,6 +389,7 @@ static void memory_region_oldmmio_read_accessor(MemoryRegion *mr, uint64_t tmp; tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr); + trace_memory_region_ops_read(mr, addr, tmp, size); *value |= (tmp & mask) << shift; } @@ -404,6 +406,7 @@ static void memory_region_read_accessor(MemoryRegion *mr, qemu_flush_coalesced_mmio_buffer(); } tmp = mr->ops->read(mr->opaque, addr, size); + trace_memory_region_ops_read(mr, addr, tmp, size); *value |= (tmp & mask) << shift; } @@ -417,6 +420,7 @@ static void memory_region_oldmmio_write_accessor(MemoryRegion *mr, uint64_t tmp; tmp = (*value >> shift) & mask; + trace_memory_region_ops_write(mr, addr, tmp, size); mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp); } @@ -433,6 +437,7 @@ static void memory_region_write_accessor(MemoryRegion *mr, qemu_flush_coalesced_mmio_buffer(); } tmp = (*value >> shift) & mask; + trace_memory_region_ops_write(mr, addr, tmp, size); mr->ops->write(mr->opaque, addr, tmp, size); } diff --git a/migration-rdma.c b/migration-rdma.c index d044830ed8..4828738560 100644 --- a/migration-rdma.c +++ b/migration-rdma.c @@ -2494,7 +2494,7 @@ static int qemu_rdma_close(void *opaque) * @size == 0 : * A 'hint' or 'advice' that means that we wish to speculatively * and asynchronously unregister this memory. In this case, there is no - * gaurantee that the unregister will actually happen, for example, + * guarantee that the unregister will actually happen, for example, * if the memory is being actively transmitted. Additionally, the memory * may be re-registered at any future time if a write within the same * chunk was requested again, even if you attempted to unregister it @@ -2570,7 +2570,7 @@ static size_t qemu_rdma_save_page(QEMUFile *f, void *opaque, qemu_rdma_signal_unregister(rdma, index, chunk, 0); /* - * TODO: Synchronous, gauranteed unregistration (should not occur during + * TODO: Synchronous, guaranteed unregistration (should not occur during * fast-path). Otherwise, unregisters will process on the next call to * qemu_rdma_drain_cq() if (size < 0) { @@ -73,7 +73,7 @@ eth_get_gso_type(uint16_t l3_proto, uint8_t *l3_hdr, uint8_t l4proto) } /* Unsupported offload */ - assert(false); + g_assert_not_reached(); return VIRTIO_NET_HDR_GSO_NONE | ecn_state; } diff --git a/pc-bios/qemu-nsis.bmp b/pc-bios/qemu-nsis.bmp Binary files differnew file mode 100644 index 0000000000..ae82cd2697 --- /dev/null +++ b/pc-bios/qemu-nsis.bmp diff --git a/pc-bios/qemu-nsis.ico b/pc-bios/qemu-nsis.ico Binary files differnew file mode 100644 index 0000000000..1d0128cd4c --- /dev/null +++ b/pc-bios/qemu-nsis.ico diff --git a/pc-bios/s390-ccw.img b/pc-bios/s390-ccw.img Binary files differindex 1b2a11e728..05fc7c2fae 100644 --- a/pc-bios/s390-ccw.img +++ b/pc-bios/s390-ccw.img diff --git a/pc-bios/s390-ccw/cio.h b/pc-bios/s390-ccw/cio.h index cb5815accd..f5b4549ea3 100644 --- a/pc-bios/s390-ccw/cio.h +++ b/pc-bios/s390-ccw/cio.h @@ -93,6 +93,26 @@ struct subchannel_id { __u32 sch_no : 16; } __attribute__ ((packed, aligned(4))); +struct chsc_header { + __u16 length; + __u16 code; +} __attribute__((packed)); + +struct chsc_area_sda { + struct chsc_header request; + __u8 reserved1:4; + __u8 format:4; + __u8 reserved2; + __u16 operation_code; + __u32 reserved3; + __u32 reserved4; + __u32 operation_data_area[252]; + struct chsc_header response; + __u32 reserved5:4; + __u32 format2:4; + __u32 reserved6:24; +} __attribute__((packed)); + /* * TPI info structure */ diff --git a/pc-bios/s390-ccw/main.c b/pc-bios/s390-ccw/main.c index 1665c57225..c5d533231b 100644 --- a/pc-bios/s390-ccw/main.c +++ b/pc-bios/s390-ccw/main.c @@ -35,6 +35,13 @@ static void virtio_setup(uint64_t dev_info) check_devno = true; dev_no = dev_info & 0xffff; debug_print_int("device no. ", dev_no); + blk_schid.ssid = (dev_info >> 16) & 0x3; + if (blk_schid.ssid != 0) { + debug_print_int("ssid ", blk_schid.ssid); + if (enable_mss_facility() != 0) { + virtio_panic("Failed to enable mss facility\n"); + } + } } for (i = 0; i < 0x10000; i++) { diff --git a/pc-bios/s390-ccw/s390-ccw.h b/pc-bios/s390-ccw/s390-ccw.h index 8241b0af05..5e871ac84c 100644 --- a/pc-bios/s390-ccw/s390-ccw.h +++ b/pc-bios/s390-ccw/s390-ccw.h @@ -61,6 +61,7 @@ unsigned long virtio_load_direct(ulong rec_list1, ulong rec_list2, bool virtio_is_blk(struct subchannel_id schid); void virtio_setup_block(struct subchannel_id schid); int virtio_read(ulong sector, void *load_addr); +int enable_mss_facility(void); /* bootmap.c */ int zipl_load(void); diff --git a/pc-bios/s390-ccw/virtio.c b/pc-bios/s390-ccw/virtio.c index f438af15aa..49f2d291fc 100644 --- a/pc-bios/s390-ccw/virtio.c +++ b/pc-bios/s390-ccw/virtio.c @@ -13,6 +13,8 @@ struct vring block; +static char chsc_page[PAGE_SIZE] __attribute__((__aligned__(PAGE_SIZE))); + static long kvm_hypercall(unsigned long nr, unsigned long param1, unsigned long param2) { @@ -301,3 +303,19 @@ bool virtio_is_blk(struct subchannel_id schid) return true; } +int enable_mss_facility(void) +{ + int ret; + struct chsc_area_sda *sda_area = (struct chsc_area_sda *) chsc_page; + + memset(sda_area, 0, PAGE_SIZE); + sda_area->request.length = 0x0400; + sda_area->request.code = 0x0031; + sda_area->operation_code = 0x2; + + ret = chsc(sda_area); + if ((ret == 0) && (sda_area->response.code == 0x0001)) { + return 0; + } + return -EIO; +} diff --git a/qapi-schema.json b/qapi-schema.json index f82d829fdc..a51f7d2d6e 100644 --- a/qapi-schema.json +++ b/qapi-schema.json @@ -3362,15 +3362,15 @@ '*rows' : 'int' } } ## -# @ChardevMemory: +# @ChardevRingbuf: # -# Configuration info for memory chardevs +# Configuration info for ring buffer chardevs. # -# @size: #optional Ringbuffer size, must be power of two, default is 65536 +# @size: #optional ring buffer size, must be power of two, default is 65536 # # Since: 1.5 ## -{ 'type': 'ChardevMemory', 'data': { '*size' : 'int' } } +{ 'type': 'ChardevRingbuf', 'data': { '*size' : 'int' } } ## # @ChardevBackend: @@ -3397,7 +3397,9 @@ 'spicevmc' : 'ChardevSpiceChannel', 'spiceport' : 'ChardevSpicePort', 'vc' : 'ChardevVC', - 'memory' : 'ChardevMemory' } } + 'ringbuf': 'ChardevRingbuf', + # next one is just for compatibility + 'memory' : 'ChardevRingbuf' } } ## # @ChardevReturn: diff --git a/qdev-monitor.c b/qdev-monitor.c index e54dbc2c5d..410cdcbe97 100644 --- a/qdev-monitor.c +++ b/qdev-monitor.c @@ -75,24 +75,27 @@ static bool qdev_class_has_alias(DeviceClass *dc) return (qdev_class_get_alias(dc) != NULL); } -static void qdev_print_devinfo(ObjectClass *klass, void *opaque) +static void qdev_print_class_devinfo(DeviceClass *dc) { - DeviceClass *dc; - bool *show_no_user = opaque; - - dc = (DeviceClass *)object_class_dynamic_cast(klass, TYPE_DEVICE); + DeviceCategory category; - if (!dc || (show_no_user && !*show_no_user && dc->no_user)) { + if (!dc) { return; } - error_printf("name \"%s\"", object_class_get_name(klass)); + error_printf("name \"%s\"", object_class_get_name(OBJECT_CLASS(dc))); if (dc->bus_type) { error_printf(", bus %s", dc->bus_type); } if (qdev_class_has_alias(dc)) { error_printf(", alias \"%s\"", qdev_class_get_alias(dc)); } + error_printf(", categories"); + for (category = 0; category < DEVICE_CATEGORY_MAX; ++category) { + if (test_bit(category, dc->categories)) { + error_printf(" \"%s\"", qdev_category_get_name(category)); + } + } if (dc->desc) { error_printf(", desc \"%s\"", dc->desc); } @@ -102,6 +105,15 @@ static void qdev_print_devinfo(ObjectClass *klass, void *opaque) error_printf("\n"); } +static void qdev_print_devinfo(ObjectClass *klass, void *opaque) +{ + DeviceClass *dc; + + dc = (DeviceClass *)object_class_dynamic_cast(klass, TYPE_DEVICE); + + qdev_print_class_devinfo(dc); +} + static int set_property(const char *name, const char *value, void *opaque) { DeviceState *dev = opaque; @@ -139,6 +151,21 @@ static const char *find_typename_by_alias(const char *alias) return NULL; } +static void qdev_print_category_devices(DeviceCategory category) +{ + DeviceClass *dc; + GSList *list, *curr; + + list = object_class_get_list(TYPE_DEVICE, false); + for (curr = list; curr; curr = g_slist_next(curr)) { + dc = (DeviceClass *)object_class_dynamic_cast(curr->data, TYPE_DEVICE); + if (!dc->no_user && test_bit(category, dc->categories)) { + qdev_print_class_devinfo(dc); + } + } + g_slist_free(list); +} + int qdev_device_help(QemuOpts *opts) { const char *driver; @@ -147,8 +174,11 @@ int qdev_device_help(QemuOpts *opts) driver = qemu_opt_get(opts, "driver"); if (driver && is_help_option(driver)) { - bool show_no_user = false; - object_class_foreach(qdev_print_devinfo, TYPE_DEVICE, false, &show_no_user); + DeviceCategory category; + for (category = 0; category < DEVICE_CATEGORY_MAX; ++category) { + qdev_print_category_devices(category); + } + return 1; } @@ -360,7 +390,7 @@ static BusState *qbus_find(const char *path) /* find device */ if (sscanf(path+pos, "%127[^/]%n", elem, &len) != 1) { - assert(0); + g_assert_not_reached(); elem[0] = len = 0; } pos += len; @@ -397,7 +427,7 @@ static BusState *qbus_find(const char *path) /* find bus */ if (sscanf(path+pos, "%127[^/]%n", elem, &len) != 1) { - assert(0); + g_assert_not_reached(); elem[0] = len = 0; } pos += len; diff --git a/qemu-char.c b/qemu-char.c index c86ce4ba2e..3f606c935b 100644 --- a/qemu-char.c +++ b/qemu-char.c @@ -2783,8 +2783,8 @@ static void ringbuf_chr_close(struct CharDriverState *chr) chr->opaque = NULL; } -static CharDriverState *qemu_chr_open_memory(ChardevMemory *opts, - Error **errp) +static CharDriverState *qemu_chr_open_ringbuf(ChardevRingbuf *opts, + Error **errp) { CharDriverState *chr; RingBufCharDriver *d; @@ -2796,7 +2796,7 @@ static CharDriverState *qemu_chr_open_memory(ChardevMemory *opts, /* The size must be power of 2 */ if (d->size & (d->size - 1)) { - error_setg(errp, "size of memory chardev must be power of two"); + error_setg(errp, "size of ringbuf chardev must be power of two"); goto fail; } @@ -3105,17 +3105,17 @@ static void qemu_chr_parse_pipe(QemuOpts *opts, ChardevBackend *backend, backend->pipe->device = g_strdup(device); } -static void qemu_chr_parse_memory(QemuOpts *opts, ChardevBackend *backend, - Error **errp) +static void qemu_chr_parse_ringbuf(QemuOpts *opts, ChardevBackend *backend, + Error **errp) { int val; - backend->memory = g_new0(ChardevMemory, 1); + backend->ringbuf = g_new0(ChardevRingbuf, 1); val = qemu_opt_get_size(opts, "size", 0); if (val != 0) { - backend->memory->has_size = true; - backend->memory->size = val; + backend->ringbuf->has_size = true; + backend->ringbuf->size = val; } } @@ -3723,8 +3723,9 @@ ChardevReturn *qmp_chardev_add(const char *id, ChardevBackend *backend, case CHARDEV_BACKEND_KIND_VC: chr = vc_init(backend->vc); break; + case CHARDEV_BACKEND_KIND_RINGBUF: case CHARDEV_BACKEND_KIND_MEMORY: - chr = qemu_chr_open_memory(backend->memory, errp); + chr = qemu_chr_open_ringbuf(backend->ringbuf, errp); break; default: error_setg(errp, "unknown chardev backend (%d)", backend->kind); @@ -3774,8 +3775,8 @@ static void register_types(void) register_char_driver_qapi("null", CHARDEV_BACKEND_KIND_NULL, NULL); register_char_driver("socket", qemu_chr_open_socket); register_char_driver("udp", qemu_chr_open_udp); - register_char_driver_qapi("memory", CHARDEV_BACKEND_KIND_MEMORY, - qemu_chr_parse_memory); + register_char_driver_qapi("ringbuf", CHARDEV_BACKEND_KIND_RINGBUF, + qemu_chr_parse_ringbuf); register_char_driver_qapi("file", CHARDEV_BACKEND_KIND_FILE, qemu_chr_parse_file_out); register_char_driver_qapi("stdio", CHARDEV_BACKEND_KIND_STDIO, @@ -3794,6 +3795,9 @@ static void register_types(void) qemu_chr_parse_pipe); register_char_driver_qapi("mux", CHARDEV_BACKEND_KIND_MUX, qemu_chr_parse_mux); + /* Bug-compatibility: */ + register_char_driver_qapi("memory", CHARDEV_BACKEND_KIND_MEMORY, + qemu_chr_parse_ringbuf); } type_init(register_types); diff --git a/qemu-options.hx b/qemu-options.hx index 2dbfd42a8c..d15338e879 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -844,7 +844,8 @@ you can totally disable graphical output so that QEMU is a simple command line application. The emulated serial port is redirected on the console and muxed with the monitor (unless redirected elsewhere explicitly). Therefore, you can still use QEMU to debug a Linux kernel -with a serial console. +with a serial console. Use @key{C-a h} for help on switching between +the console and monitor. ETEXI DEF("curses", 0, QEMU_OPTION_curses, @@ -1782,7 +1783,7 @@ DEF("chardev", HAS_ARG, QEMU_OPTION_chardev, "-chardev msmouse,id=id[,mux=on|off]\n" "-chardev vc,id=id[[,width=width][,height=height]][[,cols=cols][,rows=rows]]\n" " [,mux=on|off]\n" - "-chardev memory,id=id[,size=size]\n" + "-chardev ringbuf,id=id[,size=size]\n" "-chardev file,id=id,path=path[,mux=on|off]\n" "-chardev pipe,id=id,path=path[,mux=on|off]\n" #ifdef _WIN32 @@ -1820,7 +1821,7 @@ Backend is one of: @option{udp}, @option{msmouse}, @option{vc}, -@option{memory}, +@option{ringbuf}, @option{file}, @option{pipe}, @option{console}, @@ -1929,7 +1930,7 @@ the console, in pixels. @option{cols} and @option{rows} specify that the console be sized to fit a text console with the given dimensions. -@item -chardev memory ,id=@var{id} [,size=@var{size}] +@item -chardev ringbuf ,id=@var{id} [,size=@var{size}] Create a ring buffer with fixed size @option{size}. @var{size} must be a power of two, and defaults to @code{64K}). diff --git a/qemu-seccomp.c b/qemu-seccomp.c index ca123bfeba..3298de8f34 100644 --- a/qemu-seccomp.c +++ b/qemu-seccomp.c @@ -26,12 +26,9 @@ static const struct QemuSeccompSyscall seccomp_whitelist[] = { { SCMP_SYS(timer_gettime), 254 }, { SCMP_SYS(futex), 253 }, { SCMP_SYS(select), 252 }, -#if defined(__x86_64__) { SCMP_SYS(recvfrom), 251 }, { SCMP_SYS(sendto), 250 }, -#elif defined(__i386__) { SCMP_SYS(socketcall), 250 }, -#endif { SCMP_SYS(read), 249 }, { SCMP_SYS(brk), 248 }, { SCMP_SYS(clone), 247 }, @@ -40,7 +37,6 @@ static const struct QemuSeccompSyscall seccomp_whitelist[] = { { SCMP_SYS(execve), 245 }, { SCMP_SYS(open), 245 }, { SCMP_SYS(ioctl), 245 }, -#if defined(__x86_64__) { SCMP_SYS(socket), 245 }, { SCMP_SYS(setsockopt), 245 }, { SCMP_SYS(recvmsg), 245 }, @@ -51,9 +47,7 @@ static const struct QemuSeccompSyscall seccomp_whitelist[] = { { SCMP_SYS(bind), 245 }, { SCMP_SYS(listen), 245 }, { SCMP_SYS(semget), 245 }, -#elif defined(__i386__) { SCMP_SYS(ipc), 245 }, -#endif { SCMP_SYS(gettimeofday), 245 }, { SCMP_SYS(readlink), 245 }, { SCMP_SYS(access), 245 }, @@ -64,7 +58,6 @@ static const struct QemuSeccompSyscall seccomp_whitelist[] = { { SCMP_SYS(statfs), 245 }, { SCMP_SYS(unlink), 245 }, { SCMP_SYS(wait4), 245 }, -#if defined(__i386__) { SCMP_SYS(fcntl64), 245 }, { SCMP_SYS(fstat64), 245 }, { SCMP_SYS(stat64), 245 }, @@ -77,7 +70,6 @@ static const struct QemuSeccompSyscall seccomp_whitelist[] = { { SCMP_SYS(_llseek), 245 }, { SCMP_SYS(mmap2), 245 }, { SCMP_SYS(sigprocmask), 245 }, -#endif { SCMP_SYS(sched_getparam), 245 }, { SCMP_SYS(sched_getscheduler), 245 }, { SCMP_SYS(fstat), 245 }, @@ -116,7 +108,6 @@ static const struct QemuSeccompSyscall seccomp_whitelist[] = { { SCMP_SYS(lseek), 245 }, { SCMP_SYS(pselect6), 245 }, { SCMP_SYS(fork), 245 }, - { SCMP_SYS(eventfd), 245 }, { SCMP_SYS(rt_sigprocmask), 245 }, { SCMP_SYS(write), 244 }, { SCMP_SYS(fcntl), 243 }, @@ -145,21 +136,17 @@ static const struct QemuSeccompSyscall seccomp_whitelist[] = { { SCMP_SYS(epoll_create), 242 }, { SCMP_SYS(epoll_ctl), 242 }, { SCMP_SYS(epoll_wait), 242 }, -#if defined(__i386__) { SCMP_SYS(waitpid), 242 }, -#elif defined(__x86_64__) { SCMP_SYS(getsockname), 242 }, { SCMP_SYS(getpeername), 242 }, { SCMP_SYS(accept4), 242 }, { SCMP_SYS(newfstatat), 241 }, { SCMP_SYS(shutdown), 241 }, { SCMP_SYS(getsockopt), 241 }, - { SCMP_SYS(semctl), 241 }, { SCMP_SYS(semop), 241 }, { SCMP_SYS(semtimedop), 241 }, { SCMP_SYS(epoll_ctl_old), 241 }, { SCMP_SYS(epoll_wait_old), 241 }, -#endif { SCMP_SYS(epoll_pwait), 241 }, { SCMP_SYS(epoll_create1), 241 }, { SCMP_SYS(ppoll), 241 }, @@ -174,7 +161,6 @@ static const struct QemuSeccompSyscall seccomp_whitelist[] = { { SCMP_SYS(getresuid), 241 }, { SCMP_SYS(getresgid), 241 }, { SCMP_SYS(getgroups), 241 }, -#if defined(__i386__) { SCMP_SYS(getresuid32), 241 }, { SCMP_SYS(getresgid32), 241 }, { SCMP_SYS(getgroups32), 241 }, @@ -193,7 +179,6 @@ static const struct QemuSeccompSyscall seccomp_whitelist[] = { { SCMP_SYS(lstat64), 241 }, { SCMP_SYS(sendfile64), 241 }, { SCMP_SYS(ugetrlimit), 241 }, -#endif { SCMP_SYS(alarm), 241 }, { SCMP_SYS(rt_sigsuspend), 241 }, { SCMP_SYS(rt_sigqueueinfo), 241 }, @@ -205,12 +190,10 @@ static const struct QemuSeccompSyscall seccomp_whitelist[] = { { SCMP_SYS(lchown), 241 }, { SCMP_SYS(fchownat), 241 }, { SCMP_SYS(fstatfs), 241 }, - { SCMP_SYS(sendfile), 241 }, { SCMP_SYS(getitimer), 241 }, { SCMP_SYS(syncfs), 241 }, { SCMP_SYS(fsync), 241 }, { SCMP_SYS(fchdir), 241 }, - { SCMP_SYS(flock), 241 }, { SCMP_SYS(msync), 241 }, { SCMP_SYS(sched_setparam), 241 }, { SCMP_SYS(sched_setscheduler), 241 }, diff --git a/qemu.nsi b/qemu.nsi new file mode 100644 index 0000000000..1d57455956 --- /dev/null +++ b/qemu.nsi @@ -0,0 +1,250 @@ +;!/usr/bin/makensis + +; This NSIS script creates an installer for QEMU on Windows. + +; Copyright (C) 2006-2012 Stefan Weil +; +; This program is free software: you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation, either version 2 of the License, or +; (at your option) version 3 or any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program. If not, see <http://www.gnu.org/licenses/>. + +; NSIS_WIN32_MAKENSIS + +!define PRODUCT "QEMU" +!define URL "http://www.qemu.org/" + +!define UNINST_EXE "$INSTDIR\qemu-uninstall.exe" +!define UNINST_KEY "Software\Microsoft\Windows\CurrentVersion\Uninstall\${PRODUCT}" + +!ifndef BINDIR +!define BINDIR nsis.tmp +!endif +!ifndef SRCDIR +!define SRCDIR . +!endif +!ifndef OUTFILE +!define OUTFILE "qemu-setup.exe" +!endif + +; Optionally install documentation. +!ifndef CONFIG_DOCUMENTATION +!define CONFIG_DOCUMENTATION +!endif + +; Use maximum compression. +SetCompressor /SOLID lzma + +!include "MUI2.nsh" + +; The name of the installer. +Name "QEMU" + +; The file to write +OutFile "${OUTFILE}" + +; The default installation directory. +!ifdef W64 +InstallDir $PROGRAMFILES64\qemu +!else +InstallDir $PROGRAMFILES\qemu +!endif + +; Registry key to check for directory (so if you install again, it will +; overwrite the old one automatically) +InstallDirRegKey HKLM "Software\qemu" "Install_Dir" + +; Request administrator privileges for Windows Vista. +RequestExecutionLevel admin + +;-------------------------------- +; Interface Settings. +;!define MUI_HEADERIMAGE "qemu-nsis.bmp" +; !define MUI_SPECIALBITMAP "qemu.bmp" +!define MUI_ICON "${SRCDIR}\pc-bios\qemu-nsis.ico" +!define MUI_UNICON "${SRCDIR}\pc-bios\qemu-nsis.ico" +!define MUI_WELCOMEFINISHPAGE_BITMAP "${SRCDIR}\pc-bios\qemu-nsis.bmp" +; !define MUI_HEADERIMAGE_BITMAP "qemu-install.bmp" +; !define MUI_HEADERIMAGE_UNBITMAP "qemu-uninstall.bmp" +; !define MUI_COMPONENTSPAGE_SMALLDESC +; !define MUI_WELCOMEPAGE_TEXT "Insert text here.$\r$\n$\r$\n$\r$\n$_CLICK" + +;-------------------------------- +; Pages. + +!insertmacro MUI_PAGE_WELCOME +!insertmacro MUI_PAGE_LICENSE "${SRCDIR}\COPYING" +!insertmacro MUI_PAGE_COMPONENTS +!insertmacro MUI_PAGE_DIRECTORY +!insertmacro MUI_PAGE_INSTFILES +!define MUI_FINISHPAGE_LINK "Visit the QEMU Wiki online!" +!define MUI_FINISHPAGE_LINK_LOCATION "${URL}" +!insertmacro MUI_PAGE_FINISH + +!insertmacro MUI_UNPAGE_CONFIRM +!insertmacro MUI_UNPAGE_INSTFILES + +;-------------------------------- +; Languages. + +!insertmacro MUI_LANGUAGE "English" +!insertmacro MUI_LANGUAGE "French" +!insertmacro MUI_LANGUAGE "German" + +;-------------------------------- + +; The stuff to install. +Section "${PRODUCT} (required)" + + SectionIn RO + + ; Set output path to the installation directory. + SetOutPath "$INSTDIR" + + File "${SRCDIR}\Changelog" + File "${SRCDIR}\COPYING" + File "${SRCDIR}\COPYING.LIB" + File "${SRCDIR}\README" + File "${SRCDIR}\VERSION" + + File "${BINDIR}\*.bmp" + File "${BINDIR}\*.bin" + File "${BINDIR}\*.dtb" + File "${BINDIR}\*.rom" + File "${BINDIR}\openbios-*" + + File /r "${BINDIR}\keymaps" +!ifdef CONFIG_GTK + File /r "${BINDIR}\share" +!endif + +!ifdef W64 + SetRegView 64 +!endif + + ; Write the installation path into the registry + WriteRegStr HKLM SOFTWARE\${PRODUCT} "Install_Dir" "$INSTDIR" + + ; Write the uninstall keys for Windows + WriteRegStr HKLM "${UNINST_KEY}" "DisplayName" "QEMU" + WriteRegStr HKLM "${UNINST_KEY}" "UninstallString" '"${UNINST_EXE}"' + WriteRegDWORD HKLM "${UNINST_KEY}" "NoModify" 1 + WriteRegDWORD HKLM "${UNINST_KEY}" "NoRepair" 1 + WriteUninstaller "qemu-uninstall.exe" +SectionEnd + +Section "Tools" SectionTools + SetOutPath "$INSTDIR" + File "${BINDIR}\qemu-img.exe" + File "${BINDIR}\qemu-io.exe" +SectionEnd + +SectionGroup "System Emulations" SectionSystem + +!include "${BINDIR}\system-emulations.nsh" + +SectionGroupEnd + +!ifdef DLLDIR +Section "Libraries (DLL)" SectionDll + SetOutPath "$INSTDIR" + File "${DLLDIR}\*.dll" +SectionEnd +!endif + +!ifdef CONFIG_DOCUMENTATION +Section "Documentation" SectionDoc + SetOutPath "$INSTDIR" + File "${BINDIR}\qemu-doc.html" + File "${BINDIR}\qemu-tech.html" + CreateDirectory "$SMPROGRAMS\${PRODUCT}" + CreateShortCut "$SMPROGRAMS\${PRODUCT}\User Documentation.lnk" "$INSTDIR\qemu-doc.html" "" "$INSTDIR\qemu-doc.html" 0 + CreateShortCut "$SMPROGRAMS\${PRODUCT}\Technical Documentation.lnk" "$INSTDIR\qemu-tech.html" "" "$INSTDIR\qemu-tech.html" 0 +SectionEnd +!endif + +; Optional section (can be disabled by the user) +Section "Start Menu Shortcuts" SectionMenu + CreateDirectory "$SMPROGRAMS\${PRODUCT}" + CreateShortCut "$SMPROGRAMS\${PRODUCT}\Uninstall.lnk" "${UNINST_EXE}" "" "${UNINST_EXE}" 0 +SectionEnd + +;-------------------------------- + +; Uninstaller + +Section "Uninstall" + ; Remove registry keys +!ifdef W64 + SetRegView 64 +!endif + DeleteRegKey HKLM "${UNINST_KEY}" + DeleteRegKey HKLM SOFTWARE\${PRODUCT} + + ; Remove shortcuts, if any + Delete "$SMPROGRAMS\${PRODUCT}\User Documentation.lnk" + Delete "$SMPROGRAMS\${PRODUCT}\Technical Documentation.lnk" + Delete "$SMPROGRAMS\${PRODUCT}\Uninstall.lnk" + RMDir "$SMPROGRAMS\${PRODUCT}" + + ; Remove files and directories used + Delete "$INSTDIR\Changelog" + Delete "$INSTDIR\COPYING" + Delete "$INSTDIR\COPYING.LIB" + Delete "$INSTDIR\README" + Delete "$INSTDIR\VERSION" + Delete "$INSTDIR\*.bmp" + Delete "$INSTDIR\*.bin" + Delete "$INSTDIR\*.dll" + Delete "$INSTDIR\*.dtb" + Delete "$INSTDIR\*.rom" + Delete "$INSTDIR\openbios-*" + Delete "$INSTDIR\qemu-img.exe" + Delete "$INSTDIR\qemu-io.exe" + Delete "$INSTDIR\qemu.exe" + Delete "$INSTDIR\qemu-system-*.exe" + Delete "$INSTDIR\qemu-doc.html" + Delete "$INSTDIR\qemu-tech.html" + RMDir /r "$INSTDIR\keymaps" + RMDir /r "$INSTDIR\share" + ; Remove generated files + Delete "$INSTDIR\stderr.txt" + Delete "$INSTDIR\stdout.txt" + ; Remove uninstaller + Delete "${UNINST_EXE}" + RMDir "$INSTDIR" +SectionEnd + +;-------------------------------- + +; Descriptions (mouse-over). +!insertmacro MUI_FUNCTION_DESCRIPTION_BEGIN + !insertmacro MUI_DESCRIPTION_TEXT ${SectionSystem} "System emulation." + !insertmacro MUI_DESCRIPTION_TEXT ${Section_alpha} "Alpha system emulation." + !insertmacro MUI_DESCRIPTION_TEXT ${Section_alphaw} "Alpha system emulation (GUI)." + !insertmacro MUI_DESCRIPTION_TEXT ${Section_i386} "PC i386 system emulation." + !insertmacro MUI_DESCRIPTION_TEXT ${Section_i386w} "PC i386 system emulation (GUI)." + !insertmacro MUI_DESCRIPTION_TEXT ${SectionTools} "Tools." +!ifdef DLLDIR + !insertmacro MUI_DESCRIPTION_TEXT ${SectionDll} "Runtime Libraries (DLL)." +!endif +!ifdef CONFIG_DOCUMENTATION + !insertmacro MUI_DESCRIPTION_TEXT ${SectionDoc} "Documentation." +!endif + !insertmacro MUI_DESCRIPTION_TEXT ${SectionMenu} "Menu entries." +!insertmacro MUI_FUNCTION_DESCRIPTION_END + +;-------------------------------- +; Functions. + +Function .onInit + !insertmacro MUI_LANGDLL_DISPLAY +FunctionEnd @@ -157,6 +157,17 @@ static int cpu_common_write_elf64_note(WriteCoreDumpFunction f, } +static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg) +{ + return 0; +} + +static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg) +{ + return 0; +} + + void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -217,8 +228,6 @@ static void cpu_common_realizefn(DeviceState *dev, Error **errp) { CPUState *cpu = CPU(dev); - qemu_init_vcpu(cpu); - if (dev->hotplugged) { cpu_synchronize_post_init(cpu); notifier_list_notify(&cpu_added_notifiers, dev); @@ -226,6 +235,14 @@ static void cpu_common_realizefn(DeviceState *dev, Error **errp) } } +static void cpu_common_initfn(Object *obj) +{ + CPUState *cpu = CPU(obj); + CPUClass *cc = CPU_GET_CLASS(obj); + + cpu->gdb_num_regs = cc->gdb_num_core_regs; +} + static int64_t cpu_common_get_arch_id(CPUState *cpu) { return cpu->cpu_index; @@ -245,6 +262,8 @@ static void cpu_class_init(ObjectClass *klass, void *data) k->write_elf32_note = cpu_common_write_elf32_note; k->write_elf64_qemunote = cpu_common_write_elf64_qemunote; k->write_elf64_note = cpu_common_write_elf64_note; + k->gdb_read_register = cpu_common_gdb_read_register; + k->gdb_write_register = cpu_common_gdb_write_register; dc->realize = cpu_common_realizefn; dc->no_user = 1; } @@ -253,6 +272,7 @@ static const TypeInfo cpu_type_info = { .name = TYPE_CPU, .parent = TYPE_DEVICE, .instance_size = sizeof(CPUState), + .instance_init = cpu_common_initfn, .abstract = true, .class_size = sizeof(CPUClass), .class_init = cpu_class_init, diff --git a/scripts/qapi.py b/scripts/qapi.py index 38c808e256..0ebea945bb 100644 --- a/scripts/qapi.py +++ b/scripts/qapi.py @@ -2,14 +2,17 @@ # QAPI helper library # # Copyright IBM, Corp. 2011 +# Copyright (c) 2013 Red Hat Inc. # # Authors: # Anthony Liguori <aliguori@us.ibm.com> +# Markus Armbruster <armbru@redhat.com> # # This work is licensed under the terms of the GNU GPLv2. # See the COPYING.LIB file in the top-level directory. from ordereddict import OrderedDict +import sys builtin_types = [ 'str', 'int', 'number', 'bool', @@ -32,99 +35,147 @@ builtin_type_qtypes = { 'uint64': 'QTYPE_QINT', } -def tokenize(data): - while len(data): - ch = data[0] - data = data[1:] - if ch in ['{', '}', ':', ',', '[', ']']: - yield ch - elif ch in ' \n': - None - elif ch == "'": - string = '' - esc = False - while True: - if (data == ''): - raise Exception("Mismatched quotes") - ch = data[0] - data = data[1:] - if esc: - string += ch - esc = False - elif ch == "\\": - esc = True - elif ch == "'": - break - else: - string += ch - yield string - -def parse(tokens): - if tokens[0] == '{': - ret = OrderedDict() - tokens = tokens[1:] - while tokens[0] != '}': - key = tokens[0] - tokens = tokens[1:] - - tokens = tokens[1:] # : - - value, tokens = parse(tokens) - - if tokens[0] == ',': - tokens = tokens[1:] - - ret[key] = value - tokens = tokens[1:] - return ret, tokens - elif tokens[0] == '[': - ret = [] - tokens = tokens[1:] - while tokens[0] != ']': - value, tokens = parse(tokens) - if tokens[0] == ',': - tokens = tokens[1:] - ret.append(value) - tokens = tokens[1:] - return ret, tokens - else: - return tokens[0], tokens[1:] - -def evaluate(string): - return parse(map(lambda x: x, tokenize(string)))[0] - -def get_expr(fp): - expr = '' - - for line in fp: - if line.startswith('#') or line == '\n': - continue - - if line.startswith(' '): - expr += line - elif expr: - yield expr - expr = line +class QAPISchemaError(Exception): + def __init__(self, schema, msg): + self.fp = schema.fp + self.msg = msg + self.line = self.col = 1 + for ch in schema.src[0:schema.pos]: + if ch == '\n': + self.line += 1 + self.col = 1 + elif ch == '\t': + self.col = (self.col + 7) % 8 + 1 + else: + self.col += 1 + + def __str__(self): + return "%s:%s:%s: %s" % (self.fp.name, self.line, self.col, self.msg) + +class QAPISchema: + + def __init__(self, fp): + self.fp = fp + self.src = fp.read() + if self.src == '' or self.src[-1] != '\n': + self.src += '\n' + self.cursor = 0 + self.exprs = [] + self.accept() + + while self.tok != None: + self.exprs.append(self.get_expr(False)) + + def accept(self): + while True: + self.tok = self.src[self.cursor] + self.pos = self.cursor + self.cursor += 1 + self.val = None + + if self.tok == '#': + self.cursor = self.src.find('\n', self.cursor) + elif self.tok in ['{', '}', ':', ',', '[', ']']: + return + elif self.tok == "'": + string = '' + esc = False + while True: + ch = self.src[self.cursor] + self.cursor += 1 + if ch == '\n': + raise QAPISchemaError(self, + 'Missing terminating "\'"') + if esc: + string += ch + esc = False + elif ch == "\\": + esc = True + elif ch == "'": + self.val = string + return + else: + string += ch + elif self.tok == '\n': + if self.cursor == len(self.src): + self.tok = None + return + elif not self.tok.isspace(): + raise QAPISchemaError(self, 'Stray "%s"' % self.tok) + + def get_members(self): + expr = OrderedDict() + if self.tok == '}': + self.accept() + return expr + if self.tok != "'": + raise QAPISchemaError(self, 'Expected string or "}"') + while True: + key = self.val + self.accept() + if self.tok != ':': + raise QAPISchemaError(self, 'Expected ":"') + self.accept() + expr[key] = self.get_expr(True) + if self.tok == '}': + self.accept() + return expr + if self.tok != ',': + raise QAPISchemaError(self, 'Expected "," or "}"') + self.accept() + if self.tok != "'": + raise QAPISchemaError(self, 'Expected string') + + def get_values(self): + expr = [] + if self.tok == ']': + self.accept() + return expr + if not self.tok in [ '{', '[', "'" ]: + raise QAPISchemaError(self, 'Expected "{", "[", "]" or string') + while True: + expr.append(self.get_expr(True)) + if self.tok == ']': + self.accept() + return expr + if self.tok != ',': + raise QAPISchemaError(self, 'Expected "," or "]"') + self.accept() + + def get_expr(self, nested): + if self.tok != '{' and not nested: + raise QAPISchemaError(self, 'Expected "{"') + if self.tok == '{': + self.accept() + expr = self.get_members() + elif self.tok == '[': + self.accept() + expr = self.get_values() + elif self.tok == "'": + expr = self.val + self.accept() else: - expr += line - - if expr: - yield expr + raise QAPISchemaError(self, 'Expected "{", "[" or string') + return expr def parse_schema(fp): + try: + schema = QAPISchema(fp) + except QAPISchemaError as e: + print >>sys.stderr, e + exit(1) + exprs = [] - for expr in get_expr(fp): - expr_eval = evaluate(expr) - - if expr_eval.has_key('enum'): - add_enum(expr_eval['enum']) - elif expr_eval.has_key('union'): - add_union(expr_eval) - add_enum('%sKind' % expr_eval['union']) - elif expr_eval.has_key('type'): - add_struct(expr_eval) - exprs.append(expr_eval) + for expr in schema.exprs: + if expr.has_key('enum'): + add_enum(expr['enum']) + elif expr.has_key('union'): + add_union(expr) + add_enum('%sKind' % expr['union']) + elif expr.has_key('type'): + add_struct(expr) + exprs.append(expr) return exprs diff --git a/stubs/Makefile.objs b/stubs/Makefile.objs index 9b701b4714..f306cbada3 100644 --- a/stubs/Makefile.objs +++ b/stubs/Makefile.objs @@ -7,6 +7,7 @@ stub-obj-y += fdset-add-fd.o stub-obj-y += fdset-find-fd.o stub-obj-y += fdset-get-fd.o stub-obj-y += fdset-remove-fd.o +stub-obj-y += gdbstub.o stub-obj-y += get-fd.o stub-obj-y += get-vm-name.o stub-obj-y += iothread-lock.o diff --git a/stubs/gdbstub.c b/stubs/gdbstub.c new file mode 100644 index 0000000000..c1dbfe7fb7 --- /dev/null +++ b/stubs/gdbstub.c @@ -0,0 +1,5 @@ +#include "qemu-common.h" + +const char *const xml_builtin[][2] = { + { NULL, NULL } +}; diff --git a/target-alpha/Makefile.objs b/target-alpha/Makefile.objs index 590304cc61..b96c5da98d 100644 --- a/target-alpha/Makefile.objs +++ b/target-alpha/Makefile.objs @@ -1,3 +1,4 @@ obj-$(CONFIG_SOFTMMU) += machine.o obj-y += translate.o helper.o cpu.o obj-y += int_helper.o fpu_helper.o sys_helper.o mem_helper.o +obj-y += gdbstub.o diff --git a/target-alpha/cpu-qom.h b/target-alpha/cpu-qom.h index b2eeba36f3..2ebc9bcacb 100644 --- a/target-alpha/cpu-qom.h +++ b/target-alpha/cpu-qom.h @@ -82,5 +82,7 @@ void alpha_cpu_do_interrupt(CPUState *cpu); void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int alpha_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #endif diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index c8c8c2c861..cfad2ea121 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -33,8 +33,11 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value) static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) { + CPUState *cs = CPU(dev); AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev); + qemu_init_vcpu(cs); + acc->parent_realize(dev, errp); } @@ -271,11 +274,14 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) cc->do_interrupt = alpha_cpu_do_interrupt; cc->dump_state = alpha_cpu_dump_state; cc->set_pc = alpha_cpu_set_pc; + cc->gdb_read_register = alpha_cpu_gdb_read_register; + cc->gdb_write_register = alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->do_unassigned_access = alpha_cpu_unassigned_access; cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug; dc->vmsd = &vmstate_alpha_cpu; #endif + cc->gdb_num_core_regs = 67; } static const TypeInfo alpha_cpu_type_info = { diff --git a/target-alpha/gdbstub.c b/target-alpha/gdbstub.c new file mode 100644 index 0000000000..980f140e72 --- /dev/null +++ b/target-alpha/gdbstub.c @@ -0,0 +1,93 @@ +/* + * Alpha gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" + +int alpha_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + AlphaCPU *cpu = ALPHA_CPU(cs); + CPUAlphaState *env = &cpu->env; + uint64_t val; + CPU_DoubleU d; + + switch (n) { + case 0 ... 30: + val = env->ir[n]; + break; + case 32 ... 62: + d.d = env->fir[n - 32]; + val = d.ll; + break; + case 63: + val = cpu_alpha_load_fpcr(env); + break; + case 64: + val = env->pc; + break; + case 66: + val = env->unique; + break; + case 31: + case 65: + /* 31 really is the zero register; 65 is unassigned in the + gdb protocol, but is still required to occupy 8 bytes. */ + val = 0; + break; + default: + return 0; + } + return gdb_get_regl(mem_buf, val); +} + +int alpha_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + AlphaCPU *cpu = ALPHA_CPU(cs); + CPUAlphaState *env = &cpu->env; + target_ulong tmp = ldtul_p(mem_buf); + CPU_DoubleU d; + + switch (n) { + case 0 ... 30: + env->ir[n] = tmp; + break; + case 32 ... 62: + d.ll = tmp; + env->fir[n - 32] = d.d; + break; + case 63: + cpu_alpha_store_fpcr(env, tmp); + break; + case 64: + env->pc = tmp; + break; + case 66: + env->unique = tmp; + break; + case 31: + case 65: + /* 31 really is the zero register; 65 is unassigned in the + gdb protocol, but is still required to occupy 8 bytes. */ + break; + default: + return 0; + } + return 8; +} diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs index 4a6e52e528..2d9f77fa9b 100644 --- a/target-arm/Makefile.objs +++ b/target-arm/Makefile.objs @@ -4,3 +4,4 @@ obj-$(CONFIG_KVM) += kvm.o obj-$(CONFIG_NO_KVM) += kvm-stub.o obj-y += translate.o op_helper.o helper.o cpu.o obj-y += neon_helper.o iwmmxt_helper.o +obj-y += gdbstub.o diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 02162c9aba..cf3658714e 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -149,4 +149,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, hwaddr arm_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); + #endif diff --git a/target-arm/cpu.c b/target-arm/cpu.c index d3906a4829..5a7566b8fc 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -159,6 +159,7 @@ static void arm_cpu_finalizefn(Object *obj) static void arm_cpu_realizefn(DeviceState *dev, Error **errp) { + CPUState *cs = CPU(dev); ARMCPU *cpu = ARM_CPU(dev); ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); CPUARMState *env = &cpu->env; @@ -214,7 +215,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) init_cpreg_list(cpu); - cpu_reset(CPU(cpu)); + cpu_reset(cs); + qemu_init_vcpu(cs); acc->parent_realize(dev, errp); } @@ -824,10 +826,14 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->do_interrupt = arm_cpu_do_interrupt; cc->dump_state = arm_cpu_dump_state; cc->set_pc = arm_cpu_set_pc; + cc->gdb_read_register = arm_cpu_gdb_read_register; + cc->gdb_write_register = arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; cc->vmsd = &vmstate_arm_cpu; #endif + cc->gdb_num_core_regs = 26; + cc->gdb_core_xml_file = "arm-core.xml"; } static void cpu_register(const ARMCPUInfo *info) diff --git a/target-arm/gdbstub.c b/target-arm/gdbstub.c new file mode 100644 index 0000000000..1c3439654f --- /dev/null +++ b/target-arm/gdbstub.c @@ -0,0 +1,102 @@ +/* + * ARM gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" + +/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect + whatever the target description contains. Due to a historical mishap + the FPA registers appear in between core integer regs and the CPSR. + We hack round this by giving the FPA regs zero size when talking to a + newer gdb. */ + +int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + + if (n < 16) { + /* Core integer register. */ + return gdb_get_reg32(mem_buf, env->regs[n]); + } + if (n < 24) { + /* FPA registers. */ + if (gdb_has_xml) { + return 0; + } + memset(mem_buf, 0, 12); + return 12; + } + switch (n) { + case 24: + /* FPA status register. */ + if (gdb_has_xml) { + return 0; + } + return gdb_get_reg32(mem_buf, 0); + case 25: + /* CPSR */ + return gdb_get_reg32(mem_buf, cpsr_read(env)); + } + /* Unknown register. */ + return 0; +} + +int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + uint32_t tmp; + + tmp = ldl_p(mem_buf); + + /* Mask out low bit of PC to workaround gdb bugs. This will probably + cause problems if we ever implement the Jazelle DBX extensions. */ + if (n == 15) { + tmp &= ~1; + } + + if (n < 16) { + /* Core integer register. */ + env->regs[n] = tmp; + return 4; + } + if (n < 24) { /* 16-23 */ + /* FPA registers (ignored). */ + if (gdb_has_xml) { + return 0; + } + return 12; + } + switch (n) { + case 24: + /* FPA status register (ignored). */ + if (gdb_has_xml) { + return 0; + } + return 4; + case 25: + /* CPSR */ + cpsr_write(env, tmp, 0xffffffff); + return 4; + } + /* Unknown register. */ + return 0; +} diff --git a/target-arm/helper.c b/target-arm/helper.c index b0c3ca1fbe..4968391b83 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1653,7 +1653,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, "was %s, now %s\n", r2->cp, 32 + 32 * is64, r2->crn, r2->crm, r2->opc1, r2->opc2, oldreg->name, r2->name); - assert(0); + g_assert_not_reached(); } } g_hash_table_insert(cpu->cp_regs, key, r2); diff --git a/target-cris/Makefile.objs b/target-cris/Makefile.objs index afb87bcc80..7779227fc4 100644 --- a/target-cris/Makefile.objs +++ b/target-cris/Makefile.objs @@ -1,2 +1,3 @@ obj-y += translate.o op_helper.o helper.o cpu.o +obj-y += gdbstub.o obj-$(CONFIG_SOFTMMU) += mmu.o machine.o diff --git a/target-cris/cpu-qom.h b/target-cris/cpu-qom.h index d7baf0746a..75593667d6 100644 --- a/target-cris/cpu-qom.h +++ b/target-cris/cpu-qom.h @@ -81,4 +81,8 @@ void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int crisv10_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int cris_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); + #endif diff --git a/target-cris/cpu.c b/target-cris/cpu.c index ba095e75a5..44301a4b10 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -137,10 +137,11 @@ void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf) static void cris_cpu_realizefn(DeviceState *dev, Error **errp) { - CRISCPU *cpu = CRIS_CPU(dev); + CPUState *cs = CPU(dev); CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev); - cpu_reset(CPU(cpu)); + cpu_reset(cs); + qemu_init_vcpu(cs); ccc->parent_realize(dev, errp); } @@ -175,6 +176,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void *data) ccc->vr = 8; cc->do_interrupt = crisv10_cpu_do_interrupt; + cc->gdb_read_register = crisv10_cpu_gdb_read_register; } static void crisv9_cpu_class_init(ObjectClass *oc, void *data) @@ -184,6 +186,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void *data) ccc->vr = 9; cc->do_interrupt = crisv10_cpu_do_interrupt; + cc->gdb_read_register = crisv10_cpu_gdb_read_register; } static void crisv10_cpu_class_init(ObjectClass *oc, void *data) @@ -193,6 +196,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, void *data) ccc->vr = 10; cc->do_interrupt = crisv10_cpu_do_interrupt; + cc->gdb_read_register = crisv10_cpu_gdb_read_register; } static void crisv11_cpu_class_init(ObjectClass *oc, void *data) @@ -202,6 +206,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data) ccc->vr = 11; cc->do_interrupt = crisv10_cpu_do_interrupt; + cc->gdb_read_register = crisv10_cpu_gdb_read_register; } static void crisv32_cpu_class_init(ObjectClass *oc, void *data) @@ -255,9 +260,13 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) cc->do_interrupt = cris_cpu_do_interrupt; cc->dump_state = cris_cpu_dump_state; cc->set_pc = cris_cpu_set_pc; + cc->gdb_read_register = cris_cpu_gdb_read_register; + cc->gdb_write_register = cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; #endif + + cc->gdb_num_core_regs = 49; } static const TypeInfo cris_cpu_type_info = { diff --git a/target-cris/gdbstub.c b/target-cris/gdbstub.c new file mode 100644 index 0000000000..5db3683ab6 --- /dev/null +++ b/target-cris/gdbstub.c @@ -0,0 +1,130 @@ +/* + * CRIS gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" + +int crisv10_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + CRISCPU *cpu = CRIS_CPU(cs); + CPUCRISState *env = &cpu->env; + + if (n < 15) { + return gdb_get_reg32(mem_buf, env->regs[n]); + } + + if (n == 15) { + return gdb_get_reg32(mem_buf, env->pc); + } + + if (n < 32) { + switch (n) { + case 16: + return gdb_get_reg8(mem_buf, env->pregs[n - 16]); + case 17: + return gdb_get_reg8(mem_buf, env->pregs[n - 16]); + case 20: + case 21: + return gdb_get_reg16(mem_buf, env->pregs[n - 16]); + default: + if (n >= 23) { + return gdb_get_reg32(mem_buf, env->pregs[n - 16]); + } + break; + } + } + return 0; +} + +int cris_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + CRISCPU *cpu = CRIS_CPU(cs); + CPUCRISState *env = &cpu->env; + uint8_t srs; + + srs = env->pregs[PR_SRS]; + if (n < 16) { + return gdb_get_reg32(mem_buf, env->regs[n]); + } + + if (n >= 21 && n < 32) { + return gdb_get_reg32(mem_buf, env->pregs[n - 16]); + } + if (n >= 33 && n < 49) { + return gdb_get_reg32(mem_buf, env->sregs[srs][n - 33]); + } + switch (n) { + case 16: + return gdb_get_reg8(mem_buf, env->pregs[0]); + case 17: + return gdb_get_reg8(mem_buf, env->pregs[1]); + case 18: + return gdb_get_reg32(mem_buf, env->pregs[2]); + case 19: + return gdb_get_reg8(mem_buf, srs); + case 20: + return gdb_get_reg16(mem_buf, env->pregs[4]); + case 32: + return gdb_get_reg32(mem_buf, env->pc); + } + + return 0; +} + +int cris_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + CRISCPU *cpu = CRIS_CPU(cs); + CPUCRISState *env = &cpu->env; + uint32_t tmp; + + if (n > 49) { + return 0; + } + + tmp = ldl_p(mem_buf); + + if (n < 16) { + env->regs[n] = tmp; + } + + if (n >= 21 && n < 32) { + env->pregs[n - 16] = tmp; + } + + /* FIXME: Should support function regs be writable? */ + switch (n) { + case 16: + return 1; + case 17: + return 1; + case 18: + env->pregs[PR_PID] = tmp; + break; + case 19: + return 1; + case 20: + return 2; + case 32: + env->pc = tmp; + break; + } + + return 4; +} diff --git a/target-i386/Makefile.objs b/target-i386/Makefile.objs index c1d4f059da..3b629d4d39 100644 --- a/target-i386/Makefile.objs +++ b/target-i386/Makefile.objs @@ -1,6 +1,7 @@ obj-y += translate.o helper.o cpu.o obj-y += excp_helper.o fpu_helper.o cc_helper.o int_helper.o svm_helper.o obj-y += smm_helper.o misc_helper.o mem_helper.o seg_helper.o +obj-y += gdbstub.o obj-$(CONFIG_SOFTMMU) += machine.o arch_memory_mapping.o arch_dump.o obj-$(CONFIG_KVM) += kvm.o hyperv.o obj-$(CONFIG_NO_KVM) += kvm-stub.o diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index d928562c53..53b4c3439b 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -68,6 +68,13 @@ typedef struct X86CPU { /* Features that were filtered out because of missing host capabilities */ uint32_t filtered_features[FEATURE_WORDS]; + + /* Enable PMU CPUID bits. This can't be enabled by default yet because + * it doesn't have ABI stability guarantees, as it passes all PMU CPUID + * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel + * capabilities) directly to the guest. + */ + bool enable_pmu; } X86CPU; static inline X86CPU *x86_env_get_cpu(CPUX86State *env) @@ -106,4 +113,7 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); + #endif diff --git a/target-i386/cpu.c b/target-i386/cpu.c index cd350cb8e4..71ab91531d 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1475,9 +1475,11 @@ static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque, error_propagate(errp, err); } -static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name) +static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def, + const char *name) { x86_def_t *def; + Error *err = NULL; int i; if (name == NULL) { @@ -1485,6 +1487,8 @@ static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name) } if (kvm_enabled() && strcmp(name, "host") == 0) { kvm_cpu_fill_host(x86_cpu_def); + object_property_set_bool(OBJECT(cpu), true, "pmu", &err); + assert_no_error(err); return 0; } @@ -1742,7 +1746,7 @@ static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp) memset(def, 0, sizeof(*def)); - if (cpu_x86_find_by_name(def, name) < 0) { + if (cpu_x86_find_by_name(cpu, def, name) < 0) { error_setg(errp, "Unable to find CPU definition: %s", name); return; } @@ -2016,7 +2020,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 0xA: /* Architectural Performance Monitoring Leaf */ - if (kvm_enabled()) { + if (kvm_enabled() && cpu->enable_pmu) { KVMState *s = cs->kvm_state; *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX); @@ -2333,6 +2337,7 @@ static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { + CPUState *cs = CPU(dev); X86CPU *cpu = X86_CPU(dev); X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); CPUX86State *env = &cpu->env; @@ -2387,12 +2392,13 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #endif mce_init(cpu); + qemu_init_vcpu(cs); x86_cpu_apic_realize(cpu, &local_err); if (local_err != NULL) { goto out; } - cpu_reset(CPU(cpu)); + cpu_reset(cs); xcc->parent_realize(dev, &local_err); out: @@ -2520,6 +2526,11 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) cpu->env.eip = tb->pc - tb->cs_base; } +static Property x86_cpu_properties[] = { + DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), + DEFINE_PROP_END_OF_LIST() +}; + static void x86_cpu_common_class_init(ObjectClass *oc, void *data) { X86CPUClass *xcc = X86_CPU_CLASS(oc); @@ -2529,6 +2540,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) xcc->parent_realize = dc->realize; dc->realize = x86_cpu_realizefn; dc->bus_type = TYPE_ICC_BUS; + dc->props = x86_cpu_properties; xcc->parent_reset = cc->reset; cc->reset = x86_cpu_reset; @@ -2538,6 +2550,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->dump_state = x86_cpu_dump_state; cc->set_pc = x86_cpu_set_pc; cc->synchronize_from_tb = x86_cpu_synchronize_from_tb; + cc->gdb_read_register = x86_cpu_gdb_read_register; + cc->gdb_write_register = x86_cpu_gdb_write_register; cc->get_arch_id = x86_cpu_get_arch_id; cc->get_paging_enabled = x86_cpu_get_paging_enabled; #ifndef CONFIG_USER_ONLY @@ -2549,6 +2563,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote; cc->vmsd = &vmstate_x86_cpu; #endif + cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25; } static const TypeInfo x86_cpu_type_info = { diff --git a/target-i386/gdbstub.c b/target-i386/gdbstub.c new file mode 100644 index 0000000000..15bebeff89 --- /dev/null +++ b/target-i386/gdbstub.c @@ -0,0 +1,231 @@ +/* + * x86 gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" + +#ifdef TARGET_X86_64 +static const int gpr_map[16] = { + R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP, + 8, 9, 10, 11, 12, 13, 14, 15 +}; +#else +#define gpr_map gpr_map32 +#endif +static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; + +#define IDX_IP_REG CPU_NB_REGS +#define IDX_FLAGS_REG (IDX_IP_REG + 1) +#define IDX_SEG_REGS (IDX_FLAGS_REG + 1) +#define IDX_FP_REGS (IDX_SEG_REGS + 6) +#define IDX_XMM_REGS (IDX_FP_REGS + 16) +#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS) + +int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + + if (n < CPU_NB_REGS) { + if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { + return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]); + } else if (n < CPU_NB_REGS32) { + return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]); + } + } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) { +#ifdef USE_X86LDOUBLE + /* FIXME: byteswap float values - after fixing fpregs layout. */ + memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10); +#else + memset(mem_buf, 0, 10); +#endif + return 10; + } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { + n -= IDX_XMM_REGS; + if (n < CPU_NB_REGS32 || + (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) { + stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0)); + stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1)); + return 16; + } + } else { + switch (n) { + case IDX_IP_REG: + if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { + return gdb_get_reg64(mem_buf, env->eip); + } else { + return gdb_get_reg32(mem_buf, env->eip); + } + case IDX_FLAGS_REG: + return gdb_get_reg32(mem_buf, env->eflags); + + case IDX_SEG_REGS: + return gdb_get_reg32(mem_buf, env->segs[R_CS].selector); + case IDX_SEG_REGS + 1: + return gdb_get_reg32(mem_buf, env->segs[R_SS].selector); + case IDX_SEG_REGS + 2: + return gdb_get_reg32(mem_buf, env->segs[R_DS].selector); + case IDX_SEG_REGS + 3: + return gdb_get_reg32(mem_buf, env->segs[R_ES].selector); + case IDX_SEG_REGS + 4: + return gdb_get_reg32(mem_buf, env->segs[R_FS].selector); + case IDX_SEG_REGS + 5: + return gdb_get_reg32(mem_buf, env->segs[R_GS].selector); + + case IDX_FP_REGS + 8: + return gdb_get_reg32(mem_buf, env->fpuc); + case IDX_FP_REGS + 9: + return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) | + (env->fpstt & 0x7) << 11); + case IDX_FP_REGS + 10: + return gdb_get_reg32(mem_buf, 0); /* ftag */ + case IDX_FP_REGS + 11: + return gdb_get_reg32(mem_buf, 0); /* fiseg */ + case IDX_FP_REGS + 12: + return gdb_get_reg32(mem_buf, 0); /* fioff */ + case IDX_FP_REGS + 13: + return gdb_get_reg32(mem_buf, 0); /* foseg */ + case IDX_FP_REGS + 14: + return gdb_get_reg32(mem_buf, 0); /* fooff */ + case IDX_FP_REGS + 15: + return gdb_get_reg32(mem_buf, 0); /* fop */ + + case IDX_MXCSR_REG: + return gdb_get_reg32(mem_buf, env->mxcsr); + } + } + return 0; +} + +static int x86_cpu_gdb_load_seg(X86CPU *cpu, int sreg, uint8_t *mem_buf) +{ + CPUX86State *env = &cpu->env; + uint16_t selector = ldl_p(mem_buf); + + if (selector != env->segs[sreg].selector) { +#if defined(CONFIG_USER_ONLY) + cpu_x86_load_seg(env, sreg, selector); +#else + unsigned int limit, flags; + target_ulong base; + + if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { + base = selector << 4; + limit = 0xffff; + flags = 0; + } else { + if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, + &flags)) { + return 4; + } + } + cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags); +#endif + } + return 4; +} + +int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + uint32_t tmp; + + if (n < CPU_NB_REGS) { + if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { + env->regs[gpr_map[n]] = ldtul_p(mem_buf); + return sizeof(target_ulong); + } else if (n < CPU_NB_REGS32) { + n = gpr_map32[n]; + env->regs[n] &= ~0xffffffffUL; + env->regs[n] |= (uint32_t)ldl_p(mem_buf); + return 4; + } + } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) { +#ifdef USE_X86LDOUBLE + /* FIXME: byteswap float values - after fixing fpregs layout. */ + memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10); +#endif + return 10; + } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { + n -= IDX_XMM_REGS; + if (n < CPU_NB_REGS32 || + (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) { + env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf); + env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8); + return 16; + } + } else { + switch (n) { + case IDX_IP_REG: + if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { + env->eip = ldq_p(mem_buf); + return 8; + } else { + env->eip &= ~0xffffffffUL; + env->eip |= (uint32_t)ldl_p(mem_buf); + return 4; + } + case IDX_FLAGS_REG: + env->eflags = ldl_p(mem_buf); + return 4; + + case IDX_SEG_REGS: + return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf); + case IDX_SEG_REGS + 1: + return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf); + case IDX_SEG_REGS + 2: + return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf); + case IDX_SEG_REGS + 3: + return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf); + case IDX_SEG_REGS + 4: + return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf); + case IDX_SEG_REGS + 5: + return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf); + + case IDX_FP_REGS + 8: + env->fpuc = ldl_p(mem_buf); + return 4; + case IDX_FP_REGS + 9: + tmp = ldl_p(mem_buf); + env->fpstt = (tmp >> 11) & 7; + env->fpus = tmp & ~0x3800; + return 4; + case IDX_FP_REGS + 10: /* ftag */ + return 4; + case IDX_FP_REGS + 11: /* fiseg */ + return 4; + case IDX_FP_REGS + 12: /* fioff */ + return 4; + case IDX_FP_REGS + 13: /* foseg */ + return 4; + case IDX_FP_REGS + 14: /* fooff */ + return 4; + case IDX_FP_REGS + 15: /* fop */ + return 4; + + case IDX_MXCSR_REG: + env->mxcsr = ldl_p(mem_buf); + return 4; + } + } + /* Unrecognised register. */ + return 0; +} diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 3c9d10a762..376fc70ae3 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1618,7 +1618,7 @@ static int kvm_guest_debug_workarounds(X86CPU *cpu) */ if (reinject_trap || (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) { - ret = kvm_update_guest_debug(env, reinject_trap); + ret = kvm_update_guest_debug(cs, reinject_trap); } return ret; } diff --git a/target-lm32/Makefile.objs b/target-lm32/Makefile.objs index ca20f21443..40236876c8 100644 --- a/target-lm32/Makefile.objs +++ b/target-lm32/Makefile.objs @@ -1,2 +1,3 @@ obj-y += translate.o op_helper.o helper.o cpu.o +obj-y += gdbstub.o obj-$(CONFIG_SOFTMMU) += machine.o diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h index 9e2732919d..723f6049c3 100644 --- a/target-lm32/cpu-qom.h +++ b/target-lm32/cpu-qom.h @@ -79,5 +79,7 @@ void lm32_cpu_do_interrupt(CPUState *cpu); void lm32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int lm32_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int lm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #endif diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index ce55e4807d..869878c04a 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -46,10 +46,12 @@ static void lm32_cpu_reset(CPUState *s) static void lm32_cpu_realizefn(DeviceState *dev, Error **errp) { - LM32CPU *cpu = LM32_CPU(dev); + CPUState *cs = CPU(dev); LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev); - cpu_reset(CPU(cpu)); + cpu_reset(cs); + + qemu_init_vcpu(cs); lcc->parent_realize(dev, errp); } @@ -87,10 +89,13 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) cc->do_interrupt = lm32_cpu_do_interrupt; cc->dump_state = lm32_cpu_dump_state; cc->set_pc = lm32_cpu_set_pc; + cc->gdb_read_register = lm32_cpu_gdb_read_register; + cc->gdb_write_register = lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug; cc->vmsd = &vmstate_lm32_cpu; #endif + cc->gdb_num_core_regs = 32 + 7; } static const TypeInfo lm32_cpu_type_info = { diff --git a/target-lm32/gdbstub.c b/target-lm32/gdbstub.c new file mode 100644 index 0000000000..4979a98d74 --- /dev/null +++ b/target-lm32/gdbstub.c @@ -0,0 +1,92 @@ +/* + * LM32 gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" +#include "hw/lm32/lm32_pic.h" + +int lm32_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + LM32CPU *cpu = LM32_CPU(cs); + CPULM32State *env = &cpu->env; + + if (n < 32) { + return gdb_get_reg32(mem_buf, env->regs[n]); + } else { + switch (n) { + case 32: + return gdb_get_reg32(mem_buf, env->pc); + /* FIXME: put in right exception ID */ + case 33: + return gdb_get_reg32(mem_buf, 0); + case 34: + return gdb_get_reg32(mem_buf, env->eba); + case 35: + return gdb_get_reg32(mem_buf, env->deba); + case 36: + return gdb_get_reg32(mem_buf, env->ie); + case 37: + return gdb_get_reg32(mem_buf, lm32_pic_get_im(env->pic_state)); + case 38: + return gdb_get_reg32(mem_buf, lm32_pic_get_ip(env->pic_state)); + } + } + return 0; +} + +int lm32_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + LM32CPU *cpu = LM32_CPU(cs); + CPUClass *cc = CPU_GET_CLASS(cs); + CPULM32State *env = &cpu->env; + uint32_t tmp; + + if (n > cc->gdb_num_core_regs) { + return 0; + } + + tmp = ldl_p(mem_buf); + + if (n < 32) { + env->regs[n] = tmp; + } else { + switch (n) { + case 32: + env->pc = tmp; + break; + case 34: + env->eba = tmp; + break; + case 35: + env->deba = tmp; + break; + case 36: + env->ie = tmp; + break; + case 37: + lm32_pic_set_im(env->pic_state, tmp); + break; + case 38: + lm32_pic_set_ip(env->pic_state, tmp); + break; + } + } + return 4; +} diff --git a/target-m68k/Makefile.objs b/target-m68k/Makefile.objs index 2e2b85044d..02cf616a78 100644 --- a/target-m68k/Makefile.objs +++ b/target-m68k/Makefile.objs @@ -1,2 +1,3 @@ obj-y += m68k-semi.o obj-y += translate.o op_helper.o helper.o cpu.o +obj-y += gdbstub.o diff --git a/target-m68k/cpu-qom.h b/target-m68k/cpu-qom.h index 7115707e91..7f388eda68 100644 --- a/target-m68k/cpu-qom.h +++ b/target-m68k/cpu-qom.h @@ -74,5 +74,7 @@ void m68k_cpu_do_interrupt(CPUState *cpu); void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #endif diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index 988f476257..008d8db2da 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -143,12 +143,14 @@ static const M68kCPUInfo m68k_cpus[] = { static void m68k_cpu_realizefn(DeviceState *dev, Error **errp) { + CPUState *cs = CPU(dev); M68kCPU *cpu = M68K_CPU(dev); M68kCPUClass *mcc = M68K_CPU_GET_CLASS(dev); m68k_cpu_init_gdb(cpu); - cpu_reset(CPU(cpu)); + cpu_reset(cs); + qemu_init_vcpu(cs); mcc->parent_realize(dev, errp); } @@ -190,10 +192,14 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) cc->do_interrupt = m68k_cpu_do_interrupt; cc->dump_state = m68k_cpu_dump_state; cc->set_pc = m68k_cpu_set_pc; + cc->gdb_read_register = m68k_cpu_gdb_read_register; + cc->gdb_write_register = m68k_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug; #endif dc->vmsd = &vmstate_m68k_cpu; + cc->gdb_num_core_regs = 18; + cc->gdb_core_xml_file = "cf-core.xml"; } static void register_cpu_type(const M68kCPUInfo *info) diff --git a/target-m68k/gdbstub.c b/target-m68k/gdbstub.c new file mode 100644 index 0000000000..ae8179c016 --- /dev/null +++ b/target-m68k/gdbstub.c @@ -0,0 +1,75 @@ +/* + * m68k gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" + +int m68k_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + M68kCPU *cpu = M68K_CPU(cs); + CPUM68KState *env = &cpu->env; + + if (n < 8) { + /* D0-D7 */ + return gdb_get_reg32(mem_buf, env->dregs[n]); + } else if (n < 16) { + /* A0-A7 */ + return gdb_get_reg32(mem_buf, env->aregs[n - 8]); + } else { + switch (n) { + case 16: + return gdb_get_reg32(mem_buf, env->sr); + case 17: + return gdb_get_reg32(mem_buf, env->pc); + } + } + /* FP registers not included here because they vary between + ColdFire and m68k. Use XML bits for these. */ + return 0; +} + +int m68k_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + M68kCPU *cpu = M68K_CPU(cs); + CPUM68KState *env = &cpu->env; + uint32_t tmp; + + tmp = ldl_p(mem_buf); + + if (n < 8) { + /* D0-D7 */ + env->dregs[n] = tmp; + } else if (n < 16) { + /* A0-A7 */ + env->aregs[n - 8] = tmp; + } else { + switch (n) { + case 16: + env->sr = tmp; + break; + case 17: + env->pc = tmp; + break; + default: + return 0; + } + } + return 4; +} diff --git a/target-microblaze/Makefile.objs b/target-microblaze/Makefile.objs index 985330eac5..f3d7b44c89 100644 --- a/target-microblaze/Makefile.objs +++ b/target-microblaze/Makefile.objs @@ -1,2 +1,3 @@ obj-y += translate.o op_helper.o helper.o cpu.o +obj-y += gdbstub.o obj-$(CONFIG_SOFTMMU) += mmu.o diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index 1318a36676..35a12b42a5 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -75,5 +75,7 @@ void mb_cpu_do_interrupt(CPUState *cs); void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #endif diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 9f10c8c778..0ef9aa4b74 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -90,10 +90,11 @@ static void mb_cpu_reset(CPUState *s) static void mb_cpu_realizefn(DeviceState *dev, Error **errp) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(dev); + CPUState *cs = CPU(dev); MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); - cpu_reset(CPU(cpu)); + cpu_reset(cs); + qemu_init_vcpu(cs); mcc->parent_realize(dev, errp); } @@ -141,12 +142,15 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->do_interrupt = mb_cpu_do_interrupt; cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; + cc->gdb_read_register = mb_cpu_gdb_read_register; + cc->gdb_write_register = mb_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->do_unassigned_access = mb_cpu_unassigned_access; cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; #endif dc->vmsd = &vmstate_mb_cpu; dc->props = mb_properties; + cc->gdb_num_core_regs = 32 + 5; } static const TypeInfo mb_cpu_type_info = { diff --git a/target-microblaze/gdbstub.c b/target-microblaze/gdbstub.c new file mode 100644 index 0000000000..a70e2ee3cb --- /dev/null +++ b/target-microblaze/gdbstub.c @@ -0,0 +1,56 @@ +/* + * MicroBlaze gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" + +int mb_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = &cpu->env; + + if (n < 32) { + return gdb_get_reg32(mem_buf, env->regs[n]); + } else { + return gdb_get_reg32(mem_buf, env->sregs[n - 32]); + } + return 0; +} + +int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUClass *cc = CPU_GET_CLASS(cs); + CPUMBState *env = &cpu->env; + uint32_t tmp; + + if (n > cc->gdb_num_core_regs) { + return 0; + } + + tmp = ldl_p(mem_buf); + + if (n < 32) { + env->regs[n] = tmp; + } else { + env->sregs[n - 32] = tmp; + } + return 4; +} diff --git a/target-mips/Makefile.objs b/target-mips/Makefile.objs index 119c816518..0277d56e82 100644 --- a/target-mips/Makefile.objs +++ b/target-mips/Makefile.objs @@ -1,2 +1,3 @@ obj-y += translate.o dsp_helper.o op_helper.o lmi_helper.o helper.o cpu.o +obj-y += gdbstub.o obj-$(CONFIG_SOFTMMU) += machine.o diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h index 7c8e616392..8877f813f7 100644 --- a/target-mips/cpu-qom.h +++ b/target-mips/cpu-qom.h @@ -78,5 +78,7 @@ void mips_cpu_do_interrupt(CPUState *cpu); void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #endif diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 4834c86d02..9dd47e84f7 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -62,10 +62,11 @@ static void mips_cpu_reset(CPUState *s) static void mips_cpu_realizefn(DeviceState *dev, Error **errp) { - MIPSCPU *cpu = MIPS_CPU(dev); + CPUState *cs = CPU(dev); MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); - cpu_reset(CPU(cpu)); + cpu_reset(cs); + qemu_init_vcpu(cs); mcc->parent_realize(dev, errp); } @@ -100,10 +101,14 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->dump_state = mips_cpu_dump_state; cc->set_pc = mips_cpu_set_pc; cc->synchronize_from_tb = mips_cpu_synchronize_from_tb; + cc->gdb_read_register = mips_cpu_gdb_read_register; + cc->gdb_write_register = mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->do_unassigned_access = mips_cpu_unassigned_access; cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; #endif + + cc->gdb_num_core_regs = 73; } static const TypeInfo mips_cpu_type_info = { diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 4116de93c3..b088a25017 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -390,7 +390,7 @@ static inline int32_t mipsdsp_mul_q15_q15_overflowflag21(uint16_t a, uint16_t b, temp = 0x7FFFFFFF; set_DSPControl_overflow_flag(1, 21, env); } else { - temp = ((int32_t)(int16_t)a * (int32_t)(int16_t)b) << 1; + temp = ((int16_t)a * (int16_t)b) << 1; } return temp; @@ -583,7 +583,7 @@ static inline int64_t mipsdsp_mul_q31_q31(int32_t ac, uint32_t a, uint32_t b, temp = (0x01ull << 63) - 1; set_DSPControl_overflow_flag(1, 16 + ac, env); } else { - temp = ((uint64_t)a * (uint64_t)b) << 1; + temp = ((int64_t)(int32_t)a * (int32_t)b) << 1; } return temp; @@ -622,7 +622,7 @@ static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b, temp = 0x7FFF0000; set_DSPControl_overflow_flag(1, 21, env); } else { - temp = (a * b) << 1; + temp = ((int16_t)a * (int16_t)b) << 1; temp = temp + 0x00008000; } @@ -648,16 +648,22 @@ static inline int32_t mipsdsp_sat16_mul_q15_q15(uint16_t a, uint16_t b, static inline uint16_t mipsdsp_trunc16_sat16_round(int32_t a, CPUMIPSState *env) { - int64_t temp; + uint16_t temp; - temp = (int32_t)a + 0x00008000; - if (a > (int)0x7fff8000) { - temp = 0x7FFFFFFF; + /* + * The value 0x00008000 will be added to the input Q31 value, and the code + * needs to check if the addition causes an overflow. Since a positive value + * is added, overflow can happen in one direction only. + */ + if (a > 0x7FFF7FFF) { + temp = 0x7FFF; set_DSPControl_overflow_flag(1, 22, env); + } else { + temp = ((a + 0x8000) >> 16) & 0xFFFF; } - return (temp >> 16) & 0xFFFF; + return temp; } static inline uint8_t mipsdsp_sat8_reduce_precision(uint16_t a, diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c new file mode 100644 index 0000000000..5b72d58a44 --- /dev/null +++ b/target-mips/gdbstub.c @@ -0,0 +1,155 @@ +/* + * MIPS gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" + +int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + + if (n < 32) { + return gdb_get_regl(mem_buf, env->active_tc.gpr[n]); + } + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + if (n >= 38 && n < 70) { + if (env->CP0_Status & (1 << CP0St_FR)) { + return gdb_get_regl(mem_buf, + env->active_fpu.fpr[n - 38].d); + } else { + return gdb_get_regl(mem_buf, + env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); + } + } + switch (n) { + case 70: + return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31); + case 71: + return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0); + } + } + switch (n) { + case 32: + return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status); + case 33: + return gdb_get_regl(mem_buf, env->active_tc.LO[0]); + case 34: + return gdb_get_regl(mem_buf, env->active_tc.HI[0]); + case 35: + return gdb_get_regl(mem_buf, env->CP0_BadVAddr); + case 36: + return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause); + case 37: + return gdb_get_regl(mem_buf, env->active_tc.PC | + !!(env->hflags & MIPS_HFLAG_M16)); + case 72: + return gdb_get_regl(mem_buf, 0); /* fp */ + case 89: + return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid); + } + if (n >= 73 && n <= 88) { + /* 16 embedded regs. */ + return gdb_get_regl(mem_buf, 0); + } + + return 0; +} + +/* convert MIPS rounding mode in FCR31 to IEEE library */ +static unsigned int ieee_rm[] = { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down +}; +#define RESTORE_ROUNDING_MODE \ + set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], \ + &env->active_fpu.fp_status) + +int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + target_ulong tmp; + + tmp = ldtul_p(mem_buf); + + if (n < 32) { + env->active_tc.gpr[n] = tmp; + return sizeof(target_ulong); + } + if (env->CP0_Config1 & (1 << CP0C1_FP) + && n >= 38 && n < 73) { + if (n < 70) { + if (env->CP0_Status & (1 << CP0St_FR)) { + env->active_fpu.fpr[n - 38].d = tmp; + } else { + env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; + } + } + switch (n) { + case 70: + env->active_fpu.fcr31 = tmp & 0xFF83FFFF; + /* set rounding mode */ + RESTORE_ROUNDING_MODE; + break; + case 71: + env->active_fpu.fcr0 = tmp; + break; + } + return sizeof(target_ulong); + } + switch (n) { + case 32: + env->CP0_Status = tmp; + break; + case 33: + env->active_tc.LO[0] = tmp; + break; + case 34: + env->active_tc.HI[0] = tmp; + break; + case 35: + env->CP0_BadVAddr = tmp; + break; + case 36: + env->CP0_Cause = tmp; + break; + case 37: + env->active_tc.PC = tmp & ~(target_ulong)1; + if (tmp & 1) { + env->hflags |= MIPS_HFLAG_M16; + } else { + env->hflags &= ~(MIPS_HFLAG_M16); + } + break; + case 72: /* fp, ignored */ + break; + default: + if (n > 89) { + return 0; + } + /* Other registers are readonly. Ignore writes. */ + break; + } + + return sizeof(target_ulong); +} diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 5cf1c3f04b..b828375714 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1735,7 +1735,6 @@ target_ulong helper_evpe(CPUMIPSState *env) void helper_fork(target_ulong arg1, target_ulong arg2) { // arg1 = rt, arg2 = rs - arg1 = 0; // TODO: store to TC register } diff --git a/target-mips/translate.c b/target-mips/translate.c index 877f8dfe88..c1d57a791e 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -9571,8 +9571,7 @@ static void decode_i64_mips16 (DisasContext *ctx, } #endif -static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx, - int *is_branch) +static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx) { int extend = cpu_lduw_code(env, ctx->pc + 2); int op, rx, ry, funct, sa; @@ -9763,8 +9762,7 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx, return 4; } -static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, - int *is_branch) +static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) { int rx, ry; int sa; @@ -9807,7 +9805,6 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, op = ((ctx->opcode >> 10) & 0x1) ? OPC_JALXS : OPC_JALS; gen_compute_branch(ctx, op, 4, rx, ry, offset); n_bytes = 4; - *is_branch = 1; break; case M16_OPC_BEQZ: gen_compute_branch(ctx, OPC_BEQ, 2, rx, 0, ((int8_t)ctx->opcode) << 1); @@ -10046,9 +10043,6 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, } gen_compute_branch(ctx, op, 2, ra ? 31 : rx, 31, 0); - if (!nd) { - *is_branch = 1; - } } break; case RR_SDBBP: @@ -10193,7 +10187,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, } break; case M16_OPC_EXTEND: - decode_extended_mips16_opc(env, ctx, is_branch); + decode_extended_mips16_opc(env, ctx); n_bytes = 4; break; #if defined(TARGET_MIPS64) @@ -10802,7 +10796,7 @@ static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist, } -static void gen_pool16c_insn(DisasContext *ctx, int *is_branch) +static void gen_pool16c_insn(DisasContext *ctx) { int rd = mmreg((ctx->opcode >> 3) & 0x7); int rs = mmreg(ctx->opcode & 0x7); @@ -10864,7 +10858,6 @@ static void gen_pool16c_insn(DisasContext *ctx, int *is_branch) gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0); } - *is_branch = 1; break; case JRC16 + 0: case JRC16 + 1: @@ -10889,7 +10882,6 @@ static void gen_pool16c_insn(DisasContext *ctx, int *is_branch) gen_compute_branch(ctx, opc, 2, reg, 31, 0); } - *is_branch = 1; break; case MFHI16 + 0: case MFHI16 + 1: @@ -11020,8 +11012,7 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, tcg_temp_free(t1); } -static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs, - int *is_branch) +static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) { int extension = (ctx->opcode >> 6) & 0x3f; int minor = (ctx->opcode >> 12) & 0xf; @@ -11147,12 +11138,10 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs, case JALR: case JALR_HB: gen_compute_branch (ctx, OPC_JALR, 4, rs, rt, 0); - *is_branch = 1; break; case JALRS: case JALRS_HB: gen_compute_branch (ctx, OPC_JALRS, 4, rs, rt, 0); - *is_branch = 1; break; default: goto pool32axf_invalid; @@ -11551,7 +11540,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs) } static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, - uint16_t insn_hw1, int *is_branch) + uint16_t insn_hw1) { int32_t offset; uint16_t insn; @@ -11685,7 +11674,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd); return; case POOL32AXF: - gen_pool32axf(env, ctx, rt, rs, is_branch); + gen_pool32axf(env, ctx, rt, rs); break; case 0x07: generate_exception(ctx, EXCP_BREAK); @@ -12048,7 +12037,6 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, mips32_op = OPC_BGTZ; do_branch: gen_compute_branch(ctx, mips32_op, 4, rs, -1, imm << 1); - *is_branch = 1; break; /* Traps */ @@ -12109,7 +12097,6 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, do_cp1branch: gen_compute_branch1(ctx, mips32_op, (ctx->opcode >> 18) & 0x7, imm << 1); - *is_branch = 1; break; case BPOSGE64: case BPOSGE32: @@ -12216,30 +12203,24 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case JALX32: offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset); - *is_branch = 1; break; case JALS32: offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 1; gen_compute_branch(ctx, OPC_JALS, 4, rt, rs, offset); - *is_branch = 1; break; case BEQ32: gen_compute_branch(ctx, OPC_BEQ, 4, rt, rs, imm << 1); - *is_branch = 1; break; case BNE32: gen_compute_branch(ctx, OPC_BNE, 4, rt, rs, imm << 1); - *is_branch = 1; break; case J32: gen_compute_branch(ctx, OPC_J, 4, rt, rs, (int32_t)(ctx->opcode & 0x3FFFFFF) << 1); - *is_branch = 1; break; case JAL32: gen_compute_branch(ctx, OPC_JAL, 4, rt, rs, (int32_t)(ctx->opcode & 0x3FFFFFF) << 1); - *is_branch = 1; break; /* Floating point (COP1) */ case LWC132: @@ -12309,7 +12290,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, } } -static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) +static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx) { uint32_t op; @@ -12442,7 +12423,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b } break; case POOL16C: - gen_pool16c_insn(ctx, is_branch); + gen_pool16c_insn(ctx); break; case LWGP16: { @@ -12582,14 +12563,12 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b case B16: gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, SIMM(ctx->opcode, 0, 10) << 1); - *is_branch = 1; break; case BNEZ16: case BEQZ16: gen_compute_branch(ctx, op == BNEZ16 ? OPC_BNE : OPC_BEQ, 2, mmreg(uMIPS_RD(ctx->opcode)), 0, SIMM(ctx->opcode, 0, 7) << 1); - *is_branch = 1; break; case LI16: { @@ -12610,7 +12589,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b generate_exception(ctx, EXCP_RI); break; default: - decode_micromips32_opc (env, ctx, op, is_branch); + decode_micromips32_opc (env, ctx, op); return 4; } @@ -14346,7 +14325,7 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, /* End MIPSDSP functions. */ -static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) +static void decode_opc (CPUMIPSState *env, DisasContext *ctx) { int32_t offset; int rs, rt, rd, sa; @@ -14460,7 +14439,6 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; case OPC_JR ... OPC_JALR: gen_compute_branch(ctx, op1, 4, rs, rd, sa); - *is_branch = 1; break; case OPC_TGE ... OPC_TEQ: /* Traps */ case OPC_TNE: @@ -15227,7 +15205,6 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_BLTZ ... OPC_BGEZL: /* REGIMM branches */ case OPC_BLTZAL ... OPC_BGEZALL: gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2); - *is_branch = 1; break; case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */ case OPC_TNEI: @@ -15243,7 +15220,6 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) #endif check_dsp(ctx); gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2); - *is_branch = 1; break; default: /* Invalid */ MIPS_INVAL("regimm"); @@ -15355,12 +15331,10 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_J ... OPC_JAL: /* Jump */ offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; gen_compute_branch(ctx, op, 4, rs, rt, offset); - *is_branch = 1; break; case OPC_BEQ ... OPC_BGTZ: /* Branch */ case OPC_BEQL ... OPC_BGTZL: gen_compute_branch(ctx, op, 4, rs, rt, imm << 2); - *is_branch = 1; break; case OPC_LB ... OPC_LWR: /* Load and stores */ case OPC_LL: @@ -15420,7 +15394,6 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_BC1: gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), (rt >> 2) & 0x7, imm << 2); - *is_branch = 1; break; case OPC_S_FMT: case OPC_D_FMT: @@ -15527,7 +15500,6 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS); offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; gen_compute_branch(ctx, op, 4, rs, rt, offset); - *is_branch = 1; break; case OPC_MDMX: check_insn(ctx, ASE_MDMX); @@ -15553,7 +15525,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, int num_insns; int max_insns; int insn_bytes; - int is_branch; + int is_delay; if (search_pc) qemu_log("search pc %d\n", search_pc); @@ -15611,23 +15583,23 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); - is_branch = 0; + is_delay = ctx.hflags & MIPS_HFLAG_BMASK; if (!(ctx.hflags & MIPS_HFLAG_M16)) { ctx.opcode = cpu_ldl_code(env, ctx.pc); insn_bytes = 4; - decode_opc(env, &ctx, &is_branch); + decode_opc(env, &ctx); } else if (ctx.insn_flags & ASE_MICROMIPS) { ctx.opcode = cpu_lduw_code(env, ctx.pc); - insn_bytes = decode_micromips_opc(env, &ctx, &is_branch); + insn_bytes = decode_micromips_opc(env, &ctx); } else if (ctx.insn_flags & ASE_MIPS16) { ctx.opcode = cpu_lduw_code(env, ctx.pc); - insn_bytes = decode_mips16_opc(env, &ctx, &is_branch); + insn_bytes = decode_mips16_opc(env, &ctx); } else { generate_exception(&ctx, EXCP_RI); ctx.bstate = BS_STOP; break; } - if (!is_branch) { + if (is_delay) { handle_delay_slot(&ctx, insn_bytes); } ctx.pc += insn_bytes; diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index 6550be5b35..d97a091eb4 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -45,10 +45,11 @@ static void moxie_cpu_reset(CPUState *s) static void moxie_cpu_realizefn(DeviceState *dev, Error **errp) { - MoxieCPU *cpu = MOXIE_CPU(dev); + CPUState *cs = CPU(dev); MoxieCPUClass *mcc = MOXIE_CPU_GET_CLASS(dev); - cpu_reset(CPU(cpu)); + qemu_init_vcpu(cs); + cpu_reset(cs); mcc->parent_realize(dev, errp); } diff --git a/target-openrisc/Makefile.objs b/target-openrisc/Makefile.objs index 44dc5399df..397d01650e 100644 --- a/target-openrisc/Makefile.objs +++ b/target-openrisc/Makefile.objs @@ -2,3 +2,4 @@ obj-$(CONFIG_SOFTMMU) += machine.o obj-y += cpu.o exception.o interrupt.o mmu.o translate.o obj-y += exception_helper.o fpu_helper.o int_helper.o \ interrupt_helper.o mmu_helper.o sys_helper.o +obj-y += gdbstub.o diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 3da5a7a8b1..075f00a897 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -66,10 +66,11 @@ static inline void set_feature(OpenRISCCPU *cpu, int feature) static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) { - OpenRISCCPU *cpu = OPENRISC_CPU(dev); + CPUState *cs = CPU(dev); OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); - cpu_reset(CPU(cpu)); + qemu_init_vcpu(cs); + cpu_reset(cs); occ->parent_realize(dev, errp); } @@ -106,6 +107,7 @@ static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model); oc = object_class_by_name(typename); + g_free(typename); if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || object_class_is_abstract(oc))) { return NULL; @@ -154,10 +156,13 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) cc->do_interrupt = openrisc_cpu_do_interrupt; cc->dump_state = openrisc_cpu_dump_state; cc->set_pc = openrisc_cpu_set_pc; + cc->gdb_read_register = openrisc_cpu_gdb_read_register; + cc->gdb_write_register = openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; dc->vmsd = &vmstate_openrisc_cpu; #endif + cc->gdb_num_core_regs = 32 + 3; } static void cpu_register(const OpenRISCCPUInfo *info) diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 3ddb7674c7..8fd0bc0bf0 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -350,6 +350,8 @@ void openrisc_cpu_do_interrupt(CPUState *cpu); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env, target_ulong address, diff --git a/target-openrisc/gdbstub.c b/target-openrisc/gdbstub.c new file mode 100644 index 0000000000..18bcc46167 --- /dev/null +++ b/target-openrisc/gdbstub.c @@ -0,0 +1,83 @@ +/* + * OpenRISC gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" + +int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + OpenRISCCPU *cpu = OPENRISC_CPU(cs); + CPUOpenRISCState *env = &cpu->env; + + if (n < 32) { + return gdb_get_reg32(mem_buf, env->gpr[n]); + } else { + switch (n) { + case 32: /* PPC */ + return gdb_get_reg32(mem_buf, env->ppc); + + case 33: /* NPC */ + return gdb_get_reg32(mem_buf, env->npc); + + case 34: /* SR */ + return gdb_get_reg32(mem_buf, env->sr); + + default: + break; + } + } + return 0; +} + +int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + OpenRISCCPU *cpu = OPENRISC_CPU(cs); + CPUClass *cc = CPU_GET_CLASS(cs); + CPUOpenRISCState *env = &cpu->env; + uint32_t tmp; + + if (n > cc->gdb_num_core_regs) { + return 0; + } + + tmp = ldl_p(mem_buf); + + if (n < 32) { + env->gpr[n] = tmp; + } else { + switch (n) { + case 32: /* PPC */ + env->ppc = tmp; + break; + + case 33: /* NPC */ + env->npc = tmp; + break; + + case 34: /* SR */ + env->sr = tmp; + break; + + default: + break; + } + } + return 4; +} diff --git a/target-ppc/Makefile.objs b/target-ppc/Makefile.objs index 6e78cb3624..f72e3993f7 100644 --- a/target-ppc/Makefile.objs +++ b/target-ppc/Makefile.objs @@ -13,3 +13,4 @@ obj-y += timebase_helper.o obj-y += misc_helper.o obj-y += mem_helper.o obj-$(CONFIG_USER_ONLY) += user_only_helper.o +obj-y += gdbstub.o diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index 3341c5151d..f3c710a9e5 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -106,5 +106,11 @@ void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); + +#ifndef CONFIG_USER_ONLY +extern const struct VMStateDescription vmstate_ppc_cpu; +#endif #endif diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 6f51e1f526..711db083e0 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -948,7 +948,7 @@ struct CPUPPCState { #if defined(TARGET_PPC64) /* PowerPC 64 SLB area */ ppc_slb_t slb[64]; - int slb_nr; + int32_t slb_nr; #endif /* segment registers */ hwaddr htab_base; @@ -957,11 +957,11 @@ struct CPUPPCState { /* externally stored hash table */ uint8_t *external_htab; /* BATs */ - int nb_BATs; + uint32_t nb_BATs; target_ulong DBAT[2][8]; target_ulong IBAT[2][8]; /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */ - int nb_tlb; /* Total number of TLB */ + int32_t nb_tlb; /* Total number of TLB */ int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ int nb_ways; /* Number of ways in the TLB set */ int last_way; /* Last used way used to allocate TLB in a LRU way */ @@ -1176,8 +1176,6 @@ static inline CPUPPCState *cpu_init(const char *cpu_model) #define cpu_signal_handler cpu_ppc_signal_handler #define cpu_list ppc_cpu_list -#define CPU_SAVE_VERSION 4 - /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _user #define MMU_MODE1_SUFFIX _kernel diff --git a/target-ppc/gdbstub.c b/target-ppc/gdbstub.c new file mode 100644 index 0000000000..1c910902ea --- /dev/null +++ b/target-ppc/gdbstub.c @@ -0,0 +1,131 @@ +/* + * PowerPC gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" + +/* Old gdb always expects FP registers. Newer (xml-aware) gdb only + * expects whatever the target description contains. Due to a + * historical mishap the FP registers appear in between core integer + * regs and PC, MSR, CR, and so forth. We hack round this by giving the + * FP regs zero size when talking to a newer gdb. + */ + +int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + if (n < 32) { + /* gprs */ + return gdb_get_regl(mem_buf, env->gpr[n]); + } else if (n < 64) { + /* fprs */ + if (gdb_has_xml) { + return 0; + } + stfq_p(mem_buf, env->fpr[n-32]); + return 8; + } else { + switch (n) { + case 64: + return gdb_get_regl(mem_buf, env->nip); + case 65: + return gdb_get_regl(mem_buf, env->msr); + case 66: + { + uint32_t cr = 0; + int i; + for (i = 0; i < 8; i++) { + cr |= env->crf[i] << (32 - ((i + 1) * 4)); + } + return gdb_get_reg32(mem_buf, cr); + } + case 67: + return gdb_get_regl(mem_buf, env->lr); + case 68: + return gdb_get_regl(mem_buf, env->ctr); + case 69: + return gdb_get_regl(mem_buf, env->xer); + case 70: + { + if (gdb_has_xml) { + return 0; + } + return gdb_get_reg32(mem_buf, env->fpscr); + } + } + } + return 0; +} + +int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + if (n < 32) { + /* gprs */ + env->gpr[n] = ldtul_p(mem_buf); + return sizeof(target_ulong); + } else if (n < 64) { + /* fprs */ + if (gdb_has_xml) { + return 0; + } + env->fpr[n-32] = ldfq_p(mem_buf); + return 8; + } else { + switch (n) { + case 64: + env->nip = ldtul_p(mem_buf); + return sizeof(target_ulong); + case 65: + ppc_store_msr(env, ldtul_p(mem_buf)); + return sizeof(target_ulong); + case 66: + { + uint32_t cr = ldl_p(mem_buf); + int i; + for (i = 0; i < 8; i++) { + env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF; + } + return 4; + } + case 67: + env->lr = ldtul_p(mem_buf); + return sizeof(target_ulong); + case 68: + env->ctr = ldtul_p(mem_buf); + return sizeof(target_ulong); + case 69: + env->xer = ldtul_p(mem_buf); + return sizeof(target_ulong); + case 70: + /* fpscr */ + if (gdb_has_xml) { + return 0; + } + store_fpscr(env, ldtul_p(mem_buf), 0xffffffff); + return sizeof(target_ulong); + } + } + return 0; +} diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index b0099e122f..27e2aaf648 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -65,6 +65,7 @@ static int cap_one_reg; static int cap_epr; static int cap_ppc_watchdog; static int cap_papr; +static int cap_htab_fd; /* XXX We have a race condition where we actually have a level triggered * interrupt, but the infrastructure can't expose that yet, so the guest @@ -101,6 +102,7 @@ int kvm_arch_init(KVMState *s) cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); /* Note: we don't set cap_papr here, because this capability is * only activated after this by kvmppc_set_papr() */ + cap_htab_fd = kvm_check_extension(s, KVM_CAP_PPC_HTAB_FD); if (!cap_interrupt_level) { fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the " @@ -1626,7 +1628,7 @@ void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd) return NULL; } - len = (window_size / SPAPR_TCE_PAGE_SIZE) * sizeof(sPAPRTCE); + len = (window_size / SPAPR_TCE_PAGE_SIZE) * sizeof(uint64_t); /* FIXME: round this up to page size */ table = mmap(NULL, len, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); @@ -1649,7 +1651,7 @@ int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t window_size) return -1; } - len = (window_size / SPAPR_TCE_PAGE_SIZE)*sizeof(sPAPRTCE); + len = (window_size / SPAPR_TCE_PAGE_SIZE)*sizeof(uint64_t); if ((munmap(table, len) < 0) || (close(fd) < 0)) { fprintf(stderr, "KVM: Unexpected error removing TCE table: %s", @@ -1788,6 +1790,73 @@ static int kvm_ppc_register_host_cpu_type(void) } +int kvmppc_get_htab_fd(bool write) +{ + struct kvm_get_htab_fd s = { + .flags = write ? KVM_GET_HTAB_WRITE : 0, + .start_index = 0, + }; + + if (!cap_htab_fd) { + fprintf(stderr, "KVM version doesn't support saving the hash table\n"); + return -1; + } + + return kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s); +} + +int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) +{ + int64_t starttime = qemu_get_clock_ns(rt_clock); + uint8_t buf[bufsize]; + ssize_t rc; + + do { + rc = read(fd, buf, bufsize); + if (rc < 0) { + fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n", + strerror(errno)); + return rc; + } else if (rc) { + /* Kernel already retuns data in BE format for the file */ + qemu_put_buffer(f, buf, rc); + } + } while ((rc != 0) + && ((max_ns < 0) + || ((qemu_get_clock_ns(rt_clock) - starttime) < max_ns))); + + return (rc == 0) ? 1 : 0; +} + +int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, + uint16_t n_valid, uint16_t n_invalid) +{ + struct kvm_get_htab_header *buf; + size_t chunksize = sizeof(*buf) + n_valid*HASH_PTE_SIZE_64; + ssize_t rc; + + buf = alloca(chunksize); + /* This is KVM on ppc, so this is all big-endian */ + buf->index = index; + buf->n_valid = n_valid; + buf->n_invalid = n_invalid; + + qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64*n_valid); + + rc = write(fd, buf, chunksize); + if (rc < 0) { + fprintf(stderr, "Error writing KVM hash table: %s\n", + strerror(errno)); + return rc; + } + if (rc != chunksize) { + /* We should never get a short write on a single chunk */ + fprintf(stderr, "Short write, restoring KVM hash table\n"); + return -1; + } + return 0; +} + bool kvm_arch_stop_on_emulation_error(CPUState *cpu) { return true; diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h index 771cfbe82b..4ae7bf2c32 100644 --- a/target-ppc/kvm_ppc.h +++ b/target-ppc/kvm_ppc.h @@ -38,6 +38,10 @@ uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift); #endif /* !CONFIG_USER_ONLY */ int kvmppc_fixup_cpu(PowerPCCPU *cpu); bool kvmppc_has_cap_epr(void); +int kvmppc_get_htab_fd(bool write); +int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns); +int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, + uint16_t n_valid, uint16_t n_invalid); #else @@ -159,6 +163,24 @@ static inline bool kvmppc_has_cap_epr(void) { return false; } + +static inline int kvmppc_get_htab_fd(bool write) +{ + return -1; +} + +static inline int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, + int64_t max_ns) +{ + abort(); +} + +static inline int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, + uint16_t n_valid, uint16_t n_invalid) +{ + abort(); +} + #endif #ifndef CONFIG_KVM diff --git a/target-ppc/machine.c b/target-ppc/machine.c index 2d10adb60d..12e1512996 100644 --- a/target-ppc/machine.c +++ b/target-ppc/machine.c @@ -1,96 +1,12 @@ #include "hw/hw.h" #include "hw/boards.h" #include "sysemu/kvm.h" +#include "helper_regs.h" -void cpu_save(QEMUFile *f, void *opaque) +static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) { - CPUPPCState *env = (CPUPPCState *)opaque; - unsigned int i, j; - uint32_t fpscr; - target_ulong xer; - - for (i = 0; i < 32; i++) - qemu_put_betls(f, &env->gpr[i]); -#if !defined(TARGET_PPC64) - for (i = 0; i < 32; i++) - qemu_put_betls(f, &env->gprh[i]); -#endif - qemu_put_betls(f, &env->lr); - qemu_put_betls(f, &env->ctr); - for (i = 0; i < 8; i++) - qemu_put_be32s(f, &env->crf[i]); - xer = cpu_read_xer(env); - qemu_put_betls(f, &xer); - qemu_put_betls(f, &env->reserve_addr); - qemu_put_betls(f, &env->msr); - for (i = 0; i < 4; i++) - qemu_put_betls(f, &env->tgpr[i]); - for (i = 0; i < 32; i++) { - union { - float64 d; - uint64_t l; - } u; - u.d = env->fpr[i]; - qemu_put_be64(f, u.l); - } - fpscr = env->fpscr; - qemu_put_be32s(f, &fpscr); - qemu_put_sbe32s(f, &env->access_type); -#if defined(TARGET_PPC64) - qemu_put_betls(f, &env->spr[SPR_ASR]); - qemu_put_sbe32s(f, &env->slb_nr); -#endif - qemu_put_betls(f, &env->spr[SPR_SDR1]); - for (i = 0; i < 32; i++) - qemu_put_betls(f, &env->sr[i]); - for (i = 0; i < 2; i++) - for (j = 0; j < 8; j++) - qemu_put_betls(f, &env->DBAT[i][j]); - for (i = 0; i < 2; i++) - for (j = 0; j < 8; j++) - qemu_put_betls(f, &env->IBAT[i][j]); - qemu_put_sbe32s(f, &env->nb_tlb); - qemu_put_sbe32s(f, &env->tlb_per_way); - qemu_put_sbe32s(f, &env->nb_ways); - qemu_put_sbe32s(f, &env->last_way); - qemu_put_sbe32s(f, &env->id_tlbs); - qemu_put_sbe32s(f, &env->nb_pids); - if (env->tlb.tlb6) { - // XXX assumes 6xx - for (i = 0; i < env->nb_tlb; i++) { - qemu_put_betls(f, &env->tlb.tlb6[i].pte0); - qemu_put_betls(f, &env->tlb.tlb6[i].pte1); - qemu_put_betls(f, &env->tlb.tlb6[i].EPN); - } - } - for (i = 0; i < 4; i++) - qemu_put_betls(f, &env->pb[i]); - for (i = 0; i < 1024; i++) - qemu_put_betls(f, &env->spr[i]); - qemu_put_be32s(f, &env->vscr); - qemu_put_be64s(f, &env->spe_acc); - qemu_put_be32s(f, &env->spe_fscr); - qemu_put_betls(f, &env->msr_mask); - qemu_put_be32s(f, &env->flags); - qemu_put_sbe32s(f, &env->error_code); - qemu_put_be32s(f, &env->pending_interrupts); - qemu_put_be32s(f, &env->irq_input_state); - for (i = 0; i < POWERPC_EXCP_NB; i++) - qemu_put_betls(f, &env->excp_vectors[i]); - qemu_put_betls(f, &env->excp_prefix); - qemu_put_betls(f, &env->ivor_mask); - qemu_put_betls(f, &env->ivpr_mask); - qemu_put_betls(f, &env->hreset_vector); - qemu_put_betls(f, &env->nip); - qemu_put_betls(f, &env->hflags); - qemu_put_betls(f, &env->hflags_nmsr); - qemu_put_sbe32s(f, &env->mmu_idx); - qemu_put_sbe32(f, 0); -} - -int cpu_load(QEMUFile *f, void *opaque, int version_id) -{ - CPUPPCState *env = (CPUPPCState *)opaque; + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; unsigned int i, j; target_ulong sdr1; uint32_t fpscr; @@ -177,3 +93,442 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) return 0; } + +static int get_avr(QEMUFile *f, void *pv, size_t size) +{ + ppc_avr_t *v = pv; + + v->u64[0] = qemu_get_be64(f); + v->u64[1] = qemu_get_be64(f); + + return 0; +} + +static void put_avr(QEMUFile *f, void *pv, size_t size) +{ + ppc_avr_t *v = pv; + + qemu_put_be64(f, v->u64[0]); + qemu_put_be64(f, v->u64[1]); +} + +const VMStateInfo vmstate_info_avr = { + .name = "avr", + .get = get_avr, + .put = put_avr, +}; + +#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) + +#define VMSTATE_AVR_ARRAY(_f, _s, _n) \ + VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) + +static void cpu_pre_save(void *opaque) +{ + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; + int i; + + env->spr[SPR_LR] = env->lr; + env->spr[SPR_CTR] = env->ctr; + env->spr[SPR_XER] = env->xer; +#if defined(TARGET_PPC64) + env->spr[SPR_CFAR] = env->cfar; +#endif + env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; + + for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { + env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i]; + env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i]; + env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i]; + env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i]; + } + for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { + env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4]; + env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4]; + env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4]; + env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4]; + } +} + +static int cpu_post_load(void *opaque, int version_id) +{ + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; + int i; + + env->lr = env->spr[SPR_LR]; + env->ctr = env->spr[SPR_CTR]; + env->xer = env->spr[SPR_XER]; +#if defined(TARGET_PPC64) + env->cfar = env->spr[SPR_CFAR]; +#endif + env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; + + for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { + env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i]; + env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1]; + env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i]; + env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1]; + } + for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { + env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i]; + env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1]; + env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i]; + env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1]; + } + + /* Restore htab_base and htab_mask variables */ + ppc_store_sdr1(env, env->spr[SPR_SDR1]); + + hreg_compute_hflags(env); + hreg_compute_mem_idx(env); + + return 0; +} + +static bool fpu_needed(void *opaque) +{ + PowerPCCPU *cpu = opaque; + + return (cpu->env.insns_flags & PPC_FLOAT); +} + +static const VMStateDescription vmstate_fpu = { + .name = "cpu/fpu", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32), + VMSTATE_UINTTL(env.fpscr, PowerPCCPU), + VMSTATE_END_OF_LIST() + }, +}; + +static bool altivec_needed(void *opaque) +{ + PowerPCCPU *cpu = opaque; + + return (cpu->env.insns_flags & PPC_ALTIVEC); +} + +static const VMStateDescription vmstate_altivec = { + .name = "cpu/altivec", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32), + VMSTATE_UINT32(env.vscr, PowerPCCPU), + VMSTATE_END_OF_LIST() + }, +}; + +static bool vsx_needed(void *opaque) +{ + PowerPCCPU *cpu = opaque; + + return (cpu->env.insns_flags2 & PPC2_VSX); +} + +static const VMStateDescription vmstate_vsx = { + .name = "cpu/vsx", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), + VMSTATE_END_OF_LIST() + }, +}; + +static bool sr_needed(void *opaque) +{ +#ifdef TARGET_PPC64 + PowerPCCPU *cpu = opaque; + + return !(cpu->env.mmu_model & POWERPC_MMU_64); +#else + return true; +#endif +} + +static const VMStateDescription vmstate_sr = { + .name = "cpu/sr", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), + VMSTATE_END_OF_LIST() + }, +}; + +#ifdef TARGET_PPC64 +static int get_slbe(QEMUFile *f, void *pv, size_t size) +{ + ppc_slb_t *v = pv; + + v->esid = qemu_get_be64(f); + v->vsid = qemu_get_be64(f); + + return 0; +} + +static void put_slbe(QEMUFile *f, void *pv, size_t size) +{ + ppc_slb_t *v = pv; + + qemu_put_be64(f, v->esid); + qemu_put_be64(f, v->vsid); +} + +const VMStateInfo vmstate_info_slbe = { + .name = "slbe", + .get = get_slbe, + .put = put_slbe, +}; + +#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) + +#define VMSTATE_SLB_ARRAY(_f, _s, _n) \ + VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) + +static bool slb_needed(void *opaque) +{ + PowerPCCPU *cpu = opaque; + + /* We don't support any of the old segment table based 64-bit CPUs */ + return (cpu->env.mmu_model & POWERPC_MMU_64); +} + +static const VMStateDescription vmstate_slb = { + .name = "cpu/slb", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU), + VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, 64), + VMSTATE_END_OF_LIST() + } +}; +#endif /* TARGET_PPC64 */ + +static const VMStateDescription vmstate_tlb6xx_entry = { + .name = "cpu/tlb6xx_entry", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), + VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), + VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), + VMSTATE_END_OF_LIST() + }, +}; + +static bool tlb6xx_needed(void *opaque) +{ + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; + + return env->nb_tlb && (env->tlb_type == TLB_6XX); +} + +static const VMStateDescription vmstate_tlb6xx = { + .name = "cpu/tlb6xx", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), + VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, + env.nb_tlb, + vmstate_tlb6xx_entry, + ppc6xx_tlb_t), + VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_tlbemb_entry = { + .name = "cpu/tlbemb_entry", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT64(RPN, ppcemb_tlb_t), + VMSTATE_UINTTL(EPN, ppcemb_tlb_t), + VMSTATE_UINTTL(PID, ppcemb_tlb_t), + VMSTATE_UINTTL(size, ppcemb_tlb_t), + VMSTATE_UINT32(prot, ppcemb_tlb_t), + VMSTATE_UINT32(attr, ppcemb_tlb_t), + VMSTATE_END_OF_LIST() + }, +}; + +static bool tlbemb_needed(void *opaque) +{ + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; + + return env->nb_tlb && (env->tlb_type == TLB_EMB); +} + +static bool pbr403_needed(void *opaque) +{ + PowerPCCPU *cpu = opaque; + uint32_t pvr = cpu->env.spr[SPR_PVR]; + + return (pvr & 0xffff0000) == 0x00200000; +} + +static const VMStateDescription vmstate_pbr403 = { + .name = "cpu/pbr403", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4), + VMSTATE_END_OF_LIST() + }, +}; + +static const VMStateDescription vmstate_tlbemb = { + .name = "cpu/tlb6xx", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), + VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, + env.nb_tlb, + vmstate_tlbemb_entry, + ppcemb_tlb_t), + /* 403 protection registers */ + VMSTATE_END_OF_LIST() + }, + .subsections = (VMStateSubsection []) { + { + .vmsd = &vmstate_pbr403, + .needed = pbr403_needed, + } , { + /* empty */ + } + } +}; + +static const VMStateDescription vmstate_tlbmas_entry = { + .name = "cpu/tlbmas_entry", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT32(mas8, ppcmas_tlb_t), + VMSTATE_UINT32(mas1, ppcmas_tlb_t), + VMSTATE_UINT64(mas2, ppcmas_tlb_t), + VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), + VMSTATE_END_OF_LIST() + }, +}; + +static bool tlbmas_needed(void *opaque) +{ + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; + + return env->nb_tlb && (env->tlb_type == TLB_MAS); +} + +static const VMStateDescription vmstate_tlbmas = { + .name = "cpu/tlbmas", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), + VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, + env.nb_tlb, + vmstate_tlbmas_entry, + ppcmas_tlb_t), + VMSTATE_END_OF_LIST() + } +}; + +const VMStateDescription vmstate_ppc_cpu = { + .name = "cpu", + .version_id = 5, + .minimum_version_id = 5, + .minimum_version_id_old = 4, + .load_state_old = cpu_load_old, + .pre_save = cpu_pre_save, + .post_load = cpu_post_load, + .fields = (VMStateField []) { + /* Verify we haven't changed the pvr */ + VMSTATE_UINTTL_EQUAL(env.spr[SPR_PVR], PowerPCCPU), + + /* User mode architected state */ + VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), +#if !defined(TARGET_PPC64) + VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), +#endif + VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), + VMSTATE_UINTTL(env.nip, PowerPCCPU), + + /* SPRs */ + VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), + VMSTATE_UINT64(env.spe_acc, PowerPCCPU), + + /* Reservation */ + VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), + + /* Supervisor mode architected state */ + VMSTATE_UINTTL(env.msr, PowerPCCPU), + + /* Internal state */ + VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), + /* FIXME: access_type? */ + + /* Sanity checking */ + VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU), + VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU), + VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU), + VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU), + VMSTATE_END_OF_LIST() + }, + .subsections = (VMStateSubsection []) { + { + .vmsd = &vmstate_fpu, + .needed = fpu_needed, + } , { + .vmsd = &vmstate_altivec, + .needed = altivec_needed, + } , { + .vmsd = &vmstate_vsx, + .needed = vsx_needed, + } , { + .vmsd = &vmstate_sr, + .needed = sr_needed, + } , { +#ifdef TARGET_PPC64 + .vmsd = &vmstate_slb, + .needed = slb_needed, + } , { +#endif /* TARGET_PPC64 */ + .vmsd = &vmstate_tlb6xx, + .needed = tlb6xx_needed, + } , { + .vmsd = &vmstate_tlbemb, + .needed = tlbemb_needed, + } , { + .vmsd = &vmstate_tlbmas, + .needed = tlbmas_needed, + } , { + /* empty */ + } + } +}; diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 0b0844f467..0724226dd6 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7861,6 +7861,8 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) 34, "power-spe.xml", 0); } + qemu_init_vcpu(cs); + pcc->parent_realize(dev, errp); #if defined(PPC_DUMP_CPU) @@ -8458,8 +8460,18 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) cc->dump_state = ppc_cpu_dump_state; cc->dump_statistics = ppc_cpu_dump_statistics; cc->set_pc = ppc_cpu_set_pc; + cc->gdb_read_register = ppc_cpu_gdb_read_register; + cc->gdb_write_register = ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug; + cc->vmsd = &vmstate_ppc_cpu; +#endif + + cc->gdb_num_core_regs = 71; +#if defined(TARGET_PPC64) + cc->gdb_core_xml_file = "power64-core.xml"; +#else + cc->gdb_core_xml_file = "power-core.xml"; #endif } diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs index 4e634173a4..ab938e7ad8 100644 --- a/target-s390x/Makefile.objs +++ b/target-s390x/Makefile.objs @@ -1,4 +1,5 @@ obj-y += translate.o helper.o cpu.o interrupt.o obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o misc_helper.o +obj-y += gdbstub.o obj-$(CONFIG_SOFTMMU) += ioinst.o obj-$(CONFIG_KVM) += kvm.o diff --git a/target-s390x/cpu-qom.h b/target-s390x/cpu-qom.h index a4fe8fb5fc..0d63b1cf20 100644 --- a/target-s390x/cpu-qom.h +++ b/target-s390x/cpu-qom.h @@ -75,5 +75,7 @@ void s390_cpu_do_interrupt(CPUState *cpu); void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #endif diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index cb89d1a46b..9b824957f6 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -101,10 +101,11 @@ static void s390_cpu_machine_reset_cb(void *opaque) static void s390_cpu_realizefn(DeviceState *dev, Error **errp) { - S390CPU *cpu = S390_CPU(dev); + CPUState *cs = CPU(dev); S390CPUClass *scc = S390_CPU_GET_CLASS(dev); - cpu_reset(CPU(cpu)); + qemu_init_vcpu(cs); + cpu_reset(cs); scc->parent_realize(dev, errp); } @@ -173,10 +174,13 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) cc->do_interrupt = s390_cpu_do_interrupt; cc->dump_state = s390_cpu_dump_state; cc->set_pc = s390_cpu_set_pc; + cc->gdb_read_register = s390_cpu_gdb_read_register; + cc->gdb_write_register = s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = s390_cpu_get_phys_page_debug; #endif dc->vmsd = &vmstate_s390_cpu; + cc->gdb_num_core_regs = S390_NUM_REGS; } static const TypeInfo s390_cpu_type_info = { diff --git a/target-s390x/gdbstub.c b/target-s390x/gdbstub.c new file mode 100644 index 0000000000..a129742e2f --- /dev/null +++ b/target-s390x/gdbstub.c @@ -0,0 +1,88 @@ +/* + * s390x gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" +#include "qemu/bitops.h" + +int s390_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + uint64_t val; + int cc_op; + + switch (n) { + case S390_PSWM_REGNUM: + cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr); + val = deposit64(env->psw.mask, 44, 2, cc_op); + return gdb_get_regl(mem_buf, val); + case S390_PSWA_REGNUM: + return gdb_get_regl(mem_buf, env->psw.addr); + case S390_R0_REGNUM ... S390_R15_REGNUM: + return gdb_get_regl(mem_buf, env->regs[n-S390_R0_REGNUM]); + case S390_A0_REGNUM ... S390_A15_REGNUM: + return gdb_get_reg32(mem_buf, env->aregs[n-S390_A0_REGNUM]); + case S390_FPC_REGNUM: + return gdb_get_reg32(mem_buf, env->fpc); + case S390_F0_REGNUM ... S390_F15_REGNUM: + return gdb_get_reg64(mem_buf, env->fregs[n-S390_F0_REGNUM].ll); + } + + return 0; +} + +int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + target_ulong tmpl; + uint32_t tmp32; + int r = 8; + tmpl = ldtul_p(mem_buf); + tmp32 = ldl_p(mem_buf); + + switch (n) { + case S390_PSWM_REGNUM: + env->psw.mask = tmpl; + env->cc_op = extract64(tmpl, 44, 2); + break; + case S390_PSWA_REGNUM: + env->psw.addr = tmpl; + break; + case S390_R0_REGNUM ... S390_R15_REGNUM: + env->regs[n-S390_R0_REGNUM] = tmpl; + break; + case S390_A0_REGNUM ... S390_A15_REGNUM: + env->aregs[n-S390_A0_REGNUM] = tmp32; + r = 4; + break; + case S390_FPC_REGNUM: + env->fpc = tmp32; + r = 4; + break; + case S390_F0_REGNUM ... S390_F15_REGNUM: + env->fregs[n-S390_F0_REGNUM].ll = tmpl; + break; + default: + return 0; + } + return r; +} diff --git a/target-s390x/kvm.c b/target-s390x/kvm.c index 60e94f8ee8..85f01125de 100644 --- a/target-s390x/kvm.c +++ b/target-s390x/kvm.c @@ -345,12 +345,10 @@ void *kvm_arch_ram_alloc(ram_addr_t size) int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; static const uint8_t diag_501[] = {0x83, 0x24, 0x05, 0x01}; - if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || - cpu_memory_rw_debug(env, bp->pc, (uint8_t *)diag_501, 4, 1)) { + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)diag_501, 4, 1)) { return -EINVAL; } return 0; @@ -358,16 +356,14 @@ int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; uint8_t t[4]; static const uint8_t diag_501[] = {0x83, 0x24, 0x05, 0x01}; - if (cpu_memory_rw_debug(env, bp->pc, t, 4, 0)) { + if (cpu_memory_rw_debug(cs, bp->pc, t, 4, 0)) { return -EINVAL; } else if (memcmp(t, diag_501, 4)) { return -EINVAL; - } else if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { + } else if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { return -EINVAL; } diff --git a/target-sh4/Makefile.objs b/target-sh4/Makefile.objs index cb448a840f..a285358adf 100644 --- a/target-sh4/Makefile.objs +++ b/target-sh4/Makefile.objs @@ -1 +1,2 @@ obj-y += translate.o op_helper.o helper.o cpu.o +obj-y += gdbstub.o diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h index 7c9160bab8..c04e78631b 100644 --- a/target-sh4/cpu-qom.h +++ b/target-sh4/cpu-qom.h @@ -87,5 +87,7 @@ void superh_cpu_do_interrupt(CPUState *cpu); void superh_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #endif diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 51a77576fb..34b2b57ba7 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -240,10 +240,11 @@ static const TypeInfo sh7785_type_info = { static void superh_cpu_realizefn(DeviceState *dev, Error **errp) { - SuperHCPU *cpu = SUPERH_CPU(dev); + CPUState *cs = CPU(dev); SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); - cpu_reset(CPU(cpu)); + cpu_reset(cs); + qemu_init_vcpu(cs); scc->parent_realize(dev, errp); } @@ -286,10 +287,13 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) cc->dump_state = superh_cpu_dump_state; cc->set_pc = superh_cpu_set_pc; cc->synchronize_from_tb = superh_cpu_synchronize_from_tb; + cc->gdb_read_register = superh_cpu_gdb_read_register; + cc->gdb_write_register = superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = superh_cpu_get_phys_page_debug; #endif dc->vmsd = &vmstate_sh_cpu; + cc->gdb_num_core_regs = 59; } static const TypeInfo superh_cpu_type_info = { diff --git a/target-sh4/gdbstub.c b/target-sh4/gdbstub.c new file mode 100644 index 0000000000..df4fa2af76 --- /dev/null +++ b/target-sh4/gdbstub.c @@ -0,0 +1,146 @@ +/* + * SuperH gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" + +/* Hint: Use "set architecture sh4" in GDB to see fpu registers */ +/* FIXME: We should use XML for this. */ + +int superh_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + SuperHCPU *cpu = SUPERH_CPU(cs); + CPUSH4State *env = &cpu->env; + + switch (n) { + case 0 ... 7: + if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) { + return gdb_get_regl(mem_buf, env->gregs[n + 16]); + } else { + return gdb_get_regl(mem_buf, env->gregs[n]); + } + case 8 ... 15: + return gdb_get_regl(mem_buf, env->gregs[n]); + case 16: + return gdb_get_regl(mem_buf, env->pc); + case 17: + return gdb_get_regl(mem_buf, env->pr); + case 18: + return gdb_get_regl(mem_buf, env->gbr); + case 19: + return gdb_get_regl(mem_buf, env->vbr); + case 20: + return gdb_get_regl(mem_buf, env->mach); + case 21: + return gdb_get_regl(mem_buf, env->macl); + case 22: + return gdb_get_regl(mem_buf, env->sr); + case 23: + return gdb_get_regl(mem_buf, env->fpul); + case 24: + return gdb_get_regl(mem_buf, env->fpscr); + case 25 ... 40: + if (env->fpscr & FPSCR_FR) { + stfl_p(mem_buf, env->fregs[n - 9]); + } else { + stfl_p(mem_buf, env->fregs[n - 25]); + } + return 4; + case 41: + return gdb_get_regl(mem_buf, env->ssr); + case 42: + return gdb_get_regl(mem_buf, env->spc); + case 43 ... 50: + return gdb_get_regl(mem_buf, env->gregs[n - 43]); + case 51 ... 58: + return gdb_get_regl(mem_buf, env->gregs[n - (51 - 16)]); + } + + return 0; +} + +int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + SuperHCPU *cpu = SUPERH_CPU(cs); + CPUSH4State *env = &cpu->env; + + switch (n) { + case 0 ... 7: + if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) { + env->gregs[n + 16] = ldl_p(mem_buf); + } else { + env->gregs[n] = ldl_p(mem_buf); + } + break; + case 8 ... 15: + env->gregs[n] = ldl_p(mem_buf); + break; + case 16: + env->pc = ldl_p(mem_buf); + break; + case 17: + env->pr = ldl_p(mem_buf); + break; + case 18: + env->gbr = ldl_p(mem_buf); + break; + case 19: + env->vbr = ldl_p(mem_buf); + break; + case 20: + env->mach = ldl_p(mem_buf); + break; + case 21: + env->macl = ldl_p(mem_buf); + break; + case 22: + env->sr = ldl_p(mem_buf); + break; + case 23: + env->fpul = ldl_p(mem_buf); + break; + case 24: + env->fpscr = ldl_p(mem_buf); + break; + case 25 ... 40: + if (env->fpscr & FPSCR_FR) { + env->fregs[n - 9] = ldfl_p(mem_buf); + } else { + env->fregs[n - 25] = ldfl_p(mem_buf); + } + break; + case 41: + env->ssr = ldl_p(mem_buf); + break; + case 42: + env->spc = ldl_p(mem_buf); + break; + case 43 ... 50: + env->gregs[n - 43] = ldl_p(mem_buf); + break; + case 51 ... 58: + env->gregs[n - (51 - 16)] = ldl_p(mem_buf); + break; + default: + return 0; + } + + return 4; +} diff --git a/target-sparc/Makefile.objs b/target-sparc/Makefile.objs index 9fc42ea9b0..1cd81cccc3 100644 --- a/target-sparc/Makefile.objs +++ b/target-sparc/Makefile.objs @@ -4,3 +4,4 @@ obj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o obj-$(TARGET_SPARC) += int32_helper.o obj-$(TARGET_SPARC64) += int64_helper.o obj-$(TARGET_SPARC64) += vis_helper.o +obj-y += gdbstub.o diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h index 39d975b5fc..8e3e0de277 100644 --- a/target-sparc/cpu-qom.h +++ b/target-sparc/cpu-qom.h @@ -79,5 +79,7 @@ void sparc_cpu_do_interrupt(CPUState *cpu); void sparc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #endif diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index d1d03396ef..47ce60de4a 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -743,6 +743,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) { SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); + qemu_init_vcpu(CPU(dev)); + scc->parent_realize(dev, errp); } @@ -787,10 +789,18 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) #endif cc->set_pc = sparc_cpu_set_pc; cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb; + cc->gdb_read_register = sparc_cpu_gdb_read_register; + cc->gdb_write_register = sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->do_unassigned_access = sparc_cpu_unassigned_access; cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; #endif + +#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) + cc->gdb_num_core_regs = 86; +#else + cc->gdb_num_core_regs = 72; +#endif } static const TypeInfo sparc_cpu_type_info = { diff --git a/target-sparc/gdbstub.c b/target-sparc/gdbstub.c new file mode 100644 index 0000000000..3de3242b29 --- /dev/null +++ b/target-sparc/gdbstub.c @@ -0,0 +1,208 @@ +/* + * SPARC gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" + +#ifdef TARGET_ABI32 +#define gdb_get_rega(buf, val) gdb_get_reg32(buf, val) +#else +#define gdb_get_rega(buf, val) gdb_get_regl(buf, val) +#endif + +int sparc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + + if (n < 8) { + /* g0..g7 */ + return gdb_get_rega(mem_buf, env->gregs[n]); + } + if (n < 32) { + /* register window */ + return gdb_get_rega(mem_buf, env->regwptr[n - 8]); + } +#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) + if (n < 64) { + /* fprs */ + if (n & 1) { + return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower); + } else { + return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper); + } + } + /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */ + switch (n) { + case 64: + return gdb_get_rega(mem_buf, env->y); + case 65: + return gdb_get_rega(mem_buf, cpu_get_psr(env)); + case 66: + return gdb_get_rega(mem_buf, env->wim); + case 67: + return gdb_get_rega(mem_buf, env->tbr); + case 68: + return gdb_get_rega(mem_buf, env->pc); + case 69: + return gdb_get_rega(mem_buf, env->npc); + case 70: + return gdb_get_rega(mem_buf, env->fsr); + case 71: + return gdb_get_rega(mem_buf, 0); /* csr */ + default: + return gdb_get_rega(mem_buf, 0); + } +#else + if (n < 64) { + /* f0-f31 */ + if (n & 1) { + return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower); + } else { + return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper); + } + } + if (n < 80) { + /* f32-f62 (double width, even numbers only) */ + return gdb_get_reg64(mem_buf, env->fpr[(n - 32) / 2].ll); + } + switch (n) { + case 80: + return gdb_get_regl(mem_buf, env->pc); + case 81: + return gdb_get_regl(mem_buf, env->npc); + case 82: + return gdb_get_regl(mem_buf, (cpu_get_ccr(env) << 32) | + ((env->asi & 0xff) << 24) | + ((env->pstate & 0xfff) << 8) | + cpu_get_cwp64(env)); + case 83: + return gdb_get_regl(mem_buf, env->fsr); + case 84: + return gdb_get_regl(mem_buf, env->fprs); + case 85: + return gdb_get_regl(mem_buf, env->y); + } +#endif + return 0; +} + +int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; +#if defined(TARGET_ABI32) + abi_ulong tmp; + + tmp = ldl_p(mem_buf); +#else + target_ulong tmp; + + tmp = ldtul_p(mem_buf); +#endif + + if (n < 8) { + /* g0..g7 */ + env->gregs[n] = tmp; + } else if (n < 32) { + /* register window */ + env->regwptr[n - 8] = tmp; + } +#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) + else if (n < 64) { + /* fprs */ + /* f0-f31 */ + if (n & 1) { + env->fpr[(n - 32) / 2].l.lower = tmp; + } else { + env->fpr[(n - 32) / 2].l.upper = tmp; + } + } else { + /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */ + switch (n) { + case 64: + env->y = tmp; + break; + case 65: + cpu_put_psr(env, tmp); + break; + case 66: + env->wim = tmp; + break; + case 67: + env->tbr = tmp; + break; + case 68: + env->pc = tmp; + break; + case 69: + env->npc = tmp; + break; + case 70: + env->fsr = tmp; + break; + default: + return 0; + } + } + return 4; +#else + else if (n < 64) { + /* f0-f31 */ + tmp = ldl_p(mem_buf); + if (n & 1) { + env->fpr[(n - 32) / 2].l.lower = tmp; + } else { + env->fpr[(n - 32) / 2].l.upper = tmp; + } + return 4; + } else if (n < 80) { + /* f32-f62 (double width, even numbers only) */ + env->fpr[(n - 32) / 2].ll = tmp; + } else { + switch (n) { + case 80: + env->pc = tmp; + break; + case 81: + env->npc = tmp; + break; + case 82: + cpu_put_ccr(env, tmp >> 32); + env->asi = (tmp >> 24) & 0xff; + env->pstate = (tmp >> 8) & 0xfff; + cpu_put_cwp64(env, tmp & 0xff); + break; + case 83: + env->fsr = tmp; + break; + case 84: + env->fprs = tmp; + break; + case 85: + env->y = tmp; + break; + default: + return 0; + } + } + return 8; +#endif +} diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c index 46813e52ae..3f78208360 100644 --- a/target-unicore32/cpu.c +++ b/target-unicore32/cpu.c @@ -92,6 +92,8 @@ static void uc32_cpu_realizefn(DeviceState *dev, Error **errp) { UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev); + qemu_init_vcpu(CPU(dev)); + ucc->parent_realize(dev, errp); } diff --git a/target-xtensa/Makefile.objs b/target-xtensa/Makefile.objs index 644b7f99bb..5c150a870f 100644 --- a/target-xtensa/Makefile.objs +++ b/target-xtensa/Makefile.objs @@ -3,3 +3,4 @@ obj-y += core-dc232b.o obj-y += core-dc233c.o obj-y += core-fsf.o obj-y += translate.o op_helper.o helper.o cpu.o +obj-y += gdbstub.o diff --git a/target-xtensa/cpu-qom.h b/target-xtensa/cpu-qom.h index b9896f2647..c6cc2d91f4 100644 --- a/target-xtensa/cpu-qom.h +++ b/target-xtensa/cpu-qom.h @@ -45,6 +45,7 @@ * XtensaCPUClass: * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. + * @config: The CPU core configuration. * * An Xtensa CPU model. */ @@ -55,6 +56,8 @@ typedef struct XtensaCPUClass { DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); + + const XtensaConfig *config; } XtensaCPUClass; /** @@ -84,5 +87,7 @@ void xtensa_cpu_do_interrupt(CPUState *cpu); void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #endif diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index d2bcfc69a2..c19d17ad04 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -64,10 +64,34 @@ static void xtensa_cpu_reset(CPUState *s) reset_mmu(env); } +static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) +{ + ObjectClass *oc; + char *typename; + + if (cpu_model == NULL) { + return NULL; + } + + typename = g_strdup_printf("%s-" TYPE_XTENSA_CPU, cpu_model); + oc = object_class_by_name(typename); + g_free(typename); + if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) || + object_class_is_abstract(oc)) { + return NULL; + } + return oc; +} + static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) { + CPUState *cs = CPU(dev); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); + cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; + + qemu_init_vcpu(cs); + xcc->parent_realize(dev, errp); } @@ -75,10 +99,12 @@ static void xtensa_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); XtensaCPU *cpu = XTENSA_CPU(obj); + XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); CPUXtensaState *env = &cpu->env; static bool tcg_inited; cs->env_ptr = env; + env->config = xcc->config; cpu_exec_init(env); if (tcg_enabled() && !tcg_inited) { @@ -105,9 +131,12 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) xcc->parent_reset = cc->reset; cc->reset = xtensa_cpu_reset; + cc->class_by_name = xtensa_cpu_class_by_name; cc->do_interrupt = xtensa_cpu_do_interrupt; cc->dump_state = xtensa_cpu_dump_state; cc->set_pc = xtensa_cpu_set_pc; + cc->gdb_read_register = xtensa_cpu_gdb_read_register; + cc->gdb_write_register = xtensa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; #endif @@ -119,7 +148,7 @@ static const TypeInfo xtensa_cpu_type_info = { .parent = TYPE_CPU, .instance_size = sizeof(XtensaCPU), .instance_init = xtensa_cpu_initfn, - .abstract = false, + .abstract = true, .class_size = sizeof(XtensaCPUClass), .class_init = xtensa_cpu_class_init, }; diff --git a/target-xtensa/gdbstub.c b/target-xtensa/gdbstub.c new file mode 100644 index 0000000000..9e13b20c46 --- /dev/null +++ b/target-xtensa/gdbstub.c @@ -0,0 +1,109 @@ +/* + * Xtensa gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" + +int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + XtensaCPU *cpu = XTENSA_CPU(cs); + CPUXtensaState *env = &cpu->env; + const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; + + if (n < 0 || n >= env->config->gdb_regmap.num_regs) { + return 0; + } + + switch (reg->type) { + case 9: /*pc*/ + return gdb_get_reg32(mem_buf, env->pc); + + case 1: /*ar*/ + xtensa_sync_phys_from_window(env); + return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff) + % env->config->nareg]); + + case 2: /*SR*/ + return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]); + + case 3: /*UR*/ + return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]); + + case 4: /*f*/ + return gdb_get_reg32(mem_buf, float32_val(env->fregs[reg->targno + & 0x0f])); + + case 8: /*a*/ + return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]); + + default: + qemu_log("%s from reg %d of unsupported type %d\n", + __func__, n, reg->type); + return 0; + } +} + +int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + XtensaCPU *cpu = XTENSA_CPU(cs); + CPUXtensaState *env = &cpu->env; + uint32_t tmp; + const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; + + if (n < 0 || n >= env->config->gdb_regmap.num_regs) { + return 0; + } + + tmp = ldl_p(mem_buf); + + switch (reg->type) { + case 9: /*pc*/ + env->pc = tmp; + break; + + case 1: /*ar*/ + env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp; + xtensa_sync_window_from_phys(env); + break; + + case 2: /*SR*/ + env->sregs[reg->targno & 0xff] = tmp; + break; + + case 3: /*UR*/ + env->uregs[reg->targno & 0xff] = tmp; + break; + + case 4: /*f*/ + env->fregs[reg->targno & 0x0f] = make_float32(tmp); + break; + + case 8: /*a*/ + env->regs[reg->targno & 0x0f] = tmp; + break; + + default: + qemu_log("%s to reg %d of unsupported type %d\n", + __func__, n, reg->type); + return 0; + } + + return 4; +} diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index de6cc3b7c5..a0f9993b2d 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -35,10 +35,35 @@ static struct XtensaConfigList *xtensa_cores; +static void xtensa_core_class_init(ObjectClass *oc, void *data) +{ + CPUClass *cc = CPU_CLASS(oc); + XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc); + const XtensaConfig *config = data; + + xcc->config = config; + + /* Use num_core_regs to see only non-privileged registers in an unmodified + * gdb. Use num_regs to see all registers. gdb modification is required + * for that: reset bit 0 in the 'flags' field of the registers definitions + * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay. + */ + cc->gdb_num_core_regs = config->gdb_regmap.num_regs; +} + void xtensa_register_core(XtensaConfigList *node) { + TypeInfo type = { + .parent = TYPE_XTENSA_CPU, + .class_init = xtensa_core_class_init, + .class_data = (void *)node->config, + }; + node->next = xtensa_cores; xtensa_cores = node; + type.name = g_strdup_printf("%s-" TYPE_XTENSA_CPU, node->config->name); + type_register(&type); + g_free((gpointer)type.name); } static uint32_t check_hw_breakpoints(CPUXtensaState *env) @@ -72,24 +97,17 @@ void xtensa_breakpoint_handler(CPUXtensaState *env) XtensaCPU *cpu_xtensa_init(const char *cpu_model) { + ObjectClass *oc; XtensaCPU *cpu; CPUXtensaState *env; - const XtensaConfig *config = NULL; - XtensaConfigList *core = xtensa_cores; - - for (; core; core = core->next) - if (strcmp(core->config->name, cpu_model) == 0) { - config = core->config; - break; - } - if (config == NULL) { + oc = cpu_class_by_name(TYPE_XTENSA_CPU, cpu_model); + if (oc == NULL) { return NULL; } - cpu = XTENSA_CPU(object_new(TYPE_XTENSA_CPU)); + cpu = XTENSA_CPU(object_new(object_class_get_name(oc))); env = &cpu->env; - env->config = config; xtensa_irq_init(env); diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 562a549dab..41a17f8a62 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -315,6 +315,17 @@ static inline void tcg_out_ldst_9(TCGContext *s, tcg_out32(s, op_data << 24 | mod << 20 | off << 12 | rn << 5 | rd); } +/* tcg_out_ldst_12 expects a scaled unsigned immediate offset */ +static inline void tcg_out_ldst_12(TCGContext *s, + enum aarch64_ldst_op_data op_data, + enum aarch64_ldst_op_type op_type, + TCGReg rd, TCGReg rn, + tcg_target_ulong scaled_uimm) +{ + tcg_out32(s, (op_data | 1) << 24 + | op_type << 20 | scaled_uimm << 10 | rn << 5 | rd); +} + static inline void tcg_out_movr(TCGContext *s, int ext, TCGReg rd, TCGReg src) { /* register to register move using MOV (shifted register with no shift) */ @@ -374,10 +385,25 @@ static inline void tcg_out_ldst(TCGContext *s, enum aarch64_ldst_op_data data, { if (offset >= -256 && offset < 256) { tcg_out_ldst_9(s, data, type, rd, rn, offset); - } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset); - tcg_out_ldst_r(s, data, type, rd, rn, TCG_REG_TMP); + return; + } + + if (offset >= 256) { + /* if the offset is naturally aligned and in range, + then we can use the scaled uimm12 encoding */ + unsigned int s_bits = data >> 6; + if (!(offset & ((1 << s_bits) - 1))) { + tcg_target_ulong scaled_uimm = offset >> s_bits; + if (scaled_uimm <= 0xfff) { + tcg_out_ldst_12(s, data, type, rd, rn, scaled_uimm); + return; + } + } } + + /* worst-case scenario, move offset to temp register, use reg offset */ + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset); + tcg_out_ldst_r(s, data, type, rd, rn, TCG_REG_TMP); } /* mov alias implemented with add immediate, useful to move to/from SP */ @@ -706,6 +732,51 @@ static inline void tcg_out_uxt(TCGContext *s, int s_bits, tcg_out_ubfm(s, 0, rd, rn, 0, bits); } +static inline void tcg_out_addi(TCGContext *s, int ext, + TCGReg rd, TCGReg rn, unsigned int aimm) +{ + /* add immediate aimm unsigned 12bit value (with LSL 0 or 12) */ + /* using ADD 0x11000000 | (ext) | (aimm << 10) | (rn << 5) | rd */ + unsigned int base = ext ? 0x91000000 : 0x11000000; + + if (aimm <= 0xfff) { + aimm <<= 10; + } else { + /* we can only shift left by 12, on assert we cannot represent */ + assert(!(aimm & 0xfff)); + assert(aimm <= 0xfff000); + base |= 1 << 22; /* apply LSL 12 */ + aimm >>= 2; + } + + tcg_out32(s, base | aimm | (rn << 5) | rd); +} + +static inline void tcg_out_subi(TCGContext *s, int ext, + TCGReg rd, TCGReg rn, unsigned int aimm) +{ + /* sub immediate aimm unsigned 12bit value (with LSL 0 or 12) */ + /* using SUB 0x51000000 | (ext) | (aimm << 10) | (rn << 5) | rd */ + unsigned int base = ext ? 0xd1000000 : 0x51000000; + + if (aimm <= 0xfff) { + aimm <<= 10; + } else { + /* we can only shift left by 12, on assert we cannot represent */ + assert(!(aimm & 0xfff)); + assert(aimm <= 0xfff000); + base |= 1 << 22; /* apply LSL 12 */ + aimm >>= 2; + } + + tcg_out32(s, base | aimm | (rn << 5) | rd); +} + +static inline void tcg_out_nop(TCGContext *s) +{ + tcg_out32(s, 0xd503201f); +} + #ifdef CONFIG_SOFTMMU #include "exec/softmmu_defs.h" @@ -727,7 +798,125 @@ static const void * const qemu_st_helpers[4] = { helper_stq_mmu, }; -#else /* !CONFIG_SOFTMMU */ +static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +{ + reloc_pc19(lb->label_ptr[0], (tcg_target_long)s->code_ptr); + tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0); + tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, lb->mem_index); + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, + (tcg_target_long)qemu_ld_helpers[lb->opc & 3]); + tcg_out_callr(s, TCG_REG_TMP); + if (lb->opc & 0x04) { + tcg_out_sxt(s, 1, lb->opc & 3, lb->datalo_reg, TCG_REG_X0); + } else { + tcg_out_movr(s, 1, lb->datalo_reg, TCG_REG_X0); + } + + tcg_out_goto(s, (tcg_target_long)lb->raddr); +} + +static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +{ + reloc_pc19(lb->label_ptr[0], (tcg_target_long)s->code_ptr); + + tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0); + tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg); + tcg_out_movr(s, 1, TCG_REG_X2, lb->datalo_reg); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index); + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, + (tcg_target_long)qemu_st_helpers[lb->opc & 3]); + tcg_out_callr(s, TCG_REG_TMP); + + tcg_out_nop(s); + tcg_out_goto(s, (tcg_target_long)lb->raddr); +} + +void tcg_out_tb_finalize(TCGContext *s) +{ + int i; + for (i = 0; i < s->nb_qemu_ldst_labels; i++) { + TCGLabelQemuLdst *label = &s->qemu_ldst_labels[i]; + if (label->is_ld) { + tcg_out_qemu_ld_slow_path(s, label); + } else { + tcg_out_qemu_st_slow_path(s, label); + } + } +} + +static void add_qemu_ldst_label(TCGContext *s, int is_ld, int opc, + TCGReg data_reg, TCGReg addr_reg, + int mem_index, + uint8_t *raddr, uint8_t *label_ptr) +{ + int idx; + TCGLabelQemuLdst *label; + + if (s->nb_qemu_ldst_labels >= TCG_MAX_QEMU_LDST) { + tcg_abort(); + } + + idx = s->nb_qemu_ldst_labels++; + label = &s->qemu_ldst_labels[idx]; + label->is_ld = is_ld; + label->opc = opc; + label->datalo_reg = data_reg; + label->addrlo_reg = addr_reg; + label->mem_index = mem_index; + label->raddr = raddr; + label->label_ptr[0] = label_ptr; +} + +/* Load and compare a TLB entry, emitting the conditional jump to the + slow path for the failure case, which will be patched later when finalizing + the slow path. Generated code returns the host addend in X1, + clobbers X0,X2,X3,TMP. */ +static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, + int s_bits, uint8_t **label_ptr, int mem_index, int is_read) +{ + TCGReg base = TCG_AREG0; + int tlb_offset = is_read ? + offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) + : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write); + /* Extract the TLB index from the address into X0. + X0<CPU_TLB_BITS:0> = + addr_reg<TARGET_PAGE_BITS+CPU_TLB_BITS:TARGET_PAGE_BITS> */ + tcg_out_ubfm(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, addr_reg, + TARGET_PAGE_BITS, TARGET_PAGE_BITS + CPU_TLB_BITS); + /* Store the page mask part of the address and the low s_bits into X3. + Later this allows checking for equality and alignment at the same time. + X3 = addr_reg & (PAGE_MASK | ((1 << s_bits) - 1)) */ + tcg_out_andi(s, (TARGET_LONG_BITS == 64), TCG_REG_X3, addr_reg, + (TARGET_LONG_BITS - TARGET_PAGE_BITS) + s_bits, + (TARGET_LONG_BITS - TARGET_PAGE_BITS)); + /* Add any "high bits" from the tlb offset to the env address into X2, + to take advantage of the LSL12 form of the addi instruction. + X2 = env + (tlb_offset & 0xfff000) */ + tcg_out_addi(s, 1, TCG_REG_X2, base, tlb_offset & 0xfff000); + /* Merge the tlb index contribution into X2. + X2 = X2 + (X0 << CPU_TLB_ENTRY_BITS) */ + tcg_out_arith(s, ARITH_ADD, 1, TCG_REG_X2, TCG_REG_X2, + TCG_REG_X0, -CPU_TLB_ENTRY_BITS); + /* Merge "low bits" from tlb offset, load the tlb comparator into X0. + X0 = load [X2 + (tlb_offset & 0x000fff)] */ + tcg_out_ldst(s, TARGET_LONG_BITS == 64 ? LDST_64 : LDST_32, + LDST_LD, TCG_REG_X0, TCG_REG_X2, + (tlb_offset & 0xfff)); + /* Load the tlb addend. Do that early to avoid stalling. + X1 = load [X2 + (tlb_offset & 0xfff) + offsetof(addend)] */ + tcg_out_ldst(s, LDST_64, LDST_LD, TCG_REG_X1, TCG_REG_X2, + (tlb_offset & 0xfff) + (offsetof(CPUTLBEntry, addend)) - + (is_read ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write))); + /* Perform the address comparison. */ + tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3, 0); + *label_ptr = s->code_ptr; + /* If not equal, we jump to the slow path. */ + tcg_out_goto_cond_noaddr(s, TCG_COND_NE); +} + +#endif /* CONFIG_SOFTMMU */ static void tcg_out_qemu_ld_direct(TCGContext *s, int opc, TCGReg data_r, TCGReg addr_r, TCGReg off_r) @@ -815,13 +1004,13 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int opc, TCGReg data_r, tcg_abort(); } } -#endif /* CONFIG_SOFTMMU */ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) { TCGReg addr_reg, data_reg; #ifdef CONFIG_SOFTMMU int mem_index, s_bits; + uint8_t *label_ptr; #endif data_reg = args[0]; addr_reg = args[1]; @@ -829,23 +1018,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) #ifdef CONFIG_SOFTMMU mem_index = args[2]; s_bits = opc & 3; - - /* TODO: insert TLB lookup here */ - - /* all arguments passed via registers */ - tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0); - tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, addr_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, mem_index); - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, - (tcg_target_long)qemu_ld_helpers[s_bits]); - tcg_out_callr(s, TCG_REG_TMP); - - if (opc & 0x04) { /* sign extend */ - tcg_out_sxt(s, 1, s_bits, data_reg, TCG_REG_X0); - } else { - tcg_out_movr(s, 1, data_reg, TCG_REG_X0); - } - + tcg_out_tlb_read(s, addr_reg, s_bits, &label_ptr, mem_index, 1); + tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, TCG_REG_X1); + add_qemu_ldst_label(s, 1, opc, data_reg, addr_reg, + mem_index, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR); @@ -857,6 +1033,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) TCGReg addr_reg, data_reg; #ifdef CONFIG_SOFTMMU int mem_index, s_bits; + uint8_t *label_ptr; #endif data_reg = args[0]; addr_reg = args[1]; @@ -865,17 +1042,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) mem_index = args[2]; s_bits = opc & 3; - /* TODO: insert TLB lookup here */ - - /* all arguments passed via registers */ - tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0); - tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, addr_reg); - tcg_out_movr(s, 1, TCG_REG_X2, data_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, mem_index); - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, - (tcg_target_long)qemu_st_helpers[s_bits]); - tcg_out_callr(s, TCG_REG_TMP); - + tcg_out_tlb_read(s, addr_reg, s_bits, &label_ptr, mem_index, 0); + tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, TCG_REG_X1); + add_qemu_ldst_label(s, 0, opc, data_reg, addr_reg, + mem_index, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR); @@ -1318,26 +1488,6 @@ static void tcg_target_init(TCGContext *s) tcg_add_target_add_op_defs(aarch64_op_defs); } -static inline void tcg_out_addi(TCGContext *s, int ext, - TCGReg rd, TCGReg rn, unsigned int aimm) -{ - /* add immediate aimm unsigned 12bit value (we use LSL 0 - no shift) */ - /* using ADD 0x11000000 | (ext) | (aimm << 10) | (rn << 5) | rd */ - unsigned int base = ext ? 0x91000000 : 0x11000000; - assert(aimm <= 0xfff); - tcg_out32(s, base | (aimm << 10) | (rn << 5) | rd); -} - -static inline void tcg_out_subi(TCGContext *s, int ext, - TCGReg rd, TCGReg rn, unsigned int aimm) -{ - /* sub immediate aimm unsigned 12bit value (we use LSL 0 - no shift) */ - /* using SUB 0x51000000 | (ext) | (aimm << 10) | (rn << 5) | rd */ - unsigned int base = ext ? 0xd1000000 : 0x51000000; - assert(aimm <= 0xfff); - tcg_out32(s, base | (aimm << 10) | (rn << 5) | rd); -} - static void tcg_target_qemu_prologue(TCGContext *s) { /* NB: frame sizes are in 16 byte stack units! */ diff --git a/tests/Makefile b/tests/Makefile index cdbb79e111..d0449080b1 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -83,6 +83,14 @@ gcov-files-arm-y += hw/tmp105.c check-qtest-ppc-y += tests/boot-order-test$(EXESUF) check-qtest-ppc64-y += tests/boot-order-test$(EXESUF) +check-qapi-schema-y := $(addprefix tests/qapi-schema/, \ + comments.json empty.json funny-char.json indented-expr.json \ + missing-colon.json missing-comma-list.json \ + missing-comma-object.json non-objects.json \ + qapi-schema-test.json quoted-structural-chars.json \ + trailing-comma-list.json trailing-comma-object.json \ + unclosed-list.json unclosed-object.json unclosed-string.json) + GENERATED_HEADERS += tests/test-qapi-types.h tests/test-qapi-visit.h tests/test-qmp-commands.h test-obj-y = tests/check-qint.o tests/check-qstring.o tests/check-qdict.o \ @@ -117,13 +125,13 @@ tests/test-cutils$(EXESUF): tests/test-cutils.o util/cutils.o tests/test-int128$(EXESUF): tests/test-int128.o tests/test-qapi-types.c tests/test-qapi-types.h :\ -$(SRC_PATH)/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-types.py +$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-types.py $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-types.py $(gen-out-type) -o tests -p "test-" < $<, " GEN $@") tests/test-qapi-visit.c tests/test-qapi-visit.h :\ -$(SRC_PATH)/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-visit.py +$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-visit.py $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-visit.py $(gen-out-type) -o tests -p "test-" < $<, " GEN $@") tests/test-qmp-commands.h tests/test-qmp-marshal.c :\ -$(SRC_PATH)/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-commands.py +$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-commands.py $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-commands.py $(gen-out-type) -o tests -p "test-" < $<, " GEN $@") tests/test-string-output-visitor$(EXESUF): tests/test-string-output-visitor.o $(test-qapi-obj-y) libqemuutil.a libqemustub.a @@ -171,6 +179,7 @@ check-help: @echo " make check-qtest-TARGET Run qtest tests for given target" @echo " make check-qtest Run qtest tests" @echo " make check-unit Run qobject tests" + @echo " make check-qapi-schema Run QAPI schema tests" @echo " make check-block Run block tests" @echo " make check-report.html Generates an HTML test report" @echo @@ -233,13 +242,24 @@ check-report.html: check-report.xml check-tests/qemu-iotests-quick.sh: tests/qemu-iotests-quick.sh qemu-img$(EXESUF) qemu-io$(EXESUF) $< +.PHONY: check-tests/test-qapi.py +check-tests/test-qapi.py: tests/test-qapi.py + +.PHONY: $(patsubst %, check-%, $(check-qapi-schema-y)) +$(patsubst %, check-%, $(check-qapi-schema-y)): check-%.json: $(SRC_PATH)/%.json + $(call quiet-command, PYTHONPATH=$(SRC_PATH)/scripts $(PYTHON) $(SRC_PATH)/tests/qapi-schema/test-qapi.py <$^ >$*.out 2>$*.err; echo $$? >$*.exit, " TEST $*.out") + @diff -q $(SRC_PATH)/$*.out $*.out + @diff -q $(SRC_PATH)/$*.err $*.err + @diff -q $(SRC_PATH)/$*.exit $*.exit + # Consolidated targets -.PHONY: check-qtest check-unit check +.PHONY: check-qapi-schema check-qtest check-unit check +check-qapi-schema: $(patsubst %,check-%, $(check-qapi-schema-y)) check-qtest: $(patsubst %,check-qtest-%, $(QTEST_TARGETS)) check-unit: $(patsubst %,check-%, $(check-unit-y)) check-block: $(patsubst %,check-%, $(check-block-y)) -check: check-unit check-qtest +check: check-qapi-schema check-unit check-qtest -include $(wildcard tests/*.d) -include $(wildcard tests/libqos/*.d) diff --git a/tests/qapi-schema/comments.err b/tests/qapi-schema/comments.err new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/comments.err diff --git a/tests/qapi-schema/comments.exit b/tests/qapi-schema/comments.exit new file mode 100644 index 0000000000..573541ac97 --- /dev/null +++ b/tests/qapi-schema/comments.exit @@ -0,0 +1 @@ +0 diff --git a/tests/qapi-schema/comments.json b/tests/qapi-schema/comments.json new file mode 100644 index 0000000000..e643f3a74c --- /dev/null +++ b/tests/qapi-schema/comments.json @@ -0,0 +1,4 @@ +# Unindented comment +{ 'enum': 'Status', # Comment to the right of code + # Indented comment + 'data': [ 'good', 'bad', 'ugly' ] } diff --git a/tests/qapi-schema/comments.out b/tests/qapi-schema/comments.out new file mode 100644 index 0000000000..e3bd904453 --- /dev/null +++ b/tests/qapi-schema/comments.out @@ -0,0 +1,3 @@ +[OrderedDict([('enum', 'Status'), ('data', ['good', 'bad', 'ugly'])])] +['Status'] +[] diff --git a/tests/qapi-schema/empty.err b/tests/qapi-schema/empty.err new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/empty.err diff --git a/tests/qapi-schema/empty.exit b/tests/qapi-schema/empty.exit new file mode 100644 index 0000000000..573541ac97 --- /dev/null +++ b/tests/qapi-schema/empty.exit @@ -0,0 +1 @@ +0 diff --git a/tests/qapi-schema/empty.json b/tests/qapi-schema/empty.json new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/empty.json diff --git a/tests/qapi-schema/empty.out b/tests/qapi-schema/empty.out new file mode 100644 index 0000000000..b7f89a45c6 --- /dev/null +++ b/tests/qapi-schema/empty.out @@ -0,0 +1,3 @@ +[] +[] +[] diff --git a/tests/qapi-schema/funny-char.err b/tests/qapi-schema/funny-char.err new file mode 100644 index 0000000000..d3dd293faf --- /dev/null +++ b/tests/qapi-schema/funny-char.err @@ -0,0 +1 @@ +<stdin>:2:36: Stray ";" diff --git a/tests/qapi-schema/funny-char.exit b/tests/qapi-schema/funny-char.exit new file mode 100644 index 0000000000..d00491fd7e --- /dev/null +++ b/tests/qapi-schema/funny-char.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/funny-char.json b/tests/qapi-schema/funny-char.json new file mode 100644 index 0000000000..d4973a2cdf --- /dev/null +++ b/tests/qapi-schema/funny-char.json @@ -0,0 +1,2 @@ +{ 'enum': 'Status', + 'data': [ 'good', 'bad', 'ugly' ]; } diff --git a/tests/qapi-schema/funny-char.out b/tests/qapi-schema/funny-char.out new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/funny-char.out diff --git a/tests/qapi-schema/indented-expr.err b/tests/qapi-schema/indented-expr.err new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/indented-expr.err diff --git a/tests/qapi-schema/indented-expr.exit b/tests/qapi-schema/indented-expr.exit new file mode 100644 index 0000000000..573541ac97 --- /dev/null +++ b/tests/qapi-schema/indented-expr.exit @@ -0,0 +1 @@ +0 diff --git a/tests/qapi-schema/indented-expr.json b/tests/qapi-schema/indented-expr.json new file mode 100644 index 0000000000..d80af60564 --- /dev/null +++ b/tests/qapi-schema/indented-expr.json @@ -0,0 +1,2 @@ +{ 'id' : 'eins' } + { 'id' : 'zwei' } diff --git a/tests/qapi-schema/indented-expr.out b/tests/qapi-schema/indented-expr.out new file mode 100644 index 0000000000..98af89aa1d --- /dev/null +++ b/tests/qapi-schema/indented-expr.out @@ -0,0 +1,3 @@ +[OrderedDict([('id', 'eins')]), OrderedDict([('id', 'zwei')])] +[] +[] diff --git a/tests/qapi-schema/missing-colon.err b/tests/qapi-schema/missing-colon.err new file mode 100644 index 0000000000..9f2a35515c --- /dev/null +++ b/tests/qapi-schema/missing-colon.err @@ -0,0 +1 @@ +<stdin>:1:10: Expected ":" diff --git a/tests/qapi-schema/missing-colon.exit b/tests/qapi-schema/missing-colon.exit new file mode 100644 index 0000000000..d00491fd7e --- /dev/null +++ b/tests/qapi-schema/missing-colon.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/missing-colon.json b/tests/qapi-schema/missing-colon.json new file mode 100644 index 0000000000..6fc27ce409 --- /dev/null +++ b/tests/qapi-schema/missing-colon.json @@ -0,0 +1,2 @@ +{ 'enum' 'Status', + 'data': [ 'good', 'bad', 'ugly' ] } diff --git a/tests/qapi-schema/missing-colon.out b/tests/qapi-schema/missing-colon.out new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/missing-colon.out diff --git a/tests/qapi-schema/missing-comma-list.err b/tests/qapi-schema/missing-comma-list.err new file mode 100644 index 0000000000..4fe0700195 --- /dev/null +++ b/tests/qapi-schema/missing-comma-list.err @@ -0,0 +1 @@ +<stdin>:2:20: Expected "," or "]" diff --git a/tests/qapi-schema/missing-comma-list.exit b/tests/qapi-schema/missing-comma-list.exit new file mode 100644 index 0000000000..d00491fd7e --- /dev/null +++ b/tests/qapi-schema/missing-comma-list.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/missing-comma-list.json b/tests/qapi-schema/missing-comma-list.json new file mode 100644 index 0000000000..1af39b2930 --- /dev/null +++ b/tests/qapi-schema/missing-comma-list.json @@ -0,0 +1,2 @@ +{ 'enum': 'Status', + 'data': [ 'good' 'bad', 'ugly' ] } diff --git a/tests/qapi-schema/missing-comma-list.out b/tests/qapi-schema/missing-comma-list.out new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/missing-comma-list.out diff --git a/tests/qapi-schema/missing-comma-object.err b/tests/qapi-schema/missing-comma-object.err new file mode 100644 index 0000000000..b0121b5f3a --- /dev/null +++ b/tests/qapi-schema/missing-comma-object.err @@ -0,0 +1 @@ +<stdin>:2:3: Expected "," or "}" diff --git a/tests/qapi-schema/missing-comma-object.exit b/tests/qapi-schema/missing-comma-object.exit new file mode 100644 index 0000000000..d00491fd7e --- /dev/null +++ b/tests/qapi-schema/missing-comma-object.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/missing-comma-object.json b/tests/qapi-schema/missing-comma-object.json new file mode 100644 index 0000000000..50f51786e4 --- /dev/null +++ b/tests/qapi-schema/missing-comma-object.json @@ -0,0 +1,2 @@ +{ 'enum': 'Status' + 'data': [ 'good', 'bad', 'ugly' ] } diff --git a/tests/qapi-schema/missing-comma-object.out b/tests/qapi-schema/missing-comma-object.out new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/missing-comma-object.out diff --git a/tests/qapi-schema/non-objects.err b/tests/qapi-schema/non-objects.err new file mode 100644 index 0000000000..a6c2dc26a6 --- /dev/null +++ b/tests/qapi-schema/non-objects.err @@ -0,0 +1 @@ +<stdin>:1:1: Expected "{" diff --git a/tests/qapi-schema/non-objects.exit b/tests/qapi-schema/non-objects.exit new file mode 100644 index 0000000000..d00491fd7e --- /dev/null +++ b/tests/qapi-schema/non-objects.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/non-objects.json b/tests/qapi-schema/non-objects.json new file mode 100644 index 0000000000..f3fa851d4b --- /dev/null +++ b/tests/qapi-schema/non-objects.json @@ -0,0 +1,2 @@ +'string' +[ ] diff --git a/tests/qapi-schema/non-objects.out b/tests/qapi-schema/non-objects.out new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/non-objects.out diff --git a/tests/qapi-schema/qapi-schema-test.err b/tests/qapi-schema/qapi-schema-test.err new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/qapi-schema-test.err diff --git a/tests/qapi-schema/qapi-schema-test.exit b/tests/qapi-schema/qapi-schema-test.exit new file mode 100644 index 0000000000..573541ac97 --- /dev/null +++ b/tests/qapi-schema/qapi-schema-test.exit @@ -0,0 +1 @@ +0 diff --git a/qapi-schema-test.json b/tests/qapi-schema/qapi-schema-test.json index 4434fa3961..4434fa3961 100644 --- a/qapi-schema-test.json +++ b/tests/qapi-schema/qapi-schema-test.json diff --git a/tests/qapi-schema/qapi-schema-test.out b/tests/qapi-schema/qapi-schema-test.out new file mode 100644 index 0000000000..fb00344894 --- /dev/null +++ b/tests/qapi-schema/qapi-schema-test.out @@ -0,0 +1,19 @@ +[OrderedDict([('enum', 'EnumOne'), ('data', ['value1', 'value2', 'value3'])]), + OrderedDict([('type', 'NestedEnumsOne'), ('data', OrderedDict([('enum1', 'EnumOne'), ('*enum2', 'EnumOne'), ('enum3', 'EnumOne'), ('*enum4', 'EnumOne')]))]), + OrderedDict([('type', 'UserDefOne'), ('data', OrderedDict([('integer', 'int'), ('string', 'str'), ('*enum1', 'EnumOne')]))]), + OrderedDict([('type', 'UserDefTwo'), ('data', OrderedDict([('string', 'str'), ('dict', OrderedDict([('string', 'str'), ('dict', OrderedDict([('userdef', 'UserDefOne'), ('string', 'str')])), ('*dict2', OrderedDict([('userdef', 'UserDefOne'), ('string', 'str')]))]))]))]), + OrderedDict([('type', 'UserDefNested'), ('data', OrderedDict([('string0', 'str'), ('dict1', OrderedDict([('string1', 'str'), ('dict2', OrderedDict([('userdef1', 'UserDefOne'), ('string2', 'str')])), ('*dict3', OrderedDict([('userdef2', 'UserDefOne'), ('string3', 'str')]))]))]))]), + OrderedDict([('type', 'UserDefA'), ('data', OrderedDict([('boolean', 'bool')]))]), + OrderedDict([('type', 'UserDefB'), ('data', OrderedDict([('integer', 'int')]))]), + OrderedDict([('union', 'UserDefUnion'), ('data', OrderedDict([('a', 'UserDefA'), ('b', 'UserDefB')]))]), + OrderedDict([('union', 'UserDefNativeListUnion'), ('data', OrderedDict([('integer', ['int']), ('s8', ['int8']), ('s16', ['int16']), ('s32', ['int32']), ('s64', ['int64']), ('u8', ['uint8']), ('u16', ['uint16']), ('u32', ['uint32']), ('u64', ['uint64']), ('number', ['number']), ('boolean', ['bool']), ('string', ['str'])]))]), + OrderedDict([('command', 'user_def_cmd'), ('data', OrderedDict())]), + OrderedDict([('command', 'user_def_cmd1'), ('data', OrderedDict([('ud1a', 'UserDefOne')]))]), + OrderedDict([('command', 'user_def_cmd2'), ('data', OrderedDict([('ud1a', 'UserDefOne'), ('ud1b', 'UserDefOne')])), ('returns', 'UserDefTwo')])] +['EnumOne', 'UserDefUnionKind', 'UserDefNativeListUnionKind'] +[OrderedDict([('type', 'NestedEnumsOne'), ('data', OrderedDict([('enum1', 'EnumOne'), ('*enum2', 'EnumOne'), ('enum3', 'EnumOne'), ('*enum4', 'EnumOne')]))]), + OrderedDict([('type', 'UserDefOne'), ('data', OrderedDict([('integer', 'int'), ('string', 'str'), ('*enum1', 'EnumOne')]))]), + OrderedDict([('type', 'UserDefTwo'), ('data', OrderedDict([('string', 'str'), ('dict', OrderedDict([('string', 'str'), ('dict', OrderedDict([('userdef', 'UserDefOne'), ('string', 'str')])), ('*dict2', OrderedDict([('userdef', 'UserDefOne'), ('string', 'str')]))]))]))]), + OrderedDict([('type', 'UserDefNested'), ('data', OrderedDict([('string0', 'str'), ('dict1', OrderedDict([('string1', 'str'), ('dict2', OrderedDict([('userdef1', 'UserDefOne'), ('string2', 'str')])), ('*dict3', OrderedDict([('userdef2', 'UserDefOne'), ('string3', 'str')]))]))]))]), + OrderedDict([('type', 'UserDefA'), ('data', OrderedDict([('boolean', 'bool')]))]), + OrderedDict([('type', 'UserDefB'), ('data', OrderedDict([('integer', 'int')]))])] diff --git a/tests/qapi-schema/quoted-structural-chars.err b/tests/qapi-schema/quoted-structural-chars.err new file mode 100644 index 0000000000..a6c2dc26a6 --- /dev/null +++ b/tests/qapi-schema/quoted-structural-chars.err @@ -0,0 +1 @@ +<stdin>:1:1: Expected "{" diff --git a/tests/qapi-schema/quoted-structural-chars.exit b/tests/qapi-schema/quoted-structural-chars.exit new file mode 100644 index 0000000000..d00491fd7e --- /dev/null +++ b/tests/qapi-schema/quoted-structural-chars.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/quoted-structural-chars.json b/tests/qapi-schema/quoted-structural-chars.json new file mode 100644 index 0000000000..9fe657ae9c --- /dev/null +++ b/tests/qapi-schema/quoted-structural-chars.json @@ -0,0 +1 @@ +'{' 'key1' ':' 'value1' ',' 'key2' ':' '[' ']' '}' diff --git a/tests/qapi-schema/quoted-structural-chars.out b/tests/qapi-schema/quoted-structural-chars.out new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/quoted-structural-chars.out diff --git a/tests/qapi-schema/test-qapi.py b/tests/qapi-schema/test-qapi.py new file mode 100644 index 0000000000..b3d1e1dbce --- /dev/null +++ b/tests/qapi-schema/test-qapi.py @@ -0,0 +1,27 @@ +# +# QAPI parser test harness +# +# Copyright (c) 2013 Red Hat Inc. +# +# Authors: +# Markus Armbruster <armbru@redhat.com> +# +# This work is licensed under the terms of the GNU GPL, version 2 or later. +# See the COPYING file in the top-level directory. +# + +from qapi import * +from pprint import pprint +import sys + +try: + exprs = parse_schema(sys.stdin) +except SystemExit: + raise +except: + print >>sys.stderr, "Crashed:", sys.exc_info()[0] + exit(1) + +pprint(exprs) +pprint(enum_types) +pprint(struct_types) diff --git a/tests/qapi-schema/trailing-comma-list.err b/tests/qapi-schema/trailing-comma-list.err new file mode 100644 index 0000000000..ff839a34e9 --- /dev/null +++ b/tests/qapi-schema/trailing-comma-list.err @@ -0,0 +1 @@ +<stdin>:2:36: Expected "{", "[" or string diff --git a/tests/qapi-schema/trailing-comma-list.exit b/tests/qapi-schema/trailing-comma-list.exit new file mode 100644 index 0000000000..d00491fd7e --- /dev/null +++ b/tests/qapi-schema/trailing-comma-list.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/trailing-comma-list.json b/tests/qapi-schema/trailing-comma-list.json new file mode 100644 index 0000000000..9b0c8bd70b --- /dev/null +++ b/tests/qapi-schema/trailing-comma-list.json @@ -0,0 +1,2 @@ +{ 'enum': 'Status', + 'data': [ 'good', 'bad', 'ugly', ] } diff --git a/tests/qapi-schema/trailing-comma-list.out b/tests/qapi-schema/trailing-comma-list.out new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/trailing-comma-list.out diff --git a/tests/qapi-schema/trailing-comma-object.err b/tests/qapi-schema/trailing-comma-object.err new file mode 100644 index 0000000000..f5409627da --- /dev/null +++ b/tests/qapi-schema/trailing-comma-object.err @@ -0,0 +1 @@ +<stdin>:2:38: Expected string diff --git a/tests/qapi-schema/trailing-comma-object.exit b/tests/qapi-schema/trailing-comma-object.exit new file mode 100644 index 0000000000..d00491fd7e --- /dev/null +++ b/tests/qapi-schema/trailing-comma-object.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/trailing-comma-object.json b/tests/qapi-schema/trailing-comma-object.json new file mode 100644 index 0000000000..bbaea550c8 --- /dev/null +++ b/tests/qapi-schema/trailing-comma-object.json @@ -0,0 +1,2 @@ +{ 'enum': 'Status', + 'data': [ 'good', 'bad', 'ugly' ], } diff --git a/tests/qapi-schema/trailing-comma-object.out b/tests/qapi-schema/trailing-comma-object.out new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/trailing-comma-object.out diff --git a/tests/qapi-schema/unclosed-list.err b/tests/qapi-schema/unclosed-list.err new file mode 100644 index 0000000000..0e837a7fad --- /dev/null +++ b/tests/qapi-schema/unclosed-list.err @@ -0,0 +1 @@ +<stdin>:1:20: Expected "," or "]" diff --git a/tests/qapi-schema/unclosed-list.exit b/tests/qapi-schema/unclosed-list.exit new file mode 100644 index 0000000000..d00491fd7e --- /dev/null +++ b/tests/qapi-schema/unclosed-list.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/unclosed-list.json b/tests/qapi-schema/unclosed-list.json new file mode 100644 index 0000000000..e3e9566982 --- /dev/null +++ b/tests/qapi-schema/unclosed-list.json @@ -0,0 +1 @@ +{ 'key': [ 'value' } diff --git a/tests/qapi-schema/unclosed-list.out b/tests/qapi-schema/unclosed-list.out new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/unclosed-list.out diff --git a/tests/qapi-schema/unclosed-object.err b/tests/qapi-schema/unclosed-object.err new file mode 100644 index 0000000000..e6dc9501dc --- /dev/null +++ b/tests/qapi-schema/unclosed-object.err @@ -0,0 +1 @@ +<stdin>:1:21: Expected "," or "}" diff --git a/tests/qapi-schema/unclosed-object.exit b/tests/qapi-schema/unclosed-object.exit new file mode 100644 index 0000000000..d00491fd7e --- /dev/null +++ b/tests/qapi-schema/unclosed-object.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/unclosed-object.json b/tests/qapi-schema/unclosed-object.json new file mode 100644 index 0000000000..8ac069dce3 --- /dev/null +++ b/tests/qapi-schema/unclosed-object.json @@ -0,0 +1 @@ +{ 'key': [ 'value' ] diff --git a/tests/qapi-schema/unclosed-object.out b/tests/qapi-schema/unclosed-object.out new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/unclosed-object.out diff --git a/tests/qapi-schema/unclosed-string.err b/tests/qapi-schema/unclosed-string.err new file mode 100644 index 0000000000..948d88339d --- /dev/null +++ b/tests/qapi-schema/unclosed-string.err @@ -0,0 +1 @@ +<stdin>:1:11: Missing terminating "'" diff --git a/tests/qapi-schema/unclosed-string.exit b/tests/qapi-schema/unclosed-string.exit new file mode 100644 index 0000000000..d00491fd7e --- /dev/null +++ b/tests/qapi-schema/unclosed-string.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/unclosed-string.json b/tests/qapi-schema/unclosed-string.json new file mode 100644 index 0000000000..8c16b6b6f6 --- /dev/null +++ b/tests/qapi-schema/unclosed-string.json @@ -0,0 +1,2 @@ +{ 'text': 'lorem ips +} diff --git a/tests/qapi-schema/unclosed-string.out b/tests/qapi-schema/unclosed-string.out new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/qapi-schema/unclosed-string.out diff --git a/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c b/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c index ce864844d9..cbf900713f 100644 --- a/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c +++ b/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c @@ -14,7 +14,7 @@ int main() resultdsp = 0x01; __asm ("mthi %0, $ac1\n\t" - "mtlo %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" "dpaq_sa.l.w $ac1, %3, %4\n\t" "mfhi %0, $ac1\n\t" "mflo %1, $ac1\n\t" @@ -27,8 +27,8 @@ int main() assert(ach == resulth); assert(acl == resultl); - ach = 0x12; - acl = 0x48; + ach = 0x00000012; + acl = 0x00000048; rs = 0x80000000; rt = 0x80000000; @@ -37,7 +37,7 @@ int main() resultdsp = 0x01; __asm ("mthi %0, $ac1\n\t" - "mtlo %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" "dpaq_sa.l.w $ac1, %3, %4\n\t" "mfhi %0, $ac1\n\t" "mflo %1, $ac1\n\t" @@ -51,16 +51,64 @@ int main() assert(acl == resultl); ach = 0x741532A0; - acl = 0xfceabb08; + acl = 0xFCEABB08; rs = 0x80000000; rt = 0x80000000; - resulth = 0x7fffffff; - resultl = 0xffffffff; + resulth = 0x7FFFFFFF; + resultl = 0xFFFFFFFF; resultdsp = 0x01; __asm ("mthi %0, $ac1\n\t" - "mtlo %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + ach = 0; + acl = 0; + rs = 0xC0000000; + rt = 0x7FFFFFFF; + + resulth = 0xC0000000; + resultl = 0x80000000; + resultdsp = 0; + __asm + ("wrdsp $0\n\t" + "mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + ach = 0x20000000; + acl = 0; + rs = 0xE0000000; + rt = 0x7FFFFFFF; + + resulth = 0; + resultl = 0x40000000; + resultdsp = 0; + __asm + ("wrdsp $0\n\t" + "mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" "dpaq_sa.l.w $ac1, %3, %4\n\t" "mfhi %0, $ac1\n\t" "mflo %1, $ac1\n\t" diff --git a/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c b/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c index b7b73fdb66..eda3b14e2b 100644 --- a/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c +++ b/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c @@ -9,8 +9,8 @@ int main() rs = 0xBC0123AD; rt = 0x01643721; - resulth = 0xfdf4cbe0; - resultl = 0xd138776b; + resulth = 0x00BD3A22; + resultl = 0xD138776B; resultdsp = 0x00; __asm ("mthi %0, $ac1\n\t" diff --git a/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c b/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c index c7206039ea..370c2a8018 100644 --- a/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c +++ b/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c @@ -12,7 +12,24 @@ int main() resultdsp = 1; __asm - ("mulq_rs.ph %0, %2, %3\n\t" + ("wrdsp $0\n\t" + "mulq_rs.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + rs = 0x80011234; + rt = 0x80024321; + result = 0x7FFD098C; + resultdsp = 0; + + __asm + ("wrdsp $0\n\t" + "mulq_rs.ph %0, %2, %3\n\t" "rddsp %1\n\t" : "=r"(rd), "=r"(dsp) : "r"(rs), "r"(rt) diff --git a/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c index 3535b37a58..da6845bf24 100644 --- a/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c +++ b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c @@ -12,18 +12,34 @@ int main() result = 0x12348765; __asm - ("precrq_rs.ph.w %0, %1, %2\n\t" + ("wrdsp $0\n\t" + "precrq_rs.ph.w %0, %1, %2\n\t" : "=r"(rd) : "r"(rs), "r"(rt) ); assert(result == rd); - rs = 0x7fffC678; + rs = 0x7FFFC678; rt = 0x865432A0; - result = 0x7fff8654; + result = 0x7FFF8654; __asm - ("precrq_rs.ph.w %0, %2, %3\n\t" + ("wrdsp $0\n\t" + "precrq_rs.ph.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(((dsp >> 22) & 0x01) == 1); + assert(result == rd); + + rs = 0xBEEFFEED; + rt = 0x7FFF8000; + result = 0xBEF07FFF; + + __asm + ("wrdsp $0\n\t" + "precrq_rs.ph.w %0, %2, %3\n\t" "rddsp %1\n\t" : "=r"(rd), "=r"(dsp) : "r"(rs), "r"(rt) diff --git a/tests/test-qmp-input-visitor.c b/tests/test-qmp-input-visitor.c index 2741eef3fa..0beb8fbfd2 100644 --- a/tests/test-qmp-input-visitor.c +++ b/tests/test-qmp-input-visitor.c @@ -394,7 +394,7 @@ static void test_native_list_integer_helper(TestInputVisitorData *data, break; } default: - g_assert(false); + g_assert_not_reached(); } g_string_free(gstr_union, true); diff --git a/tests/test-qmp-output-visitor.c b/tests/test-qmp-output-visitor.c index b2fa9a74f6..e073d833bf 100644 --- a/tests/test-qmp-output-visitor.c +++ b/tests/test-qmp-output-visitor.c @@ -559,7 +559,7 @@ static void init_native_list(UserDefNativeListUnion *cvalue) break; } default: - g_assert(false); + g_assert_not_reached(); } } @@ -645,7 +645,7 @@ static void check_native_list(QObject *qobj, } break; default: - g_assert(false); + g_assert_not_reached(); } QDECREF(qlist); } diff --git a/tests/test-visitor-serialization.c b/tests/test-visitor-serialization.c index ee7916b806..9aaa5872e5 100644 --- a/tests/test-visitor-serialization.c +++ b/tests/test-visitor-serialization.c @@ -136,7 +136,7 @@ static void visit_primitive_type(Visitor *v, void **native, Error **errp) visit_type_int64(v, &pt->value.s64, NULL, errp); break; case PTYPE_EOL: - g_assert(false); + g_assert_not_reached(); } } @@ -181,7 +181,7 @@ static void visit_primitive_list(Visitor *v, void **native, Error **errp) visit_type_uint64List(v, &pl->value.u64_integers, NULL, errp); break; default: - g_assert(false); + g_assert_not_reached(); } } @@ -500,7 +500,7 @@ static void test_primitive_lists(gconstpointer opaque) break; } default: - g_assert(0); + g_assert_not_reached(); } } @@ -656,7 +656,7 @@ static void test_primitive_lists(gconstpointer opaque) break; } default: - g_assert(0); + g_assert_not_reached(); } i++; } while (cur_head); @@ -32,7 +32,7 @@ static TPMDriverOps const *be_drivers[TPM_MAX_DRIVERS] = { }; static enum TpmModel tpm_models[TPM_MAX_MODELS] = { - -1, + TPM_MODEL_MAX, }; int tpm_register_model(enum TpmModel model) @@ -40,7 +40,7 @@ int tpm_register_model(enum TpmModel model) int i; for (i = 0; i < TPM_MAX_MODELS; i++) { - if (tpm_models[i] == -1) { + if (tpm_models[i] == TPM_MODEL_MAX) { tpm_models[i] = model; return 0; } diff --git a/trace-events b/trace-events index 002df83b9d..3856b5c206 100644 --- a/trace-events +++ b/trace-events @@ -1165,6 +1165,14 @@ kvm_vm_ioctl(int type, void *arg) "type %d, arg %p" kvm_vcpu_ioctl(int cpu_index, int type, void *arg) "cpu_index %d, type %d, arg %p" kvm_run_exit(int cpu_index, uint32_t reason) "cpu_index %d, reason %d" +# memory.c +memory_region_ops_read(void *mr, uint64_t addr, uint64_t value, unsigned size) "mr %p addr %#"PRIx64" value %#"PRIx64" size %u" +memory_region_ops_write(void *mr, uint64_t addr, uint64_t value, unsigned size) "mr %p addr %#"PRIx64" value %#"PRIx64" size %u" + # qom/object.c object_dynamic_cast_assert(const char *type, const char *target, const char *file, int line, const char *func) "%s->%s (%s:%d:%s)" object_class_dynamic_cast_assert(const char *type, const char *target, const char *file, int line, const char *func) "%s->%s (%s:%d:%s)" + +# hw/xen/xen_pvdevice.c +xen_pv_mmio_read(uint64_t addr) "WARNING: read from Xen PV Device MMIO space (address %"PRIx64")" +xen_pv_mmio_write(uint64_t addr) "WARNING: write to Xen PV Device MMIO space (address %"PRIx64")" diff --git a/util/aes.c b/util/aes.c index 91e97fa6e7..4b4d88e7e6 100644 --- a/util/aes.c +++ b/util/aes.c @@ -30,12 +30,7 @@ #include "qemu-common.h" #include "qemu/aes.h" -#ifndef NDEBUG -#define NDEBUG -#endif - typedef uint32_t u32; -typedef uint16_t u16; typedef uint8_t u8; /* This controls loop-unrolling in aes_core.c */ |
