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-rw-r--r--hw/adb.c13
-rw-r--r--hw/cuda.c39
-rw-r--r--hw/grackle_pci.c16
-rw-r--r--hw/heathrow_pic.c20
-rw-r--r--hw/mac_dbdma.c20
-rw-r--r--hw/mac_nvram.c18
6 files changed, 90 insertions, 36 deletions
diff --git a/hw/adb.c b/hw/adb.c
index 5c0d6d5fd9..d6b0298b1c 100644
--- a/hw/adb.c
+++ b/hw/adb.c
@@ -25,6 +25,16 @@
#include "ppc_mac.h"
#include "console.h"
+/* debug ADB */
+//#define DEBUG_ADB
+
+#ifdef DEBUG_ADB
+#define ADB_DPRINTF(fmt, args...) \
+do { printf("ADB: " fmt , ##args); } while (0)
+#else
+#define ADB_DPRINTF(fmt, args...)
+#endif
+
/* ADB commands */
#define ADB_BUSRESET 0x00
#define ADB_FLUSH 0x01
@@ -351,6 +361,7 @@ static int adb_mouse_request(ADBDevice *d, uint8_t *obuf,
olen = 0;
switch(cmd) {
case ADB_WRITEREG:
+ ADB_DPRINTF("write reg %d val 0x%2.2x\n", reg, buf[1]);
switch(reg) {
case 2:
break;
@@ -383,6 +394,8 @@ static int adb_mouse_request(ADBDevice *d, uint8_t *obuf,
olen = 2;
break;
}
+ ADB_DPRINTF("read reg %d obuf[0] 0x%2.2x obuf[1] 0x%2.2x\n", reg,
+ obuf[0], obuf[1]);
break;
}
return olen;
diff --git a/hw/cuda.c b/hw/cuda.c
index 246c72d867..c8949088d2 100644
--- a/hw/cuda.c
+++ b/hw/cuda.c
@@ -29,9 +29,19 @@
/* XXX: implement all timer modes */
+/* debug CUDA */
//#define DEBUG_CUDA
+
+/* debug CUDA packets */
//#define DEBUG_CUDA_PACKET
+#ifdef DEBUG_CUDA
+#define CUDA_DPRINTF(fmt, args...) \
+do { printf("CUDA: " fmt , ##args); } while (0)
+#else
+#define CUDA_DPRINTF(fmt, args...)
+#endif
+
/* Bits in B data register: all active low */
#define TREQ 0x08 /* Transfer request (input) */
#define TACK 0x10 /* Transfer acknowledge (output) */
@@ -176,10 +186,7 @@ static unsigned int get_counter(CUDATimer *s)
static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
{
-#ifdef DEBUG_CUDA
- printf("cuda: T%d.counter=%d\n",
- 1 + (ti->timer == NULL), val);
-#endif
+ CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val);
ti->load_time = qemu_get_clock(vm_clock);
ti->counter_value = val;
cuda_timer_update(s, ti, ti->load_time);
@@ -209,12 +216,8 @@ static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
} else {
next_time = d + counter;
}
-#if 0
-#ifdef DEBUG_CUDA
- printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
- s->latch, d, next_time - d);
-#endif
-#endif
+ CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
+ s->latch, d, next_time - d);
next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
s->load_time;
if (next_time <= current_time)
@@ -311,10 +314,8 @@ static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
val = s->anh;
break;
}
-#ifdef DEBUG_CUDA
if (addr != 13 || val != 0)
- printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
-#endif
+ CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val);
return val;
}
@@ -323,9 +324,7 @@ static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
CUDAState *s = opaque;
addr = (addr >> 9) & 0xf;
-#ifdef DEBUG_CUDA
- printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
-#endif
+ CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val);
switch(addr) {
case 0:
@@ -412,9 +411,7 @@ static void cuda_update(CUDAState *s)
/* data output */
if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
if (s->data_out_index < sizeof(s->data_out)) {
-#ifdef DEBUG_CUDA
- printf("cuda: send: %02x\n", s->sr);
-#endif
+ CUDA_DPRINTF("send: %02x\n", s->sr);
s->data_out[s->data_out_index++] = s->sr;
s->ifr |= SR_INT;
cuda_update_irq(s);
@@ -425,9 +422,7 @@ static void cuda_update(CUDAState *s)
/* data input */
if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
s->sr = s->data_in[s->data_in_index++];
-#ifdef DEBUG_CUDA
- printf("cuda: recv: %02x\n", s->sr);
-#endif
+ CUDA_DPRINTF("recv: %02x\n", s->sr);
/* indicate end of transfer */
if (s->data_in_index >= s->data_in_size) {
s->b = (s->b | TREQ);
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index c6aee94822..c11b9ef733 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -27,6 +27,16 @@
#include "ppc_mac.h"
#include "pci.h"
+/* debug Grackle */
+//#define DEBUG_GRACKLE
+
+#ifdef DEBUG_GRACKLE
+#define GRACKLE_DPRINTF(fmt, args...) \
+do { printf("GRACKLE: " fmt , ##args); } while (0)
+#else
+#define GRACKLE_DPRINTF(fmt, args...)
+#endif
+
typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"
@@ -36,6 +46,9 @@ static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
GrackleState *s = opaque;
+
+ GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
+ val);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
@@ -51,6 +64,8 @@ static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
+ GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
+ val);
return val;
}
@@ -86,6 +101,7 @@ static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level)
{
+ GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
qemu_set_irq(pic[irq_num + 0x15], level);
}
diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c
index dc2a30c852..35bb764e70 100644
--- a/hw/heathrow_pic.c
+++ b/hw/heathrow_pic.c
@@ -25,7 +25,15 @@
#include "hw.h"
#include "ppc_mac.h"
-//#define DEBUG
+/* debug PIC */
+//#define DEBUG_PIC
+
+#ifdef DEBUG_PIC
+#define PIC_DPRINTF(fmt, args...) \
+do { printf("PIC: " fmt , ##args); } while (0)
+#else
+#define PIC_DPRINTF(fmt, args...)
+#endif
typedef struct HeathrowPIC {
uint32_t events;
@@ -64,9 +72,7 @@ static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
value = bswap32(value);
#endif
n = ((addr & 0xfff) - 0x10) >> 4;
-#ifdef DEBUG
- printf("pic_writel: " PADDRX " %u: %08x\n", addr, n, value);
-#endif
+ PIC_DPRINTF("writel: " TARGET_FMT_plx " %u: %08x\n", addr, n, value);
if (n >= 2)
return;
pic = &s->pics[n];
@@ -113,9 +119,7 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
break;
}
}
-#ifdef DEBUG
- printf("pic_readl: " PADDRX " %u: %08x\n", addr, n, value);
-#endif
+ PIC_DPRINTF("readl: " TARGET_FMT_plx " %u: %08x\n", addr, n, value);
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
@@ -145,7 +149,7 @@ static void heathrow_pic_set_irq(void *opaque, int num, int level)
{
static int last_level[64];
if (last_level[num] != level) {
- printf("set_irq: num=0x%02x level=%d\n", num, level);
+ PIC_DPRINTF("set_irq: num=0x%02x level=%d\n", num, level);
last_level[num] = level;
}
}
diff --git a/hw/mac_dbdma.c b/hw/mac_dbdma.c
index 401384c4c8..c23fbd5b9e 100644
--- a/hw/mac_dbdma.c
+++ b/hw/mac_dbdma.c
@@ -25,38 +25,54 @@
#include "hw.h"
#include "ppc_mac.h"
+/* debug DBDMA */
+//#define DEBUG_DBDMA
+
+#ifdef DEBUG_DBDMA
+#define DBDMA_DPRINTF(fmt, args...) \
+do { printf("DBDMA: " fmt , ##args); } while (0)
+#else
+#define DBDMA_DPRINTF(fmt, args...)
+#endif
+
/* DBDMA: currently no op - should suffice right now */
static void dbdma_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
- printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value);
+ DBDMA_DPRINTF("writeb 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
}
static void dbdma_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
+ DBDMA_DPRINTF("writew 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
}
static void dbdma_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
+ DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
}
static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
{
- printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr);
+ DBDMA_DPRINTF("readb 0x" TARGET_FMT_plx " => 0\n", addr);
return 0;
}
static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr)
{
+ DBDMA_DPRINTF("readw 0x" TARGET_FMT_plx " => 0\n", addr);
+
return 0;
}
static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
{
+ DBDMA_DPRINTF("readl 0x" TARGET_FMT_plx " => 0\n", addr);
+
return 0;
}
diff --git a/hw/mac_nvram.c b/hw/mac_nvram.c
index f608ace71d..3787f54d65 100644
--- a/hw/mac_nvram.c
+++ b/hw/mac_nvram.c
@@ -25,6 +25,16 @@
#include "hw.h"
#include "ppc_mac.h"
+/* debug NVR */
+//#define DEBUG_NVR
+
+#ifdef DEBUG_NVR
+#define NVR_DPRINTF(fmt, args...) \
+do { printf("NVR: " fmt , ##args); } while (0)
+#else
+#define NVR_DPRINTF(fmt, args...)
+#endif
+
struct MacIONVRAMState {
target_phys_addr_t size;
int mem_index;
@@ -37,11 +47,11 @@ uint32_t macio_nvram_read (void *opaque, uint32_t addr)
MacIONVRAMState *s = opaque;
uint32_t ret;
- // printf("%s: %p addr %04x\n", __func__, s, addr);
if (addr < 0x2000)
ret = s->data[addr];
else
ret = -1;
+ NVR_DPRINTF("read addr %04x val %x\n", addr, ret);
return ret;
}
@@ -50,7 +60,7 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val)
{
MacIONVRAMState *s = opaque;
- // printf("%s: %p addr %04x val %02x\n", __func__, s, addr, val);
+ NVR_DPRINTF("write addr %04x val %x\n", addr, val);
if (addr < 0x2000)
s->data[addr] = val;
}
@@ -63,7 +73,7 @@ static void macio_nvram_writeb (void *opaque,
addr = (addr >> 4) & 0x1fff;
s->data[addr] = value;
- // printf("macio_nvram_writeb %04x = %02x\n", addr, value);
+ NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
}
static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
@@ -73,7 +83,7 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
addr = (addr >> 4) & 0x1fff;
value = s->data[addr];
- // printf("macio_nvram_readb %04x = %02x\n", addr, value);
+ NVR_DPRINTF("readb addr %04x val %x\n", (int)addr, value);
return value;
}