diff options
| -rw-r--r-- | linux-user/main.c | 7 | ||||
| -rw-r--r-- | target-alpha/helper.h | 2 | ||||
| -rw-r--r-- | target-alpha/op_helper.c | 28 | ||||
| -rw-r--r-- | target-alpha/translate.c | 19 |
4 files changed, 23 insertions, 33 deletions
diff --git a/linux-user/main.c b/linux-user/main.c index 71a1b6737e..5680d8e0cd 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2358,6 +2358,11 @@ void cpu_loop (CPUState *env) while (1) { trapnr = cpu_alpha_exec (env); + /* All of the traps imply a transition through PALcode, which + implies an REI instruction has been executed. Which means + that the intr_flag should be cleared. */ + env->intr_flag = 0; + switch (trapnr) { case EXCP_RESET: fprintf(stderr, "Reset requested. Exit\n"); @@ -2444,7 +2449,7 @@ void cpu_loop (CPUState *env) env->ir[IR_A0], env->ir[IR_A1], env->ir[IR_A2], env->ir[IR_A3], env->ir[IR_A4], env->ir[IR_A5]); - if (trapnr != TARGET_NR_sigreturn + if (trapnr != TARGET_NR_sigreturn && trapnr != TARGET_NR_rt_sigreturn) { env->ir[IR_V0] = (sysret < 0 ? -sysret : sysret); env->ir[IR_A3] = (sysret < 0); diff --git a/target-alpha/helper.h b/target-alpha/helper.h index 73413f2a80..10c78d0e0e 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -2,8 +2,6 @@ DEF_HELPER_2(excp, void, int, int) DEF_HELPER_FLAGS_0(load_pcc, TCG_CALL_CONST | TCG_CALL_PURE, i64) -DEF_HELPER_FLAGS_0(rc, TCG_CALL_CONST, i64) -DEF_HELPER_FLAGS_0(rs, TCG_CALL_CONST, i64) DEF_HELPER_2(addqv, i64, i64, i64) DEF_HELPER_2(addlv, i64, i64, i64) diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index ded71f689e..f9cd07a6ee 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -47,32 +47,6 @@ void helper_store_fpcr (uint64_t val) cpu_alpha_store_fpcr (env, val); } -static spinlock_t intr_cpu_lock = SPIN_LOCK_UNLOCKED; - -uint64_t helper_rs(void) -{ - uint64_t tmp; - - spin_lock(&intr_cpu_lock); - tmp = env->intr_flag; - env->intr_flag = 1; - spin_unlock(&intr_cpu_lock); - - return tmp; -} - -uint64_t helper_rc(void) -{ - uint64_t tmp; - - spin_lock(&intr_cpu_lock); - tmp = env->intr_flag; - env->intr_flag = 0; - spin_unlock(&intr_cpu_lock); - - return tmp; -} - uint64_t helper_addqv (uint64_t op1, uint64_t op2) { uint64_t tmp = op1; @@ -1191,6 +1165,7 @@ void helper_hw_rei (void) { env->pc = env->ipr[IPR_EXC_ADDR] & ~3; env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1; + env->intr_flag = 0; /* XXX: re-enable interrupts and memory mapping */ } @@ -1198,6 +1173,7 @@ void helper_hw_ret (uint64_t a) { env->pc = a & ~3; env->ipr[IPR_EXC_ADDR] = a & 1; + env->intr_flag = 0; /* XXX: re-enable interrupts and memory mapping */ } diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 96d876b56b..1c296cfbb4 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1301,6 +1301,19 @@ static void gen_cmp(TCGCond cond, int ra, int rb, int rc, } } +static void gen_rx(int ra, int set) +{ + TCGv_i32 tmp; + + if (ra != 31) { + tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, offsetof(CPUState, intr_flag)); + } + + tmp = tcg_const_i32(set); + tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUState, intr_flag)); + tcg_temp_free_i32(tmp); +} + static inline int translate_one(DisasContext *ctx, uint32_t insn) { uint32_t palcode; @@ -2392,16 +2405,14 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn) break; case 0xE000: /* RC */ - if (ra != 31) - gen_helper_rc(cpu_ir[ra]); + gen_rx(ra, 0); break; case 0xE800: /* ECB */ break; case 0xF000: /* RS */ - if (ra != 31) - gen_helper_rs(cpu_ir[ra]); + gen_rx(ra, 1); break; case 0xF800: /* WH64 */ |