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-rw-r--r--target-arm/cpu-qom.h1
-rw-r--r--target-arm/cpu.c9
-rw-r--r--target-arm/helper.c10
3 files changed, 12 insertions, 8 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 7e2d4c942e..7cc4cd51ba 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -70,6 +70,7 @@ typedef struct ARMCPU {
* prefix means a constant register.
*/
uint32_t midr;
+ uint32_t reset_fpsid;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 46fbc2d073..5fb78030a3 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -100,6 +100,7 @@ static void arm926_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM926;
+ cpu->reset_fpsid = 0x41011090;
}
static void arm946_initfn(Object *obj)
@@ -117,6 +118,7 @@ static void arm1026_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
cpu->midr = ARM_CPUID_ARM1026;
+ cpu->reset_fpsid = 0x410110a0;
}
static void arm1136_r2_initfn(Object *obj)
@@ -125,6 +127,7 @@ static void arm1136_r2_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136_R2;
+ cpu->reset_fpsid = 0x410120b4;
}
static void arm1136_initfn(Object *obj)
@@ -134,6 +137,7 @@ static void arm1136_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136;
+ cpu->reset_fpsid = 0x410120b4;
}
static void arm1176_initfn(Object *obj)
@@ -143,6 +147,7 @@ static void arm1176_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM1176;
+ cpu->reset_fpsid = 0x410120b5;
}
static void arm11mpcore_initfn(Object *obj)
@@ -152,6 +157,7 @@ static void arm11mpcore_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM11MPCORE;
+ cpu->reset_fpsid = 0x410120b4;
}
static void cortex_m3_initfn(Object *obj)
@@ -170,6 +176,7 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
cpu->midr = ARM_CPUID_CORTEXA8;
+ cpu->reset_fpsid = 0x410330c0;
}
static void cortex_a9_initfn(Object *obj)
@@ -186,6 +193,7 @@ static void cortex_a9_initfn(Object *obj)
*/
set_feature(&cpu->env, ARM_FEATURE_V7MP);
cpu->midr = ARM_CPUID_CORTEXA9;
+ cpu->reset_fpsid = 0x41033090;
}
static void cortex_a15_initfn(Object *obj)
@@ -200,6 +208,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V7MP);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
cpu->midr = ARM_CPUID_CORTEXA15;
+ cpu->reset_fpsid = 0x410430f0;
}
static void ti925t_initfn(Object *obj)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e495de683b..3247dd31d7 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -50,7 +50,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
case ARM_CPUID_ARM926:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
@@ -59,7 +58,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
@@ -74,7 +72,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
*/
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -83,7 +80,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -92,7 +88,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -100,7 +95,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -113,7 +107,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -125,7 +118,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA15:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -201,6 +193,8 @@ void cpu_state_reset(CPUARMState *env)
cpu_reset_model_id(env, id);
env->cp15.c15_config_base_address = tmp;
env->cp15.c0_cpuid = cpu->midr;
+ env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
+
#if defined (CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
/* For user mode we must enable access to coprocessors */
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-25 20:10:35 +0000