diff options
| -rw-r--r-- | target-arm/cpu.h | 2 | ||||
| -rw-r--r-- | target-arm/machine.c | 22 |
2 files changed, 22 insertions, 2 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 194f16cc71..afc2bfebb4 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -405,7 +405,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list -#define CPU_SAVE_VERSION 1 +#define CPU_SAVE_VERSION 2 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel diff --git a/target-arm/machine.c b/target-arm/machine.c index b1deacb8f6..3925d3a2d5 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -22,12 +22,15 @@ void cpu_save(QEMUFile *f, void *opaque) } qemu_put_be32(f, env->cp15.c0_cpuid); qemu_put_be32(f, env->cp15.c0_cachetype); + qemu_put_be32(f, env->cp15.c0_cssel); qemu_put_be32(f, env->cp15.c1_sys); qemu_put_be32(f, env->cp15.c1_coproc); qemu_put_be32(f, env->cp15.c1_xscaleauxcr); qemu_put_be32(f, env->cp15.c2_base0); qemu_put_be32(f, env->cp15.c2_base1); + qemu_put_be32(f, env->cp15.c2_control); qemu_put_be32(f, env->cp15.c2_mask); + qemu_put_be32(f, env->cp15.c2_base_mask); qemu_put_be32(f, env->cp15.c2_data); qemu_put_be32(f, env->cp15.c2_insn); qemu_put_be32(f, env->cp15.c3); @@ -91,12 +94,18 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be32(f, env->v7m.current_sp); qemu_put_be32(f, env->v7m.exception); } + + if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + qemu_put_be32(f, env->teecr); + qemu_put_be32(f, env->teehbr); + } } int cpu_load(QEMUFile *f, void *opaque, int version_id) { CPUARMState *env = (CPUARMState *)opaque; int i; + uint32_t val; if (version_id != CPU_SAVE_VERSION) return -EINVAL; @@ -104,7 +113,10 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) for (i = 0; i < 16; i++) { env->regs[i] = qemu_get_be32(f); } - cpsr_write(env, qemu_get_be32(f), 0xffffffff); + val = qemu_get_be32(f); + /* Avoid mode switch when restoring CPSR. */ + env->uncached_cpsr = val & CPSR_M; + cpsr_write(env, val, 0xffffffff); env->spsr = qemu_get_be32(f); for (i = 0; i < 6; i++) { env->banked_spsr[i] = qemu_get_be32(f); @@ -117,12 +129,15 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) } env->cp15.c0_cpuid = qemu_get_be32(f); env->cp15.c0_cachetype = qemu_get_be32(f); + env->cp15.c0_cssel = qemu_get_be32(f); env->cp15.c1_sys = qemu_get_be32(f); env->cp15.c1_coproc = qemu_get_be32(f); env->cp15.c1_xscaleauxcr = qemu_get_be32(f); env->cp15.c2_base0 = qemu_get_be32(f); env->cp15.c2_base1 = qemu_get_be32(f); + env->cp15.c2_control = qemu_get_be32(f); env->cp15.c2_mask = qemu_get_be32(f); + env->cp15.c2_base_mask = qemu_get_be32(f); env->cp15.c2_data = qemu_get_be32(f); env->cp15.c2_insn = qemu_get_be32(f); env->cp15.c3 = qemu_get_be32(f); @@ -187,5 +202,10 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) env->v7m.exception = qemu_get_be32(f); } + if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + env->teecr = qemu_get_be32(f); + env->teehbr = qemu_get_be32(f); + } + return 0; } |