diff options
| -rw-r--r-- | target-arm/helper.c | 8 | ||||
| -rw-r--r-- | target-arm/translate.c | 7 |
2 files changed, 12 insertions, 3 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 8132d0caf4..f1b170d030 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -838,9 +838,11 @@ void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val) case 15: /* Implementation specific. */ if (arm_feature(env, ARM_FEATURE_XSCALE)) { if (op2 == 0 && crm == 1) { - /* Changes cp0 to cp13 behavior, so needs a TB flush. */ - tb_flush(env); - env->cp15.c15_cpar = (val & 0x3fff) | 2; + if (env->cp15.c15_cpar != (val & 0x3fff)) { + /* Changes cp0 to cp13 behavior, so needs a TB flush. */ + tb_flush(env); + env->cp15.c15_cpar = val & 0x3fff; + } break; } goto bad_reg; diff --git a/target-arm/translate.c b/target-arm/translate.c index 3ce93f89b1..799aef2f15 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2230,6 +2230,13 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) gen_op_movl_T0_im(val); gen_bx(s); return; + } else if ((insn & 0x0e000f00) == 0x0c000100) { + if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + /* iWMMXt register transfer. */ + if (env->cp15.c15_cpar & (1 << 1)) + if (!disas_iwmmxt_insn(env, s, insn)) + return; + } } else if ((insn & 0x0fe00000) == 0x0c400000) { /* Coprocessor double register transfer. */ } else if ((insn & 0x0f000010) == 0x0e000010) { |