New model for PowerPC CPU hardware interrupt events:

move all PowerPC specific code into target-ppc/helper.c to avoid polluting
the common code in cpu-exec.c. This makes implementation of new features
(ie embedded PowerPC timers, critical interrupts, ...) easier.
This also avoid hardcoding the IRQ callback in the OpenPIC controller,
making it more easily reusable and allowing cascading.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2542 c046a42c-6fe2-441c-8c8c-71466251a162

1 files changed, 13 insertions, 2 deletions

diff --git a/vl.h b/vl.h
index 61b5b80f75..2bcf81ada2 100644
--- a/vl.h
+++ b/vl.h
@@ -852,9 +852,16 @@ int piix4_init(PCIBus *bus, int devfn);
 
 /* openpic.c */
 typedef struct openpic_t openpic_t;
+enum {
+    OPENPIC_EVT_INT = 0, /* IRQ                       */
+    OPENPIC_EVT_CINT,    /* critical IRQ              */
+    OPENPIC_EVT_MCK,     /* Machine check event       */
+    OPENPIC_EVT_DEBUG,   /* Inconditional debug event */
+    OPENPIC_EVT_RESET,   /* Core reset event          */
+};
 void openpic_set_irq(void *opaque, int n_IRQ, int level);
-openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
-                         CPUState **envp);
+openpic_t *openpic_init (PCIBus *bus, SetIRQFunc *set_irq,
+                         int *pmem_index, int nb_cpus, CPUPPCState **envp);
 
 /* heathrow_pic.c */
 typedef struct HeathrowPICS HeathrowPICS;
@@ -1115,6 +1122,10 @@ extern void cpu_mips_irqctrl_init (void);
 extern QEMUMachine shix_machine;
 
 #ifdef TARGET_PPC
+/* PowerPC hardware exceptions management helpers */
+void ppc_set_irq (void *opaque, int n_IRQ, int level);
+void ppc_openpic_irq (void *opaque, int n_IRQ, int level);
+int ppc_hw_interrupt (CPUState *env);
 ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);
 #endif
 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);