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| author | Francisco Iglesias <frasse.iglesias@gmail.com> | 2017-12-13 17:59:21 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-12-13 17:59:21 +0000 |
| commit | c3725b8549dba4b47d17672654ca5a19a8281dfb (patch) | |
| tree | e373fa1074efbbc1d608ad3cdc5852941d5c05ef /util/uri.c | |
| parent | 5394dbcca8839bfb87bc65594170ba80f45054ec (diff) | |
xilinx_spips: Update striping to be big-endian bit order
Update striping functionality to be big-endian bit order (as according to
the Zynq-7000 Technical Reference Manual). Output thereafter the even bits
into the flash memory connected to the lower QSPI bus and the odd bits into
the flash memory connected to the upper QSPI bus.
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20171126231634.9531-7-frasse.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'util/uri.c')
0 files changed, 0 insertions, 0 deletions