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authorPeter Maydell <peter.maydell@linaro.org>2016-03-16 17:43:37 +0000
committerPeter Maydell <peter.maydell@linaro.org>2016-03-16 17:43:37 +0000
commitd1f8764099022bc1173f2413331b26d4ff609a0c (patch)
tree5dd25667e072bf580983ac1d0ad54a31b0b083f9 /ui
parent0ebc03bc065329eaefb6493f5fa7df08df528f2a (diff)
parentfec44a8c70e23f0f8433a28e824ce6dae4de8cde (diff)
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160316-1' into staging
target-arm queue: * loader: Fix incorrect parameter name in load_image_mr() * Implement MRS (banked) and MSR (banked) instructions * virt: Implement versioning for machine model * i.MX: some initial patches preparing for i.MX6 support * new ASPEED AST2400 SoC and palmetto-bmc machine * bcm2835: add some more raspi2 devices * sd: fix segfault running "info qtree" # gpg: Signature made Wed 16 Mar 2016 17:42:43 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20160316-1: (21 commits) sd: Fix "info qtree" on boards with SD cards bcm2835_dma: add emulation of Raspberry Pi DMA controller bcm2835_property: implement framebuffer control/configuration properties bcm2835_fb: add framebuffer device for Raspberry Pi bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) block bcm2835_peripherals: enable sdhci pending-insert quirk for raspberry pi hw/arm: Add palmetto-bmc machine hw/arm: Add ASPEED AST2400 SoC model hw/intc: Add (new) ASPEED VIC device model hw/timer: Add ASPEED timer device model i.MX: Add missing descriptions in devices. i.MX: Add i.MX6 CCM and ANALOG device. i.MX: Add the CLK_IPG_HIGH clock i.MX: Remove CCM useless clock computation handling. i.MX: Rename CCM NOCLK to CLK_NONE for naming consistency. i.MX: Allow GPT timer to rollover. arm: virt: Move machine class init code to the abstract machine type arm: virt: Add an abstract ARM virt machine type target-arm: Fix translation level on early translation faults target-arm: Implement MRS (banked) and MSR (banked) instructions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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