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authorMichael Clark <mjc@sifive.com>2019-03-16 01:20:20 +0000
committerPalmer Dabbelt <palmer@sifive.com>2019-03-19 05:14:39 -0700
commite3e7039cc24ecf47d81c091e8bb04552d6564ad8 (patch)
tree8246d143e414740cba7f9f84d53a137b7a2a947b /ui/vnc-auth-vencrypt.h
parent244df421333970e66bc48e48e7fb45fcb1017ea0 (diff)
RISC-V: Allow interrupt controllers to claim interrupts
We can't allow the supervisor to control SEIP as this would allow the supervisor to clear a pending external interrupt which will result in lost a interrupt in the case a PLIC is attached. The SEIP bit must be hardware controlled when a PLIC is attached. This logic was previously hard-coded so SEIP was always masked even if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts so that the PLIC can register control of SEIP. In the case of models without a PLIC (spike), the SEIP bit remains software controlled. This interface allows for hardware control of supervisor timer and software interrupts by other interrupt controller models. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'ui/vnc-auth-vencrypt.h')
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