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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-21 13:47:20 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-06-21 13:47:20 -0700 |
| commit | f200ff158d5abcb974a6b597a962b6b2fbea2b06 (patch) | |
| tree | 0bad1924d9b2c6ccb7c816a530fe7d5ee76c97b0 /ui/dbus-clipboard.c | |
| parent | 5cdcfd861e3cdb98d3239ba78c97a1a2b13d2a70 (diff) | |
| parent | c79a8e840c435bc26a251e34b043318e8b2081db (diff) | |
Merge tag 'pull-tcg-20220621' of https://gitlab.com/rth7680/qemu into staging
Speed empty timer list in qemu_clock_deadline_ns_all.
Implement remainder for Power3.1 hosts.
Optimize ppc host icache flushing.
Cleanups to tcg_accel_ops_init.
Fix mmio crash accessing unmapped physical memory.
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# gpg: Signature made Tue 21 Jun 2022 01:45:31 PM PDT
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* tag 'pull-tcg-20220621' of https://gitlab.com/rth7680/qemu:
util/cacheflush: Optimize flushing when ppc host has coherent icache
util/cacheflush: Merge aarch64 ctr_el0 usage
util: Merge cacheflush.c and cacheinfo.c
softmmu: Always initialize xlat in address_space_translate_for_iotlb
qemu-timer: Skip empty timer lists before locking in qemu_clock_deadline_ns_all
accel/tcg: Reorganize tcg_accel_ops_init()
accel/tcg: Init TCG cflags in vCPU thread handler
target/avr: Drop avr_cpu_memory_rw_debug()
tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'ui/dbus-clipboard.c')
0 files changed, 0 insertions, 0 deletions