diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2016-06-17 15:23:47 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-06-17 15:23:51 +0100 |
| commit | f7b9358e2cf12a5eb07f5f9301fdadc932f9ee03 (patch) | |
| tree | 42c5a2e58e616f9e0ccbf12ea85770162eb38f28 /trace-events | |
| parent | 359fbe65e01e13f582d3b9103e7c3ec5ac367a18 (diff) | |
hw/intc/arm_gicv3: Implement gicv3_cpuif_update()
Implement the gicv3_cpuif_update() function which deals with correctly
asserting IRQ and FIQ based on the current running priority of the CPU,
the priority of the highest priority pending interrupt and the CPU's
current exception level and security state.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 1465915112-29272-17-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'trace-events')
| -rw-r--r-- | trace-events | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/trace-events b/trace-events index c6efebdc29..6aec711ce7 100644 --- a/trace-events +++ b/trace-events @@ -2181,6 +2181,8 @@ gicv3_icc_ctlr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR read cpu %x valu gicv3_icc_ctlr_write(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR write cpu %x value 0x%" PRIx64 gicv3_icc_ctlr_el3_read(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR_EL3 read cpu %x value 0x%" PRIx64 gicv3_icc_ctlr_el3_write(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR_EL3 write cpu %x value 0x%" PRIx64 +gicv3_cpuif_update(uint32_t cpuid, int irq, int grp, int prio) "GICv3 CPU i/f %x HPPI update: irq %d group %d prio %d" +gicv3_cpuif_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CPU i/f %x HPPI update: setting FIQ %d IRQ %d" # hw/intc/arm_gicv3_dist.c gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" |