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authorMichael Walle <michael@walle.cc>2011-02-17 23:45:07 +0100
committerEdgar E. Iglesias <edgar.iglesias@gmail.com>2011-03-07 13:42:36 +0100
commit4ef66fa71882a8f8682d9a8d1528e1ec98c264e5 (patch)
tree853c28ded1d1d394dceb86920823c180ef99a57d /trace-events
parent0c45d3d4b921e9639a2ce400a6afdb4d962a5805 (diff)
lm32: interrupt controller model
This patch adds the interrupt controller of the lm32. Because the PIC is accessed through special control registers and opcodes, there are callbacks from the lm32 translation code to this model. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'trace-events')
-rw-r--r--trace-events9
1 files changed, 9 insertions, 0 deletions
diff --git a/trace-events b/trace-events
index e6138ea460..557375e4e6 100644
--- a/trace-events
+++ b/trace-events
@@ -254,3 +254,12 @@ disable spice_vmc_write(ssize_t out, int len) "spice wrottn %lu of requested %zd
disable spice_vmc_read(int bytes, int len) "spice read %lu of requested %zd"
disable spice_vmc_register_interface(void *scd) "spice vmc registered interface %p"
disable spice_vmc_unregister_interface(void *scd) "spice vmc unregistered interface %p"
+
+# hw/lm32_pic.c
+disable lm32_pic_raise_irq(void) "Raise CPU interrupt"
+disable lm32_pic_lower_irq(void) "Lower CPU interrupt"
+disable lm32_pic_interrupt(int irq, int level) "Set IRQ%d %d"
+disable lm32_pic_set_im(uint32_t im) "im 0x%08x"
+disable lm32_pic_set_ip(uint32_t ip) "ip 0x%08x"
+disable lm32_pic_get_im(uint32_t im) "im 0x%08x"
+disable lm32_pic_get_ip(uint32_t ip) "ip 0x%08x"