diff options
| author | Greg Bellows <greg.bellows@linaro.org> | 2014-12-11 12:07:48 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-12-11 12:07:48 +0000 |
| commit | 57e3a0c7cb0ac2f0288890482e0a463adce2080a (patch) | |
| tree | e536bbaa493da093353b15358d14b73d305dfda1 /thread-pool.c | |
| parent | a38bb0792ca8b4082d81884a6cb25fa0d334b4a6 (diff) | |
target-arm: extend async excp masking
This patch extends arm_excp_unmasked() to use lookup tables for determining
whether IRQ and FIQ exceptions are masked. The lookup tables are based on the
ARMv8 and ARMv7 specification physical interrupt masking tables.
If EL3 is using AArch64 IRQ/FIQ masking is ignored in all exception levels
other than EL3 if SCR.{FIQ|IRQ} is set to 1 (routed to EL3).
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-2-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'thread-pool.c')
0 files changed, 0 insertions, 0 deletions