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author | Peter Maydell <peter.maydell@linaro.org> | 2020-03-20 12:15:19 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2020-03-20 12:15:20 +0000 |
commit | 226cd20706e20264c176f8edbaf17d7c9b7ade4a (patch) | |
tree | ffe530825118c0e137fcc2b04496d62096e42ca9 /tests | |
parent | f3949284da77529c68da8be71f182bac1bcc7c3e (diff) | |
parent | c8c35e5f51c4d54bced7aa05fbd8e2371e493182 (diff) |
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/target_renesas_rx-20200320' into staging
Introduce the architectural part of the Renesas RX
architecture emulation, developed by Yoshinori Sato.
CI jobs results:
https://gitlab.com/philmd/qemu/pipelines/127886344
https://travis-ci.org/github/philmd/qemu/builds/664579420
# gpg: Signature made Fri 20 Mar 2020 10:27:32 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/target_renesas_rx-20200320:
Add rx-softmmu
target/rx: Dump bytes for each insn during disassembly
target/rx: Collect all bytes during disassembly
target/rx: Emit all disassembly in one prt()
target/rx: Use prt_ldmi for XCHG_mr disassembly
target/rx: Replace operand with prt_ldmi in disassembler
target/rx: Disassemble rx_index_addr into a string
target/rx: RX disassembler
target/rx: CPU definitions
target/rx: TCG helpers
target/rx: TCG translation
MAINTAINERS: Add entry for the Renesas RX architecture
hw/registerfields.h: Add 8bit and 16bit register macros
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests')
-rw-r--r-- | tests/qtest/machine-none-test.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c index 5953d31755..8bb54a6360 100644 --- a/tests/qtest/machine-none-test.c +++ b/tests/qtest/machine-none-test.c @@ -56,6 +56,7 @@ static struct arch2cpu cpus_map[] = { { "hppa", "hppa" }, { "riscv64", "rv64gcsu-v1.10.0" }, { "riscv32", "rv32gcsu-v1.9.1" }, + { "rx", "rx62n" }, }; static const char *get_cpu_model_by_arch(const char *arch) |