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authorPeter Maydell <peter.maydell@linaro.org>2018-08-15 12:00:53 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-08-15 12:00:53 +0100
commit48a539df4a25b009c5a1239039349d54185fc0df (patch)
tree12e4a30c7e80a9c496474ade2c348ebb17142dc0 /tests
parentc7fb81a53cacbdac7430d7c4b326f8ad04a3461f (diff)
parent054e7adf4e64e4acb3b033348ebf7cc871baa34f (diff)
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180814' into staging
target-arm queue: * Implement more of ARMv6-M support * Support direct execution from non-RAM regions; use this to implmeent execution from small (<1K) MPU regions * GICv2: implement the virtualization extensions * support a virtualization-capable GICv2 in the virt and xlnx-zynqmp boards * arm: Fix return code of arm_load_elf() so we can detect failure to load the file correctly * Implement HCR_EL2.TGE ("trap general exceptions") bit * Implement tailchaining for M profile cores * Fix bugs in SVE compare, saturating add/sub, WHILE, MOVZ # gpg: Signature made Tue 14 Aug 2018 17:23:38 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180814: (45 commits) target/arm: Fix typo in helper_sve_movz_d target/arm: Reorganize SVE WHILE target/arm: Fix typo in do_sat_addsub_64 target/arm: Fix sign of sve_cmpeq_ppzw/sve_cmpne_ppzw target/arm: Implement tailchaining for M profile cores target/arm: Restore M-profile CONTROL.SPSEL before any tailchaining target/arm: Initialize exc_secure correctly in do_v7m_exception_exit() target/arm: Improve exception-taken logging target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO} target/arm: Honour HCR_EL2.TGE when raising synchronous exceptions target/arm: Honour HCR_EL2.TGE and MDCR_EL2.TDE in debug register access checks target/arm: Mask virtual interrupts if HCR_EL2.TGE is set arm: Fix return code of arm_load_elf arm/virt: Add support for GICv2 virtualization extensions xlnx-zynqmp: Improve GIC wiring and MMIO mapping intc/arm_gic: Improve traces intc/arm_gic: Implement maintenance interrupt generation intc/arm_gic: Implement gic_update_virt() function intc/arm_gic: Implement the virtual interface registers ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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