diff options
| author | Alex Bennée <alex.bennee@linaro.org> | 2023-01-24 18:01:17 +0000 |
|---|---|---|
| committer | Alex Bennée <alex.bennee@linaro.org> | 2023-02-02 11:48:20 +0000 |
| commit | d54c6d3b5ddc0555f8d3bb6b0ba59da1f59b18f7 (patch) | |
| tree | 201edc2e85716e172b74166931e8ab4790854b4f /tests/tcg | |
| parent | 0bccdb42df66b697e0a4681c2ad4f10eccef5330 (diff) | |
tests/tcg: add memory-sve test for aarch64
This will be helpful in debugging problems with tracking SVE memory
accesses via the TCG plugins system.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Robert Henry <robhenry@microsoft.com>
Cc: Aaron Lindsay <aaron@os.amperecomputing.com>
Message-Id: <20230124180127.1881110-26-alex.bennee@linaro.org>
Diffstat (limited to 'tests/tcg')
| -rw-r--r-- | tests/tcg/aarch64/Makefile.softmmu-target | 7 | ||||
| -rw-r--r-- | tests/tcg/aarch64/system/boot.S | 3 |
2 files changed, 9 insertions, 1 deletions
diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target index a1368905f5..df9747bae8 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -36,6 +36,13 @@ config-cc.mak: Makefile memory: CFLAGS+=-DCHECK_UNALIGNED=1 +memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) + +memory-sve: CFLAGS+=-DCHECK_UNALIGNED=1 -march=armv8.1-a+sve -O3 -fno-tree-loop-distribute-patterns + +TESTS+=memory-sve + # Running QEMU_BASE_MACHINE=-M virt -cpu max -display none QEMU_OPTS+=$(QEMU_BASE_MACHINE) -semihosting-config enable=on,target=native,chardev=output -kernel diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boot.S index e190b1efa6..f136363d2a 100644 --- a/tests/tcg/aarch64/system/boot.S +++ b/tests/tcg/aarch64/system/boot.S @@ -179,12 +179,13 @@ __start: isb /* - * Enable FP registers. The standard C pre-amble will be + * Enable FP/SVE registers. The standard C pre-amble will be * saving these and A-profile compilers will use AdvSIMD * registers unless we tell it not to. */ mrs x0, cpacr_el1 orr x0, x0, #(3 << 20) + orr x0, x0, #(3 << 16) msr cpacr_el1, x0 /* Setup some stack space and enter the test code. |