diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2019-09-30 11:02:22 +0100 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2019-09-30 11:02:22 +0100 |
commit | 786d36ad416c6c199b18b78cc31eddfb784fe15d (patch) | |
tree | 5df78ee8c2a61247a609bfd25e0b3fcdaf2aa48e /tests/tcg | |
parent | 1e396381939bb7e4e799d9bf2a2af693954b5613 (diff) | |
parent | e4e34855e658b78ecac50a651cc847662ff02cfd (diff) |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190927' into staging
target-arm queue:
* Fix the CBAR register implementation for Cortex-A53,
Cortex-A57, Cortex-A72
* Fix direct booting of Linux kernels on emulated CPUs
which have an AArch32 EL3 (incorrect NSACR settings
meant they could not access the FPU)
* semihosting cleanup: do more work at translate time
and less work at runtime
# gpg: Signature made Fri 27 Sep 2019 15:32:43 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20190927:
hw/arm/boot: Use the IEC binary prefix definitions
hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots
tests/tcg: add linux-user semihosting smoke test for ARM
target/arm: remove run-time semihosting checks for linux-user
target/arm: remove run time semihosting checks
target/arm: handle A-profile semihosting at translate time
target/arm: handle M-profile semihosting at translate time
tests/tcg: clean-up some comments after the de-tangling
target/arm: fix CBAR register for AArch64 CPUs
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts:
# tests/tcg/arm/Makefile.target
Diffstat (limited to 'tests/tcg')
-rw-r--r-- | tests/tcg/aarch64/Makefile.target | 5 | ||||
-rw-r--r-- | tests/tcg/arm/Makefile.target | 6 | ||||
-rw-r--r-- | tests/tcg/arm/semihosting.c | 45 |
3 files changed, 55 insertions, 1 deletions
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 9758f89f90..509f1afa93 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -21,4 +21,9 @@ run-fcvt: fcvt AARCH64_TESTS += pauth-1 pauth-2 run-pauth-%: QEMU_OPTS += -cpu max +# Semihosting smoke test for linux-user +AARCH64_TESTS += semihosting +run-semihosting: semihosting + $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)") + TESTS += $(AARCH64_TESTS) diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index 9f43d98f35..3ddff85240 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -8,7 +8,6 @@ ARM_SRC=$(SRC_PATH)/tests/tcg/arm # Set search path for all sources VPATH += $(ARM_SRC) -# Multiarch Tests float_madds: CFLAGS+=-mfpu=neon-vfpv4 # Basic Hello World @@ -30,6 +29,11 @@ run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) +# Semihosting smoke test for linux-user +ARM_TESTS += semihosting +run-semihosting: semihosting + $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)") + TESTS += $(ARM_TESTS) # On ARM Linux only supports 4k pages diff --git a/tests/tcg/arm/semihosting.c b/tests/tcg/arm/semihosting.c new file mode 100644 index 0000000000..09c89cb481 --- /dev/null +++ b/tests/tcg/arm/semihosting.c @@ -0,0 +1,45 @@ +/* + * linux-user semihosting checks + * + * Copyright (c) 2019 + * Written by Alex Bennée <alex.bennee@linaro.org> + * + * SPDX-License-Identifier: GPL-3.0-or-later + */ + +#include <stdint.h> + +#define SYS_WRITE0 0x04 +#define SYS_REPORTEXC 0x18 + +void __semi_call(uintptr_t type, uintptr_t arg0) +{ +#if defined(__arm__) + register uintptr_t t asm("r0") = type; + register uintptr_t a0 asm("r1") = arg0; + asm("svc 0xab" + : /* no return */ + : "r" (t), "r" (a0)); +#else + register uintptr_t t asm("x0") = type; + register uintptr_t a0 asm("x1") = arg0; + asm("hlt 0xf000" + : /* no return */ + : "r" (t), "r" (a0)); +#endif +} + +int main(int argc, char *argv[argc]) +{ +#if defined(__arm__) + uintptr_t exit_code = 0x20026; +#else + uintptr_t exit_block[2] = {0x20026, 0}; + uintptr_t exit_code = (uintptr_t) &exit_block; +#endif + + __semi_call(SYS_WRITE0, (uintptr_t) "Hello World"); + __semi_call(SYS_REPORTEXC, exit_code); + /* if we get here we failed */ + return -1; +} |