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authorMax Filippov <jcmvbkbc@gmail.com>2017-01-14 19:58:55 -0800
committerMax Filippov <jcmvbkbc@gmail.com>2017-01-15 13:01:56 -0800
commit4f89b41c28a17739c4fd40886542e3cb8c7a15a3 (patch)
treedbeb7b9a21d8ed427273a2fbdb392137a5afe81a /tests/tcg
parent72b3b8f24a4ada7f6e97fe5cd83e04f94b1f25e0 (diff)
target/xtensa: tests: replace hardcoded interrupt masks
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'tests/tcg')
-rw-r--r--tests/tcg/xtensa/test_timer.S10
1 files changed, 5 insertions, 5 deletions
diff --git a/tests/tcg/xtensa/test_timer.S b/tests/tcg/xtensa/test_timer.S
index 9e6012d7fd..844c0327aa 100644
--- a/tests/tcg/xtensa/test_timer.S
+++ b/tests/tcg/xtensa/test_timer.S
@@ -59,7 +59,7 @@ test ccompare0_interrupt
rsr a2, interrupt
assert eqi, a2, 0
- movi a2, 0x40
+ movi a2, 1 << XCHAL_TIMER0_INTERRUPT
wsr a2, intenable
rsil a2, 0
loop a3, 1f
@@ -87,7 +87,7 @@ test ccompare1_interrupt
rsync
rsr a2, interrupt
assert eqi, a2, 0
- movi a2, 0x400
+ movi a2, 1 << XCHAL_TIMER1_INTERRUPT
wsr a2, intenable
rsil a2, 2
loop a3, 1f
@@ -113,7 +113,7 @@ test ccompare2_interrupt
rsync
rsr a2, interrupt
assert eqi, a2, 0
- movi a2, 0x2000
+ movi a2, 1 << XCHAL_TIMER2_INTERRUPT
wsr a2, intenable
rsil a2, 4
loop a3, 1f
@@ -141,7 +141,7 @@ test ccompare_interrupt_masked
rsr a2, interrupt
assert eqi, a2, 0
- movi a2, 0x40
+ movi a2, 1 << XCHAL_TIMER0_INTERRUPT
wsr a2, intenable
rsil a2, 0
loop a3, 1f
@@ -171,7 +171,7 @@ test ccompare_interrupt_masked_waiti
rsr a2, interrupt
assert eqi, a2, 0
- movi a2, 0x40
+ movi a2, 1 << XCHAL_TIMER0_INTERRUPT
wsr a2, intenable
waiti 0
test_fail