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authorMax Filippov <jcmvbkbc@gmail.com>2012-03-08 03:00:31 +0400
committerMax Filippov <jcmvbkbc@gmail.com>2019-02-28 04:43:23 -0800
commit5e33b037b5153936c503b17f3e6b40fa34265268 (patch)
tree7eee301da657829e660d73ea0fe53f93f5bf4df1 /tests/tcg/xtensa
parentebbd775aab3a15b3d631e6a262353ece4575fcf5 (diff)
tests/tcg/xtensa: add LSCI/LSCX group tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'tests/tcg/xtensa')
-rw-r--r--tests/tcg/xtensa/Makefile1
-rw-r--r--tests/tcg/xtensa/test_lsc.S122
2 files changed, 123 insertions, 0 deletions
diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile
index bd94ba6fe5..c2bc278be5 100644
--- a/tests/tcg/xtensa/Makefile
+++ b/tests/tcg/xtensa/Makefile
@@ -41,6 +41,7 @@ TESTCASES += test_fail.tst
TESTCASES += test_flix.tst
TESTCASES += test_interrupt.tst
TESTCASES += test_loop.tst
+TESTCASES += test_lsc.tst
TESTCASES += test_mac16.tst
TESTCASES += test_max.tst
TESTCASES += test_min.tst
diff --git a/tests/tcg/xtensa/test_lsc.S b/tests/tcg/xtensa/test_lsc.S
new file mode 100644
index 0000000000..0578bf19e7
--- /dev/null
+++ b/tests/tcg/xtensa/test_lsc.S
@@ -0,0 +1,122 @@
+#include "macros.inc"
+
+test_suite lsc
+
+#if XCHAL_HAVE_FP
+
+test lsi
+ movi a2, 1
+ wsr a2, cpenable
+
+ movi a2, 1f
+ lsi f0, a2, 0
+ lsi f1, a2, 4
+ lsiu f2, a2, 8
+ movi a3, 1f + 8
+ assert eq, a2, a3
+ rfr a2, f0
+ movi a3, 0x3f800000
+ assert eq, a2, a3
+ rfr a2, f1
+ movi a3, 0x40000000
+ assert eq, a2, a3
+ rfr a2, f2
+ movi a3, 0x40400000
+ assert eq, a2, a3
+.data
+ .align 4
+1:
+.float 1, 2, 3
+.text
+test_end
+
+test ssi
+ movi a2, 1f
+ movi a3, 0x40800000
+ wfr f3, a3
+ ssi f3, a2, 0
+ movi a3, 0x40a00000
+ wfr f4, a3
+ ssi f4, a2, 4
+ movi a3, 0x40c00000
+ wfr f5, a3
+ ssiu f5, a2, 8
+ movi a3, 1f + 8
+ assert eq, a2, a3
+ l32i a4, a2, -8
+ movi a3, 0x40800000
+ assert eq, a4, a3
+ l32i a4, a2, -4
+ movi a3, 0x40a00000
+ assert eq, a4, a3
+ l32i a4, a2, 0
+ movi a3, 0x40c00000
+ assert eq, a4, a3
+.data
+ .align 4
+1:
+.float 0, 0, 0
+.text
+test_end
+
+test lsx
+ movi a2, 1f
+ movi a3, 0
+ lsx f6, a2, a3
+ movi a3, 4
+ lsx f7, a2, a3
+ movi a3, 8
+ lsxu f8, a2, a3
+ movi a3, 1f + 8
+ assert eq, a2, a3
+ rfr a2, f6
+ movi a3, 0x40e00000
+ assert eq, a2, a3
+ rfr a2, f7
+ movi a3, 0x41000000
+ assert eq, a2, a3
+ rfr a2, f8
+ movi a3, 0x41100000
+ assert eq, a2, a3
+.data
+ .align 4
+1:
+.float 7, 8, 9
+.text
+test_end
+
+test ssx
+ movi a2, 1f
+ movi a3, 0
+ movi a4, 0x41200000
+ wfr f9, a4
+ ssx f9, a2, a3
+ movi a3, 4
+ movi a4, 0x41300000
+ wfr f10, a4
+ ssx f10, a2, a3
+ movi a3, 8
+ movi a4, 0x41400000
+ wfr f11, a4
+ ssxu f11, a2, a3
+ movi a3, 1f + 8
+ assert eq, a2, a3
+ l32i a4, a2, -8
+ movi a3, 0x41200000
+ assert eq, a4, a3
+ l32i a4, a2, -4
+ movi a3, 0x41300000
+ assert eq, a4, a3
+ l32i a4, a2, 0
+ movi a3, 0x41400000
+ assert eq, a4, a3
+.data
+ .align 4
+1:
+.float 0, 0, 0
+.text
+test_end
+
+#endif
+
+test_suite_end