Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into staging

ppc 7.0 queue:

* Cleanup of PowerNV PHBs (Daniel and Cedric)
* Cleanup and fixes for PPC405 machine (Cedric)
* Fix for xscvspdpn (Matheus)
* Rework of powerpc exception handling 1/n (Fabiano)
* Optimisation for PMU (Richard and Daniel)

# gpg: Signature made Mon 03 Jan 2022 11:04:06 PM PST
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-ppc-20220104' of https://github.com/legoater/qemu: (26 commits)
  target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0()
  target/ppc: Use env->pnc_cyc_cnt
  target/ppc: Rewrite pmu_increment_insns
  target/ppc: Cache per-pmc insn and cycle count settings
  target/ppc: powerpc_excp: Stop passing excp_model around
  target/ppc: powerpc_excp: Move system call vectored code together
  target/ppc: powerpc_excp: Set vector earlier
  target/ppc: powerpc_excp: Add excp_vectors bounds check
  target/ppc: powerpc_excp: Set alternate SRRs directly
  target/ppc: do not silence snan in xscvspdpn
  ppc/ppc405: Dump specific registers
  ppc/ppc405: Introduce a store helper for SPR_40x_PID
  ppc/ppc405: Fix timer initialization
  ppc/ppc405: Rework ppc_40x_timers_init() to use a PowerPCCPU
  ppc/ppc405: Restore TCR and STR write handlers
  ppc/ppc405: Activate MMU logs
  ppc/ppc4xx: Convert printfs()
  target/ppc: Print out literal exception names in logs
  target/ppc: Remove static inline
  target/ppc: Check effective address validity
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

1 files changed, 37 insertions, 0 deletions

diff --git a/tests/tcg/ppc64le/non_signalling_xscv.c b/tests/tcg/ppc64le/non_signalling_xscv.c
new file mode 100644
index 0000000000..91e25cad46
--- /dev/null
+++ b/tests/tcg/ppc64le/non_signalling_xscv.c
@@ -0,0 +1,37 @@
+#include <stdio.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <assert.h>
+
+#define TEST(INSN, B_HI, B_LO, T_HI, T_LO) \
+    do {                                                                \
+        uint64_t th, tl, bh = B_HI, bl = B_LO;                          \
+        asm("mtvsrd 0, %2\n\t"                                          \
+            "mtvsrd 1, %3\n\t"                                          \
+            "xxmrghd 0, 0, 1\n\t"                                       \
+            INSN " 0, 0\n\t"                                            \
+            "mfvsrd %0, 0\n\t"                                          \
+            "xxswapd 0, 0\n\t"                                          \
+            "mfvsrd %1, 0\n\t"                                          \
+            : "=r" (th), "=r" (tl)                                      \
+            : "r" (bh), "r" (bl)                                        \
+            : "vs0", "vs1");                                            \
+        printf(INSN "(0x%016" PRIx64 "%016" PRIx64 ") = 0x%016" PRIx64  \
+               "%016" PRIx64 "\n", bh, bl, th, tl);                     \
+        assert(th == T_HI && tl == T_LO);                               \
+    } while (0)
+
+int main(void)
+{
+    /* SNaN shouldn't be silenced */
+    TEST("xscvspdpn", 0x7fbfffff00000000ULL, 0x0, 0x7ff7ffffe0000000ULL, 0x0);
+    TEST("xscvdpspn", 0x7ff7ffffffffffffULL, 0x0, 0x7fbfffff7fbfffffULL, 0x0);
+
+    /*
+     * SNaN inputs having no significant bits in the upper 23 bits of the
+     * signifcand will return Infinity as the result.
+     */
+    TEST("xscvdpspn", 0x7ff000001fffffffULL, 0x0, 0x7f8000007f800000ULL, 0x0);
+
+    return 0;
+}