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authorJia Liu <proljc@gmail.com>2012-10-24 22:17:13 +0800
committerAurelien Jarno <aurelien@aurel32.net>2012-10-31 21:37:21 +0100
commitd70080c4e37fc533fa10904b286f29449decc6f8 (patch)
treee36bed089aa0fd67cb9c17bbff0a0f4aaa148f3f /tests/tcg/mips/mips64-dsp/cmpu_le_qb.c
parentaf13ae03f8dbc02974d53b11b80b3ae4dd9f30b4 (diff)
target-mips: Add ASE DSP testcases
Add MIPS ASE DSP testcases. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tests/tcg/mips/mips64-dsp/cmpu_le_qb.c')
-rw-r--r--tests/tcg/mips/mips64-dsp/cmpu_le_qb.c41
1 files changed, 41 insertions, 0 deletions
diff --git a/tests/tcg/mips/mips64-dsp/cmpu_le_qb.c b/tests/tcg/mips/mips64-dsp/cmpu_le_qb.c
new file mode 100644
index 0000000000..8a17a08513
--- /dev/null
+++ b/tests/tcg/mips/mips64-dsp/cmpu_le_qb.c
@@ -0,0 +1,41 @@
+#include "io.h"
+
+int main(void)
+{
+ long long rs, rt;
+ long long dsp;
+ long long result;
+
+ rs = 0x11777066;
+ rt = 0x55AA70FF;
+ result = 0x0F;
+ __asm
+ ("cmpu.le.qb %1, %2\n\t"
+ "rddsp %0\n\t"
+ : "=r"(dsp)
+ : "r"(rs), "r"(rt)
+ );
+ dsp = (dsp >> 24) & 0x0F;
+ if (dsp != result) {
+ printf("cmpu.le.qb wrong\n");
+
+ return -1;
+ }
+
+ rs = 0x11777066;
+ rt = 0x11777066;
+ result = 0x0F;
+ __asm
+ ("cmpu.le.qb %1, %2\n\t"
+ "rddsp %0\n\t"
+ : "=r"(dsp)
+ : "r"(rs), "r"(rt)
+ );
+ dsp = (dsp >> 24) & 0x0F;
+ if (dsp != result) {
+ printf("cmpu.le.qb wrong\n");
+
+ return -1;
+ }
+ return 0;
+}