diff options
| author | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-06-26 12:07:04 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-06-26 13:25:28 +0200 |
| commit | c0a19f7bf1f8ecb2bd971353cadae8d3a47eabf5 (patch) | |
| tree | 647c03cf0a59df07faf63165725e8befa83cf645 /tests/tcg/mips/include/wrappers_msa.h | |
| parent | 3d9569b85503ecffc8c5ed999367cb6f072dbf90 (diff) | |
tests/tcg: target/mips: Amend tests for MSA int dot product instructions
Add tests for instructions whose result depends on the value in destination
register (prior to instruction execution).
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-4-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'tests/tcg/mips/include/wrappers_msa.h')
| -rw-r--r-- | tests/tcg/mips/include/wrappers_msa.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/tests/tcg/mips/include/wrappers_msa.h b/tests/tcg/mips/include/wrappers_msa.h index 2692394754..cfb3b8b11f 100644 --- a/tests/tcg/mips/include/wrappers_msa.h +++ b/tests/tcg/mips/include/wrappers_msa.h @@ -413,6 +413,46 @@ DO_MSA__WD__WS_WT(DOTP_U_H, dotp_u.h) DO_MSA__WD__WS_WT(DOTP_U_W, dotp_u.w) DO_MSA__WD__WS_WT(DOTP_U_D, dotp_u.d) +DO_MSA__WD__WS_WT(DPADD_S_H, dpadd_s.h) +DO_MSA__WD__WD_WT(DPADD_S_H__DDT, dpadd_s.h) +DO_MSA__WD__WS_WD(DPADD_S_H__DSD, dpadd_s.h) +DO_MSA__WD__WS_WT(DPADD_S_W, dpadd_s.w) +DO_MSA__WD__WD_WT(DPADD_S_W__DDT, dpadd_s.w) +DO_MSA__WD__WS_WD(DPADD_S_W__DSD, dpadd_s.w) +DO_MSA__WD__WS_WT(DPADD_S_D, dpadd_s.d) +DO_MSA__WD__WD_WT(DPADD_S_D__DDT, dpadd_s.d) +DO_MSA__WD__WS_WD(DPADD_S_D__DSD, dpadd_s.d) + +DO_MSA__WD__WS_WT(DPADD_U_H, dpadd_u.h) +DO_MSA__WD__WD_WT(DPADD_U_H__DDT, dpadd_u.h) +DO_MSA__WD__WS_WD(DPADD_U_H__DSD, dpadd_u.h) +DO_MSA__WD__WS_WT(DPADD_U_W, dpadd_u.w) +DO_MSA__WD__WD_WT(DPADD_U_W__DDT, dpadd_u.w) +DO_MSA__WD__WS_WD(DPADD_U_W__DSD, dpadd_u.w) +DO_MSA__WD__WS_WT(DPADD_U_D, dpadd_u.d) +DO_MSA__WD__WD_WT(DPADD_U_D__DDT, dpadd_u.d) +DO_MSA__WD__WS_WD(DPADD_U_D__DSD, dpadd_u.d) + +DO_MSA__WD__WS_WT(DPSUB_S_H, dpsub_s.h) +DO_MSA__WD__WD_WT(DPSUB_S_H__DDT, dpsub_s.h) +DO_MSA__WD__WS_WD(DPSUB_S_H__DSD, dpsub_s.h) +DO_MSA__WD__WS_WT(DPSUB_S_W, dpsub_s.w) +DO_MSA__WD__WD_WT(DPSUB_S_W__DDT, dpsub_s.w) +DO_MSA__WD__WS_WD(DPSUB_S_W__DSD, dpsub_s.w) +DO_MSA__WD__WS_WT(DPSUB_S_D, dpsub_s.d) +DO_MSA__WD__WD_WT(DPSUB_S_D__DDT, dpsub_s.d) +DO_MSA__WD__WS_WD(DPSUB_S_D__DSD, dpsub_s.d) + +DO_MSA__WD__WS_WT(DPSUB_U_H, dpsub_u.h) +DO_MSA__WD__WD_WT(DPSUB_U_H__DDT, dpsub_u.h) +DO_MSA__WD__WS_WD(DPSUB_U_H__DSD, dpsub_u.h) +DO_MSA__WD__WS_WT(DPSUB_U_W, dpsub_u.w) +DO_MSA__WD__WD_WT(DPSUB_U_W__DDT, dpsub_u.w) +DO_MSA__WD__WS_WD(DPSUB_U_W__DSD, dpsub_u.w) +DO_MSA__WD__WS_WT(DPSUB_U_D, dpsub_u.d) +DO_MSA__WD__WD_WT(DPSUB_U_D__DDT, dpsub_u.d) +DO_MSA__WD__WS_WD(DPSUB_U_D__DSD, dpsub_u.d) + /* * Int Max Min |