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author | Richard Henderson <richard.henderson@linaro.org> | 2023-05-25 11:11:52 -0700 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2023-05-25 11:11:52 -0700 |
commit | a3cb6d5004ff638aefe686ecd540718a793bd1b1 (patch) | |
tree | 02b671fac114b157b5d9fcc75f0a8ce8aadd6789 /tests/tcg/arm | |
parent | 6ad2c71c238183437c91bb9fa0c8d87a9559eca3 (diff) | |
parent | a30498fcea5a8b9c544324ccfb0186090104b229 (diff) |
Merge tag 'pull-tcg-20230525' of https://gitlab.com/rth7680/qemu into staging
tcg/mips:
- Constant formation improvements
- Replace MIPS_BE with HOST_BIG_ENDIAN
- General cleanups
tcg/riscv:
- Improve setcond
- Support movcond
- Support Zbb, Zba
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# gpg: Signature made Thu 25 May 2023 11:07:21 AM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
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# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-20230525' of https://gitlab.com/rth7680/qemu: (23 commits)
tcg/riscv: Support CTZ, CLZ from Zbb
tcg/riscv: Implement movcond
tcg/riscv: Improve setcond expansion
tcg/riscv: Support CPOP from Zbb
tcg/riscv: Support REV8 from Zbb
tcg/riscv: Support rotates from Zbb
tcg/riscv: Use ADD.UW for guest address generation
tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb
tcg/riscv: Support ANDN, ORN, XNOR from Zbb
tcg/riscv: Probe for Zba, Zbb, Zicond extensions
disas/riscv: Decode czero.{eqz,nez}
tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN
tcg/mips: Use qemu_build_not_reached for LO/HI_OFF
tcg/mips: Try three insns with shift and add in tcg_out_movi
tcg/mips: Try tb-relative addresses in tcg_out_movi
tcg/mips: Aggressively use the constant pool for n64 calls
tcg/mips: Use the constant pool for 64-bit constants
tcg/mips: Split out tcg_out_movi_two
tcg/mips: Split out tcg_out_movi_one
tcg/mips: Create and use TCG_REG_TB
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tests/tcg/arm')
0 files changed, 0 insertions, 0 deletions