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authorPeter Maydell <peter.maydell@linaro.org>2019-02-05 18:25:07 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-02-05 18:25:07 +0000
commit47994e16b1d66411953623e7c0bf0cdcd50bd507 (patch)
treeab304a16cd40f9981b29fc3c1e33b975946b2a17 /tests/tcg/aarch64/pauth-1.c
parent9669c9756205290a7a357ff1515a4ca30d852b05 (diff)
parenta15945d98d3a3390c3da344d1b47218e91e49d8b (diff)
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190205' into staging
target-arm queue: * Implement Armv8.5-BTI extension for system emulation mode * Implement the PR_PAC_RESET_KEYS prctl() for linux-user mode's Armv8.3-PAuth support * Support TBI (top-byte-ignore) properly for linux-user mode * gdbstub: allow killing QEMU via vKill command * hw/arm/boot: Support DTB autoload for firmware-only boots * target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI # gpg: Signature made Tue 05 Feb 2019 17:04:22 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190205: (22 commits) target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI hw/arm/boot: Support DTB autoload for firmware-only boots hw/arm/boot: Clarify why arm_setup_firmware_boot() doesn't set env->boot_info hw/arm/boot: Factor out "set up firmware boot" code hw/arm/boot: Factor out "direct kernel boot" code into its own function hw/arm/boot: Fix block comment style in arm_load_kernel() gdbstub: allow killing QEMU via vKill command target/arm: Enable TBI for user-only target/arm: Compute TB_FLAGS for TBI for user-only target/arm: Clean TBI for data operations in the translator target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignore tests/tcg/aarch64: Add pauth smoke test linux-user: Implement PR_PAC_RESET_KEYS target/arm: Enable BTI for -cpu max target/arm: Set btype for indirect branches target/arm: Reset btype for direct branches target/arm: Default handling of BTYPE during translation target/arm: Cache the GP bit for a page in MemTxAttrs exec: Add target-specific tlb bits to MemTxAttrs target/arm: Add BT and BTYPE to tb->flags ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests/tcg/aarch64/pauth-1.c')
-rw-r--r--tests/tcg/aarch64/pauth-1.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/tests/tcg/aarch64/pauth-1.c b/tests/tcg/aarch64/pauth-1.c
new file mode 100644
index 0000000000..ae6dc05c2b
--- /dev/null
+++ b/tests/tcg/aarch64/pauth-1.c
@@ -0,0 +1,23 @@
+#include <assert.h>
+#include <sys/prctl.h>
+
+asm(".arch armv8.4-a");
+
+#ifndef PR_PAC_RESET_KEYS
+#define PR_PAC_RESET_KEYS 54
+#define PR_PAC_APDAKEY (1 << 2)
+#endif
+
+int main()
+{
+ int x;
+ void *p0 = &x, *p1, *p2;
+
+ asm volatile("pacdza %0" : "=r"(p1) : "0"(p0));
+ prctl(PR_PAC_RESET_KEYS, PR_PAC_APDAKEY, 0, 0, 0);
+ asm volatile("pacdza %0" : "=r"(p2) : "0"(p0));
+
+ assert(p1 != p0);
+ assert(p1 != p2);
+ return 0;
+}