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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-10-31 07:32:15 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-11-02 13:36:45 +0000 |
| commit | b11293c212c2927fcea1befc50dabec9baba4fcc (patch) | |
| tree | 074fa995c448d003c909deaa5f7a609e0b65cd0b /tests/tcg/aarch64/Makefile.target | |
| parent | 854c001f121578c96b023b5db0c5550250505a0e (diff) | |
target/arm: Fix SVE STR increment
The previous change missed updating one of the increments and
one of the MemOps. Add a test case for all vector lengths.
Cc: qemu-stable@nongnu.org
Fixes: e6dd5e782be ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231031143215.29764-1-richard.henderson@linaro.org
[PMM: fixed checkpatch nit]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests/tcg/aarch64/Makefile.target')
| -rw-r--r-- | tests/tcg/aarch64/Makefile.target | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 0c84b61ae0..cded1d01fc 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -103,7 +103,11 @@ sha512-sve: CFLAGS=-O3 -march=armv8.1-a+sve sha512-sve: sha512.c $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) -TESTS += sha512-sve +sve-str: CFLAGS=-O1 -march=armv8.1-a+sve +sve-str: sve-str.c + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) + +TESTS += sha512-sve sve-str ifneq ($(GDB),) GDB_SCRIPT=$(SRC_PATH)/tests/guest-debug/run-test.py |