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authorPeter Maydell <peter.maydell@linaro.org>2024-02-09 16:15:01 +0000
committerPeter Maydell <peter.maydell@linaro.org>2024-02-09 16:15:01 +0000
commitdf50424b4dcfde823047d3717abd6a61224ea205 (patch)
treed414f09a45fad2ed522877328a9c3c1a5dd7d2d3 /tests/qemu-iotests
parent5d1fc614413b10dd94858b07a1b2e26b1aa0296c (diff)
parentdeb0ff0c777d20602ecc5b6f74f18cb7ecc0b91f (diff)
Merge tag 'pull-riscv-to-apply-20240209' of https://github.com/alistair23/qemu into staging
RISC-V PR for 9.0 * Check for 'A' extension on all atomic instructions * Add support for 'B' extension * Internally deprecate riscv_cpu_options * Implement optional CSR mcontext of debug Sdtrig extension * Internally add cpu->cfg.vlenb and remove cpu->cfg.vlen * Support vlenb and vregs[] in KVM * RISC-V gdbstub and TCG plugin improvements * Remove vxrm and vxsat from FCSR * Use RISCVException as return type for all csr ops * Use g_autofree more and fix a memory leak * Add support for Zaamo and Zalrsc * Support new isa extension detection devicetree properties * SMBIOS support for RISC-V virt machine * Enable xtheadsync under user mode * Add rv32i,rv32e and rv64e CPUs # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmXGBRAACgkQr3yVEwxT # gBPqVA//etMiwP8+lQb2E4pw+QwBIzpm3qFyBlqgSCFrekj1u2kYNd4CH3CKurWE # ysoQ6OAMeb0MUbRHdjrejjzD/wOg7JNA9h7ynM1VbupveBrJY3GWC6qQWSG+A1j/ # LSgmr/dDya74chDxjxa+7ld3xqloHi5OtdGaeORfdPXl7mjCCKKCoSKYCex1ykup # uuB7bsjeWeWEbuUsntmeuHJLZJuhpnbuZJmp17tEo+3vWXqjxV00Lik+XMwh3gua # KOLiAqHjGr2NEhA3Mg1JLcQ+6JLTDM9ugZpQeNGQwMkfuB/RAU7jO/1Di3flbadF # 8l2xOHu3mydDbfdxTGZNJjcIrMTX/YEewAYZLRYpNsyPOMntgq8HEegwCdWGvK7C # M5Tc59MNSuBt+zkZkHd21qLYusa2ThP4YT/schh7IA+2F1TSKdhlptEzi2oebIc7 # ilLSgZ9Of72QlAH2OPJNSAL9Nbc06MHEM0JiHIJa5u+XdcVRhZus5h1YIOKXisqF # YPP22RnI5Jj5d5csa/0ONAZGFh5SRMTJtpjKoKSkzoYJWDjCQ2MiUAOmLscchMZd # wbK0vjeRf6kRG4U4z7nTmHS9kzH8RXUZDecVcOITuMpKih9LhUiCZ+xPunFYPycJ # WNFa9/pENcCXJweXvtk4NHwx933rX56678lF6KY2hwUwwaiBOv4= # =yuRM # -----END PGP SIGNATURE----- # gpg: Signature made Fri 09 Feb 2024 10:57:20 GMT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20240209' of https://github.com/alistair23/qemu: (61 commits) target/riscv: add rv32i, rv32e and rv64e CPUs target/riscv/cpu.c: add riscv_bare_cpu_init() target/riscv: Enable xtheadsync under user mode qemu-options: enable -smbios option on RISC-V target/riscv: SMBIOS support for RISC-V virt machine smbios: function to set default processor family smbios: add processor-family option target/riscv: support new isa extension detection devicetree properties target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS target/riscv: Expose Zaamo and Zalrsc extensions target/riscv: Check 'A' and split extensions for atomic instructions target/riscv: Add Zaamo and Zalrsc extension infrastructure hw/riscv/virt.c: use g_autofree in create_fdt_* hw/riscv/virt.c: use g_autofree in virt_machine_init() hw/riscv/virt.c: use g_autofree in create_fdt_virtio() hw/riscv/virt.c: use g_autofree in create_fdt_sockets() hw/riscv/virt.c: use g_autofree in create_fdt_socket_cpus() hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix() hw/riscv/virt-acpi-build.c: fix leak in build_rhct() target/riscv: Use RISCVException as return type for all csr ops ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests/qemu-iotests')
0 files changed, 0 insertions, 0 deletions