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authorPeter Maydell <peter.maydell@linaro.org>2018-06-15 14:57:13 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-06-15 15:23:34 +0100
commit519655e62590f8eaed1a17d159b70be24d74967e (patch)
tree73eaa420e4e5df4921683bc7d7f41e3ebb271806 /tests/qemu-iotests/203.out
parent1dcf3675196a1cec616ce71b067d9498590a60a6 (diff)
hw/arm/mps2-tz: Put ethernet controller behind PPC
The ethernet controller in the AN505 MPC FPGA image is behind the same AHB Peripheral Protection Controller that handles the graphics and GPIOs. (In the documentation this is clear in the block diagram but the ethernet controller was omitted from the table listing devices connected to the PPC.) The ethernet sits behind AHB PPCEXP0 interface 5. We had incorrectly claimed that this was a "gpio4", but there are only 4 GPIOs in this image. Correct the QEMU model to match the hardware. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180515171446.10834-1-peter.maydell@linaro.org
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