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authorPeter Maydell <peter.maydell@linaro.org>2020-07-03 16:58:38 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-07-03 16:58:39 +0100
commit5f42c3375d45108cf14f50ac8ba57c2865e75e9c (patch)
treeb6945c72ea1478a7c13979c75bb5cbc28fa45126 /tests/qapi-schema
parent4abf70a661a5df3886ac9d7c19c3617fa92b922a (diff)
parent6bf91617f47c74efc99ef48236765d9677c0898e (diff)
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200702-1' into staging
This PR contains two patches to improve PLIC support in QEMU. It also contains one patch that fixes CLINT accesses for RISC-V. This fixes a regression for most RISC-V boards. The rest of the PR is adding support for the v0.7.1 RISC-V vector extensions. This is experimental support as the vector extensions are still in a draft state. This is a v2 pull request that has fixed the building on big endian machines failure. # gpg: Signature made Thu 02 Jul 2020 17:21:54 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20200702-1: (64 commits) target/riscv: configure and turn on vector extension from command line target/riscv: vector compress instruction target/riscv: vector register gather instruction target/riscv: vector slide instructions target/riscv: floating-point scalar move instructions target/riscv: integer scalar move instruction target/riscv: integer extract instruction target/riscv: vector element index instruction target/riscv: vector iota instruction target/riscv: set-X-first mask bit target/riscv: vmfirst find-first-set mask bit target/riscv: vector mask population count vmpopc target/riscv: vector mask-register logical instructions target/riscv: vector widening floating-point reduction instructions target/riscv: vector single-width floating-point reduction instructions target/riscv: vector wideing integer reduction instructions target/riscv: vector single-width integer reduction instructions target/riscv: narrowing floating-point/integer type-convert instructions target/riscv: widening floating-point/integer type-convert instructions target/riscv: vector floating-point/integer type-convert instructions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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