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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2022-10-31 13:25:31 +0000 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2022-11-08 01:04:25 +0100 |
| commit | 4bfc895383ed65b83d55a8ae5738a166c1cc48f1 (patch) | |
| tree | bdd821e29392f654103d5e3623ddeda431e653d1 /tests/plugin | |
| parent | 4525ea7e0caa4aa6317204cd977179dea972cf6d (diff) | |
target/mips: Disable DSP ASE for Octeon68XX
I don't have access to Octeon68XX hardware but according
to my investigation Octeon never had DSP ASE support.
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have
access to a Ubiquiti Edgerouter 4 which has Octeon CN7130 processor
and I can confirm CP0C3_DSPP is read as 0 on that processor.
Further more, in linux kernel:
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
cpu_has_dsp is overridden as 0.
So I believe we shouldn't emulate DSP in QEMU as well.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Message-Id: <20221031132531.18122-4-jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'tests/plugin')
0 files changed, 0 insertions, 0 deletions