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authorMichael Clark <mjc@sifive.com>2019-05-17 15:11:06 -0700
committerPalmer Dabbelt <palmer@sifive.com>2019-06-23 23:44:41 -0700
commitcbf5827693addaff4e4d2102afedbf078a204eb2 (patch)
treee857c066240d7706ccd11e822d53aefdd049faec /tests/perf
parent49db9fa1fd7c252596b53cf80876e06f407d09ed (diff)
target/riscv: Implement riscv_cpu_unassigned_access
This patch adds support for the riscv_cpu_unassigned_access call and will raise a load or store access fault. Signed-off-by: Michael Clark <mjc@sifive.com> [Changes by AF: - Squash two patches and rewrite commit message - Set baddr to the access address ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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