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authorPeter Maydell <peter.maydell@linaro.org>2018-09-24 16:46:43 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-09-24 16:46:43 +0100
commitee4402eae1e24f776c2b58dfbe7e26c7a41e06e4 (patch)
tree7d97df05eca44b74337991a0e55a9387f3a811da /tests/machine-none-test.c
parentd5a515738ee2dec0cdf11d8a14a09abae6c20571 (diff)
parent1ca79ece35a5bcdcefb5a2582bc6da91f0640bf2 (diff)
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-pullreq-20180905' into staging
A misc collection of RISC-V related patches for 3.1. # gpg: Signature made Wed 05 Sep 2018 23:06:55 BST # gpg: using RSA key 21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-pullreq-20180905: riscv: remove define cpu_init() hw/riscv/spike: Set the soc device tree node as a simple-bus hw/riscv/virtio: Set the soc device tree node as a simple-bus target/riscv: call gen_goto_tb on DISAS_TOO_MANY target/riscv: optimize indirect branches target/riscv: optimize cross-page direct jumps in softmmu RISC-V: Simplify riscv_cpu_local_irqs_pending RISC-V: Use atomic_cmpxchg to update PLIC bitmaps RISC-V: Improve page table walker spec compliance RISC-V: Update address bits to support sv39 and sv48 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests/machine-none-test.c')
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