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authorDavid Gibson <david@gibson.dropbear.id.au>2016-10-24 15:50:22 +1100
committerDavid Gibson <david@gibson.dropbear.id.au>2016-10-28 09:38:27 +1100
commite7c8526b2a1482a9b14319fda9f8ad4bfda5b958 (patch)
tree7e7810fb220ec79ac40caf01c2000aa6a91e9737 /tests/libqos
parent204e54b86d123d091f0b2d14541c491ece7b864f (diff)
tests: Don't assume structure of PCI IO base in ahci-test
In a couple of places ahci-test makes assumptions about how the tokens returned from qpci_iomap() are formatted in ways it probably shouldn't. First in verify_state() it uses a non-NULL token to indicate that the AHCI device has been enabled (part of enabling is to iomap()). This changes it to use an explicit 'enabled' flag instead. Second, it uses the fact that the token contains a PCI address, stored when the BAR is mapped during initialization to check that the BAR has the same value after a migration. This changes it to explicitly read the BAR register before and after the migration and compare. Together, these changes will make the test more robust against changes to the internals of the libqos PCI layer. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org>
Diffstat (limited to 'tests/libqos')
-rw-r--r--tests/libqos/ahci.c1
-rw-r--r--tests/libqos/ahci.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/tests/libqos/ahci.c b/tests/libqos/ahci.c
index 716ab7939e..8e789d8407 100644
--- a/tests/libqos/ahci.c
+++ b/tests/libqos/ahci.c
@@ -351,6 +351,7 @@ void ahci_hba_enable(AHCIQState *ahci)
reg = ahci_rreg(ahci, AHCI_GHC);
ASSERT_BIT_SET(reg, AHCI_GHC_IE);
+ ahci->enabled = true;
/* TODO: The device should now be idling and waiting for commands.
* In the future, a small test-case to inspect the Register D2H FIS
* and clear the initial interrupts might be good. */
diff --git a/tests/libqos/ahci.h b/tests/libqos/ahci.h
index c69fb5ae90..9b0c1d705b 100644
--- a/tests/libqos/ahci.h
+++ b/tests/libqos/ahci.h
@@ -327,6 +327,7 @@ typedef struct AHCIQState {
uint32_t cap;
uint32_t cap2;
AHCIPortQState port[32];
+ bool enabled;
} AHCIQState;
/**