aboutsummaryrefslogtreecommitdiff
path: root/tests/iothread.c
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2020-08-04 20:39:03 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-08-05 17:31:51 +0100
commita65dabf71a9f9b949d556b1b57fd72595df92398 (patch)
tree30138d0b95100643708b7696fb0015a24c63e031 /tests/iothread.c
parent348fcc4f7ace1718006e646078d88c8cd8c1d97e (diff)
target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64
When a coprocessor instruction in an AArch32 guest traps to AArch32 Hyp mode, the syndrome register (HSR) includes Rt and Rt2 fields which are simply copies of the Rt and Rt2 fields from the trapped instruction. However, if the instruction is trapped from AArch32 to an AArch64 higher exception level, the Rt and Rt2 fields in the syndrome register (ESR_ELx) must be the AArch64 view of the register. This makes a difference if the AArch32 guest was in a mode other than User or System and it was using r13 or r14, or if it was in FIQ mode and using r8-r14. We don't know at translate time which AArch32 CPU mode we are in, so we leave the values we generate in our prototype syndrome register value at translate time as the raw Rt/Rt2 from the instruction, and instead correct them to the AArch64 view when we find we need to take an exception from AArch32 to AArch64 with one of these syndrome values. Fixes: https://bugs.launchpad.net/qemu/+bug/1879587 Reported-by: Julien Freche <julien@bedrocksystems.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200804193903.31240-1-peter.maydell@linaro.org
Diffstat (limited to 'tests/iothread.c')
0 files changed, 0 insertions, 0 deletions