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author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-08 13:32:20 +0000 |
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committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-08 13:32:20 +0000 |
commit | dd43edf4e136bff05cbbb6b42b96c024c591dbb9 (patch) | |
tree | d1f03b9c92753846ba462c5a1583af5106333d58 /tests/cris/check_clrjmp1.s | |
parent | 83fa1010ae342c5ad0392182fcdcce438c71b163 (diff) |
CRIS testsuite, based on the SIM testsuite, by Edgar E. Iglesias.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3365 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'tests/cris/check_clrjmp1.s')
-rw-r--r-- | tests/cris/check_clrjmp1.s | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/tests/cris/check_clrjmp1.s b/tests/cris/check_clrjmp1.s new file mode 100644 index 0000000000..45a7005e24 --- /dev/null +++ b/tests/cris/check_clrjmp1.s @@ -0,0 +1,36 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffff00\n + +; A bug resulting in a non-effectual clear.b discovered running the GCC +; testsuite; jump actually wrote to p0. + + .include "testutils.inc" + + start + jump 1f + nop + .p2align 8 +1: + move.d y,r4 + + .if 0 ;0 == ..asm.arch.cris.v32 +; There was a bug causing this insn to set special register p0 +; (byte-clear) to 8 (low 8 bits of location after insn). + jump [r4+] + .endif + +1: + move.d 0f,r4 + +; The corresponding bug would cause this insn too, to set p0. + jump r4 + nop + quit +0: + moveq -1,r3 + clear.b r3 + checkr3 ffffff00 + quit + +y: + .dword 1b |