diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2013-01-01 18:02:22 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2013-01-31 23:29:27 +0100 |
| commit | f7d2072e25d3592acec4657dae8862facf298e9f (patch) | |
| tree | 7d799c17404cbb21d8c7cc292e0ba825b6afbe49 /tci.c | |
| parent | 321f211707822b4c87f0bb89e4f46586fff43163 (diff) | |
target-mips: fix DSP loads with rd = 0
When rd is 0, which still need to do the actually load to possibly
generate a TLB exception.
Reviewed-by: Eric Johnson <ericj@mips.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tci.c')
0 files changed, 0 insertions, 0 deletions